diff options
| author | Bruno Randolf <br1@einfach.org> | 2017-12-28 16:32:29 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2019-06-03 01:18:05 +0300 |
| commit | fe722d46436afe502ddf1cc023a24b348e809293 (patch) | |
| tree | c541fd30897b74a184e3d42fb0df01f9f15bc74c | |
| parent | a1ffdc59f0c75d29db00d12f827f7d9fd7e1df18 (diff) | |
stm32:l4: rcc: Add helper functions
Add functions for PLL output and 48MHz clock source selection
| -rw-r--r-- | include/libopencm3/stm32/l4/rcc.h | 2 | ||||
| -rw-r--r-- | lib/stm32/l4/rcc.c | 29 |
2 files changed, 31 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/l4/rcc.h b/include/libopencm3/stm32/l4/rcc.h index f49ea7e2..01c34e26 100644 --- a/include/libopencm3/stm32/l4/rcc.h +++ b/include/libopencm3/stm32/l4/rcc.h @@ -962,6 +962,8 @@ void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pl uint32_t rcc_system_clock_source(void); void rcc_set_msi_range(uint32_t msi_range); void rcc_set_msi_range_standby(uint32_t msi_range); +void rcc_pll_output_enable(uint32_t pllout); +void rcc_set_clock48_source(uint32_t clksel); END_DECLS diff --git a/lib/stm32/l4/rcc.c b/lib/stm32/l4/rcc.c index d1fb0c48..86631254 100644 --- a/lib/stm32/l4/rcc.c +++ b/lib/stm32/l4/rcc.c @@ -369,4 +369,33 @@ void rcc_set_msi_range_standby(uint32_t msi_range) RCC_CSR = reg; } +/** Enable PLL Output + * + * - P (RCC_PLLCFGR_PLLPEN) + * - Q (RCC_PLLCFGR_PLLQEN) + * - R (RCC_PLLCFGR_PLLREN) + * + * @param pllout One or more of the definitions above + */ +void rcc_pll_output_enable(uint32_t pllout) +{ + RCC_PLLCFGR |= pllout; +} + +/** Set clock source for 48MHz clock + * + * The 48 MHz clock is derived from one of the four following sources: + * - main PLL VCO (RCC_CCIPR_CLK48SEL_PLL) + * - PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q) + * - MSI clock (RCC_CCIPR_CLK48SEL_MSI) + * - HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48) + * + * @param clksel One of the definitions above + */ +void rcc_set_clock48_source(uint32_t clksel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT); + RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT); +} + /**@}*/ |