stm32: adc-v2: Pull up the two forms of the adc-v2

The adc v2 periph has the same register map, but comes in two flavours, one
supporting injected channels, more watchdogs, per channel sampling times and
so on, and one "simple" version.

Pull up the f3 and f0 portions into the appropriate files, after comparing with
L0 and L4 reference manuals, even if those are not fully landed yet.

1 files changed, 125 insertions, 2 deletions

diff --git a/include/libopencm3/stm32/common/adc_common_v2.h b/include/libopencm3/stm32/common/adc_common_v2.h
index 6acacc86..4c3a9cb7 100644
--- a/include/libopencm3/stm32/common/adc_common_v2.h
+++ b/include/libopencm3/stm32/common/adc_common_v2.h
@@ -35,10 +35,133 @@ specific memorymap.h header before including this header file.*/
 #ifndef LIBOPENCM3_ADC_COMMON_V2_H
 #define LIBOPENCM3_ADC_COMMON_V2_H
 
+/* ----- ADC registers  -----------------------------------------------------*/
+/* ADC interrupt and status register */
+#define ADC_ISR(adc)		MMIO32((adc) + 0x00)
+/* Interrupt Enable Register */
+#define ADC_IER(adc)		MMIO32((adc) + 0x04)
+/* Control Register */
+#define ADC_CR(adc)		MMIO32((adc) + 0x08)
+/* Configuration Register 1 */
+#define ADC_CFGR1(adc)			MMIO32((adc) + 0x0C)
+/* Configuration Register 2 */
+#define ADC_CFGR2(adc)			MMIO32((adc) + 0x10)
+/* Sample Time Register 1 */
+#define ADC_SMPR1(adc)			MMIO32((adc) + 0x14)
+/* Watchdog Threshold Register 1*/
+#define ADC_TR1(adc)			MMIO32((adc) + 0x20)
+/* Regular Data Register */
+#define ADC_DR(adc)			MMIO32((adc) + 0x40)
+/* CALFACT for all but f0 :(*/
+
 /* ADC common (shared) registers */
-#define ADC_CSR(adc)		MMIO32((adc) + 0x300 + 0x0)
 #define ADC_CCR(adc)		MMIO32((adc) + 0x300 + 0x8)
-#define ADC_CDR(adc)		MMIO32((adc) + 0x300 + 0xa)
+
+/* --- Register values -------------------------------------------------------*/
+
+/* ADC_ISR Values -----------------------------------------------------------*/
+
+/* AWD1: Analog watchdog 1 flag */
+#define ADC_ISR_AWD1		(1 << 7)
+#define ADC_ISR_OVR			(1 << 4)
+#define ADC_ISR_EOS			(1 << 3)
+#define ADC_ISR_EOSEQ			ADC_ISR_EOS /* TODO - keep only one? */
+#define ADC_ISR_EOC			(1 << 2)
+#define ADC_ISR_EOSMP			(1 << 1)
+#define ADC_ISR_ADRDY			(1 << 0)
+
+/* ADC_IER Values -----------------------------------------------------------*/
+
+/* AWD1IE: Analog watchdog 1 interrupt enable */
+#define ADC_IER_AWD1IE		(1 << 7)
+/* OVRIE: Overrun interrupt enable */
+#define ADC_IER_OVRIE		(1 << 4)
+/* EOSIE: End of regular sequence of conversions interrupt enable */
+#define ADC_IER_EOSIE		(1 << 3)
+#define ADC_IER_EOSEQIE		ADC_IER_EOSIE /* TODO - keep only one? */
+/* EOCIE: End of regular conversion interrupt enable */
+#define ADC_IER_EOCIE		(1 << 2)
+/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */
+#define ADC_IER_EOSMPIE		(1 << 1)
+/* ADRDYIE : ADC ready interrupt enable */
+#define ADC_IER_ADRDYIE		(1 << 0)
+
+/* ADC_CR Values -----------------------------------------------------------*/
+
+/* ADCAL: ADC calibration */
+#define ADC_CR_ADCAL		(1 << 31)
+/* ADSTP: ADC stop of regular conversion command */
+#define ADC_CR_ADSTP		(1 << 4)
+/* ADSTART: ADC start of regular conversion */
+#define ADC_CR_ADSTART		(1 << 2)
+/* ADDIS: ADC disable command */
+#define ADC_CR_ADDIS		(1 << 1)
+/* ADEN: ADC enable control */
+#define ADC_CR_ADEN		(1 << 0)
+
+/* ADC_CFGR1 Values -----------------------------------------------------------*/
+
+/* AWD1CH[4:0]: Analog watchdog 1 channel selection */
+#define ADC_CFGR1_AWD1CH_SHIFT		26
+#define ADC_CFGR1_AWD1CH			(0x1F << ADC_CFGR1_AWD1CH_SHIFT)
+#define ADC_CFGR1_AWD1CH_VAL(x)		((x) << ADC_CFGR1_AWD1CH_SHIFT)
+
+/* AWD1EN: Analog watchdog 1 enable on regular channels */
+#define ADC_CFGR1_AWD1EN		(1 << 23)
+
+/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */
+#define ADC_CFGR1_AWD1SGL		(1 << 22)
+
+/* DISCEN: Discontinuous mode for regular channels */
+#define ADC_CFGR1_DISCEN		(1 << 16)
+
+/* AUTDLY: Delayed conversion mode */
+#define ADC_CFGR1_AUTDLY		(1 << 14)
+
+/* CONT: Single / continuous conversion mode for regular conversions */
+#define ADC_CFGR1_CONT		(1 << 13)
+
+/* OVRMOD: Overrun Mode */
+#define ADC_CFGR1_OVRMOD		(1 << 12)
+
+/*
+ * EXTEN[1:0]: External trigger enable and polarity selection for regular
+ * channels
+ */
+#define ADC_CFGR1_EXTEN_DISABLED		(0x0 << 10)
+#define ADC_CFGR1_EXTEN_RISING_EDGE	(0x1 << 10)
+#define ADC_CFGR1_EXTEN_FALLING_EDGE	(0x2 << 10)
+#define ADC_CFGR1_EXTEN_BOTH_EDGES	(0x3 << 10)
+
+#define ADC_CFGR1_EXTEN_MASK		(0x3 << 10)
+
+/* ALIGN: Data alignment */
+#define ADC_CFGR1_ALIGN		(1 << 5)
+
+/* RES[1:0]: Data resolution */
+#define ADC_CFGR1_RES_12_BIT	(0x0 << 3)
+#define ADC_CFGR1_RES_10_BIT	(0x1 << 3)
+#define ADC_CFGR1_RES_8_BIT	(0x2 << 3)
+#define ADC_CFGR1_RES_6_BIT	(0x3 << 3)
+#define ADC_CFGR1_RES_MASK	(0x3 << 3)
+
+/* DMACFG: Direct memory access configuration */
+#define ADC_CFGR1_DMACFG		(1 << 1)
+
+/* DMAEN: Direct memory access enable */
+#define ADC_CFGR1_DMAEN		(1 << 0)
+
+/* ADC_TR1 Values ------------------------------------------------------------*/
+
+#define ADC_TR1_LT_SHIFT		0
+#define ADC_TR1_LT			(0xFFF << ADC_TR1_LT_SHIFT)
+#define ADC_TR1_LT_VAL(x)		((x) << ADC_TR1_LT_SHIFT)
+
+#define ADC_TR1_HT_SHIFT		16
+#define ADC_TR1_HT			(0xFFF << ADC_TR1_HT_SHIFT)
+#define ADC_TR1_HT_VAL(x)		((x) << ADC_TR1_HT_SHIFT)
+
+
 
 /* ADC_CCR Values -----------------------------------------------------------*/
 #define ADC_CCR_VBATEN			(1 << 24)