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| author | Piotr Esden-Tempski <piotr@esden.net> | 2013-06-13 04:44:07 +0400 |
|---|---|---|
| committer | Piotr Esden-Tempski <piotr@esden.net> | 2013-06-13 05:22:56 +0400 |
| commit | 7df63fcae0efa62f60f726b3878f1c93506647c3 (patch) | |
| tree | 70e762d48192ce740856c976da5c35087213eb9a /include/libopencm3/stm32/common/hash_common_f24.h | |
| parent | 48e0f3326b8f23787adb41b6c2192d77f2ef5e08 (diff) | |
First coarse run to fix coding style in locm3.
Added --terse and --mailback options to the make stylecheck target. It
also does continue even if it enounters a possible error.
We decided on two exceptions from the linux kernel coding standard:
- Empty wait while loops may end with ; on the same line.
- All blocks after while, if, for have to be in brackets even if they
only contain one statement. Otherwise it is easy to introduce an
error.
Checkpatch needs to be adapted to reflect those changes.
Diffstat (limited to 'include/libopencm3/stm32/common/hash_common_f24.h')
| -rw-r--r-- | include/libopencm3/stm32/common/hash_common_f24.h | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/include/libopencm3/stm32/common/hash_common_f24.h b/include/libopencm3/stm32/common/hash_common_f24.h index 8614ed21..0643f9d0 100644 --- a/include/libopencm3/stm32/common/hash_common_f24.h +++ b/include/libopencm3/stm32/common/hash_common_f24.h @@ -1,6 +1,7 @@ /** @addtogroup hash_defines -@author @htmlonly © @endhtmlonly 2013 Mikhail Avkhimenia <mikhail@avkhimenia.net> +@author @htmlonly © @endhtmlonly 2013 +Mikhail Avkhimenia <mikhail@avkhimenia.net> */ @@ -38,32 +39,32 @@ @ingroup STM32F_hash_defines @{*/ -#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) #define HASH HASH_BASE /**@}*/ /* --- HASH registers ------------------------------------------------------ */ /* HASH control register (HASH_CR) */ -#define HASH_CR MMIO32(HASH + 0x00) +#define HASH_CR MMIO32(HASH + 0x00) /* HASH data input register (HASH_DIR) */ -#define HASH_DIN MMIO32(HASH + 0x04) +#define HASH_DIN MMIO32(HASH + 0x04) /* HASH start register (HASH_STR) */ -#define HASH_STR MMIO32(HASH + 0x08) +#define HASH_STR MMIO32(HASH + 0x08) /* HASH digest registers (HASH_HR[5]) */ -#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) //x5 +#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) /* x5 */ /* HASH interrupt enable register (HASH_IMR) */ -#define HASH_IMR MMIO32(HASH + 0x20) +#define HASH_IMR MMIO32(HASH + 0x20) /* HASH status register (HASH_SR) */ -#define HASH_SR MMIO32(HASH + 0x28) +#define HASH_SR MMIO32(HASH + 0x28) /* HASH context swap registers (HASH_CSR[51]) */ -#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) //x51 +#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) /* x51 */ /* --- HASH_CR values ------------------------------------------------------ */ @@ -127,7 +128,8 @@ /* --- HASH_STR values ----------------------------------------------------- */ -/* NBLW: Number of valid bits in the last word of the message in the bit string */ +/* NBLW: Number of valid bits in the last word of the message in the bit string + */ #define HASH_STR_NBW (31 << 0) /* DCAL: Digest calculation */ @@ -155,7 +157,7 @@ /* BUSY: Busy bit */ #define HASH_SR_BUSY (1 << 3) -/* --- HASH function prototypes ------------------------------------------------------- */ +/* --- HASH function prototypes -------------------------------------------- */ BEGIN_DECLS |