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| author | Karl Palsson <karlp@etactica.com> | 2017-12-07 13:30:11 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@etactica.com> | 2017-12-07 13:33:09 +0300 |
| commit | ef04708e9247cc8a87329b961e0df3a322fc6bf0 (patch) | |
| tree | 69621c240c4adb23e9d1998654797238d6ec3717 /include/libopencm3/stm32/common/pwr_common_v1.h | |
| parent | 297d996fa07ddc09d8528f1d8724e430296d0b91 (diff) | |
stm32: pwr-v1: doxygen-ize bit definitions.
Rich commentary already existed, just add the second * to let doxygen
pick it up.
Diffstat (limited to 'include/libopencm3/stm32/common/pwr_common_v1.h')
| -rw-r--r-- | include/libopencm3/stm32/common/pwr_common_v1.h | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/include/libopencm3/stm32/common/pwr_common_v1.h b/include/libopencm3/stm32/common/pwr_common_v1.h index 273c5dee..524455d5 100644 --- a/include/libopencm3/stm32/common/pwr_common_v1.h +++ b/include/libopencm3/stm32/common/pwr_common_v1.h @@ -37,17 +37,17 @@ specific memorymap.h header before including this header file.*/ /* --- PWR registers ------------------------------------------------------- */ -/* Power control register (PWR_CR) */ +/** Power control register (PWR_CR) */ #define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) -/* Power control/status register (PWR_CSR) */ +/** Power control/status register (PWR_CSR) */ #define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) /* --- PWR_CR values ------------------------------------------------------- */ /* Bits [31:9]: Reserved, must be kept at reset value. */ -/* DBP: Disable backup domain write protection */ +/** DBP: Disable backup domain write protection */ #define PWR_CR_DBP (1 << 8) /* PLS[7:5]: PVD level selection */ @@ -67,37 +67,37 @@ specific memorymap.h header before including this header file.*/ /**@}*/ #define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) -/* PVDE: Power voltage detector enable */ +/** PVDE: Power voltage detector enable */ #define PWR_CR_PVDE (1 << 4) -/* CSBF: Clear standby flag */ +/** CSBF: Clear standby flag */ #define PWR_CR_CSBF (1 << 3) -/* CWUF: Clear wakeup flag */ +/** CWUF: Clear wakeup flag */ #define PWR_CR_CWUF (1 << 2) -/* PDDS: Power down deepsleep */ +/** PDDS: Power down deepsleep */ #define PWR_CR_PDDS (1 << 1) -/* LPDS: Low-power deepsleep */ +/** LPDS: Low-power deepsleep */ #define PWR_CR_LPDS (1 << 0) /* --- PWR_CSR values ------------------------------------------------------ */ /* Bits [31:9]: Reserved, must be kept at reset value. */ -/* EWUP: Enable WKUP pin */ +/** EWUP: Enable WKUP pin */ #define PWR_CSR_EWUP (1 << 8) /* Bits [7:3]: Reserved, must be kept at reset value. */ -/* PVDO: PVD output */ +/** PVDO: PVD output */ #define PWR_CSR_PVDO (1 << 2) -/* SBF: Standby flag */ +/** SBF: Standby flag */ #define PWR_CSR_SBF (1 << 1) -/* WUF: Wakeup flag */ +/** WUF: Wakeup flag */ #define PWR_CSR_WUF (1 << 0) /* --- PWR function prototypes ------------------------------------------- */ |