[STM32F3] Removed all specific F3 stuff out of common files.

1 files changed, 2 insertions, 89 deletions

diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h
index fdde5b6e..6fc25599 100644
--- a/include/libopencm3/stm32/common/spi_common_all.h
+++ b/include/libopencm3/stm32/common/spi_common_all.h
@@ -129,33 +129,6 @@ specific memorymap.h header before including this header file.*/
 /* CRCNEXT: Transmit CRC next */
 #define SPI_CR1_CRCNEXT			(1 << 12)
 
-/* DFF: Data frame format */
-/****************************************************************************/
-/** @defgroup spi_dff SPI data frame format
-@ingroup spi_defines
-
-@{*/
-#if defined(STM32F3)
-
-#define SPI_DR8(spi_base)		MMIO8(spi_base + 0x0c)
-#define SPI1_DR8			SPI_DR8(SPI1_BASE)
-#define SPI2_DR8			SPI_DR8(SPI2_I2S_BASE)
-#define SPI3_DR8			SPI_DR8(SPI3_I2S_BASE)
-
-#define SPI_CR1_CRCL_8BIT		(0 << 11)
-#define SPI_CR1_CRCL_16BIT		(1 << 11)
-/**@}*/
-#define SPI_CR1_CRCL			(1 << 11)
-
-#elif !defined(STM32F3)
-
-#define SPI_CR1_DFF_8BIT		(0 << 11)
-#define SPI_CR1_DFF_16BIT		(1 << 11)
-/**@}*/
-#define SPI_CR1_DFF			(1 << 11)
-
-#endif
-
 /* RXONLY: Receive only */
 #define SPI_CR1_RXONLY			(1 << 10)
 
@@ -235,41 +208,7 @@ specific memorymap.h header before including this header file.*/
 
 /* --- SPI_CR2 values ------------------------------------------------------ */
 
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-#if defined(STM32F3)
-
-/* LDMA_TX: Last DMA transfer for transmission */
-#define SPI_CR2_LDMA_TX			(1 << 14)
-
-/* LDMA_RX: Last DMA transfer for reception */
-#define SPI_CR2_LDMA_RX			(1 << 13)
-
-/* FRXTH: FIFO reception threshold */
-#define SPI_CR2_FRXTH			(1 << 12)
-
-/* DS [3:0]: Data size */
-// 0x0 - 0x2 NOT USED
-#define SPI_CR2_DS_4BIT			(0x3 << 8)
-#define SPI_CR2_DS_5BIT			(0x4 << 8)
-#define SPI_CR2_DS_6BIT			(0x5 << 8)
-#define SPI_CR2_DS_7BIT			(0x6 << 8)
-#define SPI_CR2_DS_8BIT			(0x7 << 8)
-#define SPI_CR2_DS_9BIT			(0x8 << 8)
-#define SPI_CR2_DS_10BIT		(0x9 << 8)
-#define SPI_CR2_DS_11BIT		(0xA << 8)
-#define SPI_CR2_DS_12BIT		(0xB << 8)
-#define SPI_CR2_DS_13BIT		(0xC << 8)
-#define SPI_CR2_DS_14BIT		(0xD << 8)
-#define SPI_CR2_DS_15BIT		(0xE << 8)
-#define SPI_CR2_DS_16BIT		(0xF << 8)
-#define SPI_CR2_DS_MASK                 (0xF << 8)
-
-
-/* NSSP: NSS pulse management */
-#define SPI_CR2_NSSP			(1 << 3)
-
-#endif
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */
 
 /* TXEIE: Tx buffer empty interrupt enable */
 #define SPI_CR2_TXEIE			(1 << 7)
@@ -294,23 +233,7 @@ specific memorymap.h header before including this header file.*/
 
 /* --- SPI_SR values ------------------------------------------------------- */
 
-/* Bits [15:8]: Reserved. Forced to 0 by hardware. */
-
-#if defined(STM32F3)
-
-/* FTLVL[1:0]: FIFO Transmission Level */
-#define SPI_SR_FTLVL_FIFO_EMPTY		(0x0 << 11)
-#define SPI_SR_FTLVL_QUARTER_FIFO	(0x1 << 11)
-#define SPI_SR_FTLVL_HALF_FIFO		(0x2 << 11)
-#define SPI_SR_FTLVL_FIFO_FULL		(0x3 << 11)
-
-/* FRLVL[1:0]: FIFO Reception Level */
-#define SPI_SR_FRLVL_FIFO_EMPTY		(0x0 << 9)
-#define SPI_SR_FRLVL_QUARTER_FIFO	(0x1 << 9)
-#define SPI_SR_FRLVL_HALF_FIFO		(0x2 << 9)
-#define SPI_SR_FRLVL_FIFO_FULL		(0x3 << 9)
-
-#endif
+/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */
 
 /* BSY: Busy flag */
 #define SPI_SR_BSY			(1 << 7)
@@ -469,16 +392,6 @@ void spi_disable_tx_dma(uint32_t spi);
 void spi_enable_rx_dma(uint32_t spi);
 void spi_disable_rx_dma(uint32_t spi);
 
-#ifdef STM32F3
-void spi_set_data_size(uint32_t spi, uint16_t data_s);
-void spi_fifo_reception_threshold_8bit(uint32_t spi);
-void spi_fifo_reception_threshold_16bit(uint32_t spi);
-void spi_i2s_mode_spi_mode(uint32_t spi);
-void spi_send8(uint32_t spi, uint8_t data);
-uint8_t spi_read8(uint32_t spi);
-
-#endif
-
 END_DECLS
 
 /**@}*/