diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2017-10-26 02:03:48 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2017-10-26 02:03:48 +0300 |
| commit | a23d65e7dd96d047f91af00282e91a310b8e8db7 (patch) | |
| tree | 1a90d666127808f5b86e40c5dc7b65505d0af3bf /include/libopencm3/stm32/common/usart_common_v2.h | |
| parent | b20d0ff1fbec06d8fb23e4651bbde9379fc39e40 (diff) | |
stm32: usart-v2: pull up remaining f3/f0 defns
Final chunk of register definitions to be pulled up.
Now the "target" files are _only_ defining the list of u(s)arts
available, and any _specific_ functions for that target.
Diffstat (limited to 'include/libopencm3/stm32/common/usart_common_v2.h')
| -rw-r--r-- | include/libopencm3/stm32/common/usart_common_v2.h | 29 |
1 files changed, 27 insertions, 2 deletions
diff --git a/include/libopencm3/stm32/common/usart_common_v2.h b/include/libopencm3/stm32/common/usart_common_v2.h index 64f43fe0..ea98252a 100644 --- a/include/libopencm3/stm32/common/usart_common_v2.h +++ b/include/libopencm3/stm32/common/usart_common_v2.h @@ -231,9 +231,15 @@ /** RTOIE: Receiver timeout interrupt enable */ #define USART_CR1_RTOIE (1 << 26) -/* DEAT[4:0]: Driver Enable assertion time */ +#define USART_CR1_DEAT_SHIFT 21 +#define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT) +/** DEAT[4:0]: Driver Enable assertion time */ +#define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT) -/* DEDT[4:0]: Driver Enable deassertion time */ +#define USART_CR1_DEDT_SHIFT 16 +#define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT) +/** DEDT[4:0]: Driver Enable deassertion time */ +#define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT) /** OVER8: Oversampling mode */ #define USART_CR1_OVER8 (1 << 15) @@ -368,6 +374,12 @@ #define USART_CR3_WUS_START_BIT (0x2 << 20) #define USART_CR3_WUS_RXNE (0x3 << 20) +#define USART_CR3_SCARCNT_SHIFT 17 +#define USART_CR3_SCARCNT_MASK 0x7 +/** SCARCNT[2:0]: Smartcard auto retry count */ +#define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT) + /** DEP: Driver enable polarity selection */ #define USART_CR3_DEP (1 << 15) @@ -418,6 +430,19 @@ /**@}*/ +/** @defgroup usart_gtpr_values USART_GTPR Values + * @ingroup usart_defines + * @{ + */ +#define USART_GTPR_GT_SHIFT 8 +#define USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT) +#define USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT) + +#define USART_GTPR_PSC_SHIFT 0 +#define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT) +/**@}*/ + /* ------------------------------------------------------ */ /** @defgroup usart_rtor_values USART_RTOR Values * @ingroup usart_defines |