Merge remote-tracking branch 'origin/master' into master-gitlab

16 files changed, 1932 insertions, 0 deletions

diff --git a/include/libopencm3/stm32/g0/crc.h b/include/libopencm3/stm32/g0/crc.h
new file mode 100644
index 00000000..43d689d9
--- /dev/null
+++ b/include/libopencm3/stm32/g0/crc.h
@@ -0,0 +1,31 @@
+/** @defgroup crc_defines CRC Defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx CRC Generator </b>
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_CRC_H
+#define LIBOPENCM3_CRC_H
+
+#include <libopencm3/stm32/common/crc_v2.h>
+
+#endif
diff --git a/include/libopencm3/stm32/g0/doc-stm32g0.h b/include/libopencm3/stm32/g0/doc-stm32g0.h
new file mode 100644
index 00000000..66243cac
--- /dev/null
+++ b/include/libopencm3/stm32/g0/doc-stm32g0.h
@@ -0,0 +1,36 @@
+/** @page libopencm3 STM32G0
+
+@version 1.0.0
+
+@date 30 January 2019
+
+API documentation for ST Microelectronics STM32G0 Cortex M0+ series
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup peripheral_apis Peripheral APIs
+ * APIs for device peripherals
+ */
+
+/** @defgroup STM32G0xx STM32G0xx
+Libraries for ST Microelectronics STM32G0xx series.
+
+@version 1.0.0
+
+@date 30 January 2019
+
+LGPL License Terms @ref lgpl_license
+*/
+
+/** @defgroup STM32G0xx_defines STM32G0xx Defines
+
+@brief Defined Constants and Types for the STM32G0xx series
+
+@version 1.0.0
+
+@date 30 January 2019
+
+LGPL License Terms @ref lgpl_license
+*/
+
diff --git a/include/libopencm3/stm32/g0/exti.h b/include/libopencm3/stm32/g0/exti.h
new file mode 100644
index 00000000..88a1c01b
--- /dev/null
+++ b/include/libopencm3/stm32/g0/exti.h
@@ -0,0 +1,85 @@
+/** @defgroup exti_defines EXTI Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx EXTI Control</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+#ifndef LIBOPENCM3_EXTI_H
+#define LIBOPENCM3_EXTI_H
+
+#include <libopencm3/stm32/common/exti_common_all.h>
+
+/* --- EXTI registers ------------------------------------------------------ */
+#define EXTI_RTSR1			MMIO32(EXTI_BASE + 0x00)
+#define EXTI_RTSR			EXTI_RTSR1
+
+#define EXTI_FTSR1			MMIO32(EXTI_BASE + 0x04)
+#define EXTI_FTSR			EXTI_FTSR1
+
+#define EXTI_SWIER1			MMIO32(EXTI_BASE + 0x08)
+#define EXTI_RPR1			MMIO32(EXTI_BASE + 0x0c)
+#define EXTI_FPR1			MMIO32(EXTI_BASE + 0x10)
+
+#define EXTI_EXTICR(i)		MMIO32(EXTI_BASE + 0x60 + (i)*4)
+#define EXTI_EXTICR1		MMIO32(EXTI_BASE + 0x60)
+#define EXTI_EXTICR2		MMIO32(EXTI_BASE + 0x64)
+#define EXTI_EXTICR3		MMIO32(EXTI_BASE + 0x68)
+#define EXTI_EXTICR4		MMIO32(EXTI_BASE + 0x6c)
+
+#define EXTI_IMR1			MMIO32(EXTI_BASE + 0x80)
+#define EXTI_IMR			EXTI_IMR1
+
+#define EXTI_EMR1			MMIO32(EXTI_BASE + 0x84)
+#define EXTI_EMR			EXTI_EMR1
+
+#define EXTI_IMR2			MMIO32(EXTI_BASE + 0x90)
+#define EXTI_EMR2			MMIO32(EXTI_BASE + 0x94)
+
+/* --- EXTI_EXTICR Values -------------------------------------------------*/
+
+#define EXTI_EXTICR_FIELDSIZE		8
+#define EXTI_EXTICR_GPIOA		0
+#define EXTI_EXTICR_GPIOB		1
+#define EXTI_EXTICR_GPIOC		2
+#define EXTI_EXTICR_GPIOD		3
+#define EXTI_EXTICR_GPIOF		5
+
+BEGIN_DECLS
+
+uint32_t exti_get_rising_flag_status(uint32_t exti);
+uint32_t exti_get_falling_flag_status(uint32_t exti);
+
+void exti_reset_rising_request(uint32_t extis);
+void exti_reset_falling_request(uint32_t extis);
+
+END_DECLS
+
+#else
+/** @cond */
+#warning "exti_common_v1.h should not be included directly, only via exti.h"
+#endif
+/** @endcond */
+
+/**@}*/
diff --git a/include/libopencm3/stm32/g0/flash.h b/include/libopencm3/stm32/g0/flash.h
new file mode 100644
index 00000000..63fded55
--- /dev/null
+++ b/include/libopencm3/stm32/g0/flash.h
@@ -0,0 +1,201 @@
+/** @defgroup flash_defines FLASH Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx Flash Control</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+#ifndef LIBOPENCM3_FLASH_H
+#define LIBOPENCM3_FLASH_H
+
+#include <libopencm3/stm32/common/flash_common_all.h>
+
+/** @defgroup flash_registers FLASH Registers
+@{*/
+#define FLASH_ACR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
+#define FLASH_KEYR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
+#define FLASH_OPTKEYR		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0c)
+#define FLASH_SR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
+#define FLASH_CR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
+#define FLASH_ECCR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
+#define FLASH_OPTR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
+#define FLASH_PCROP1ASR		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24)
+#define FLASH_PCROP1AER		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28)
+#define FLASH_WRP1AR		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2c)
+#define FLASH_WRP1BR		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30)
+#define FLASH_PCROP1BSR		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x34)
+#define FLASH_PCROP1BER		MMIO32(FLASH_MEM_INTERFACE_BASE + 0x38)
+#define FLASH_SECR			MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80)
+/**@}*/
+
+/* --- FLASH_ACR values ----------------------------------------------------- */
+
+#define FLASH_ACR_DBG_SWEN		(1 << 18)
+#define FLASH_ACR_EMPTY			(1 << 16)
+#define FLASH_ACR_ICRST			(1 << 11)
+#define FLASH_ACR_ICEN			(1 << 9)
+#define FLASH_ACR_PRFTEN		(1 << 8)
+
+#define FLASH_ACR_LATENCY_SHIFT		0
+#define FLASH_ACR_LATENCY_MASK		0x7
+/** @defgroup flash_latency FLASH Wait States
+ * @brief Flash memory access latency. flash HCLK max freq for 0ws is 24mhz (range 1 voltage) / 8mhz (range 0), 48mhz/16mhz for 1ws and 64mhz for 2ws.
+@{*/
+#define FLASH_ACR_LATENCY_0WS		0x00
+#define FLASH_ACR_LATENCY_1WS		0x01
+#define FLASH_ACR_LATENCY_2WS		0x02
+/**@}*/
+
+/* --- FLASH_KEYR values ---------------------------------------------------- */
+
+#define FLASH_KEYR_KEY1			((uint32_t)0x08192a3b)
+#define FLASH_KEYR_KEY2			((uint32_t)0x4c5d6e7f)
+
+#define FLASH_OPTKEYR_KEY1		FLASH_KEYR_KEY1
+#define FLASH_OPTKEYR_KEY2		FLASH_KEYR_KEY2
+
+/* --- FLASH_SR values ------------------------------------------------------ */
+#define FLASH_SR_CFGBSY			(1 << 18)
+#define FLASH_SR_BSY			(1 << 16)
+#define FLASH_SR_OPTVERR		(1 << 15)
+#define FLASH_SR_RDERR			(1 << 14)
+#define FLASH_SR_FASTERR		(1 << 9)
+#define FLASH_SR_MISERR			(1 << 8)
+#define FLASH_SR_PGSERR			(1 << 7)
+#define FLASH_SR_SIZERR			(1 << 6)
+#define FLASH_SR_PGAERR			(1 << 5)
+#define FLASH_SR_WRPERR			(1 << 4)
+#define FLASH_SR_PROGERR		(1 << 3)
+#define FLASH_SR_OPERR			(1 << 1)
+#define FLASH_SR_EOP			(1 << 0)
+
+/* --- FLASH_CR values ------------------------------------------------------ */
+
+#define FLASH_CR_LOCK			(1 << 31)
+#define FLASH_CR_OPTLOCK		(1 << 30)
+#define FLASH_CR_SEC_PROT		(1 << 28)
+#define FLASH_CR_OBL_LAUNCH		(1 << 27)
+#define FLASH_CR_RDERRIE		(1 << 26)
+#define FLASH_CR_ERRIE			(1 << 25)
+#define FLASH_CR_EOPIE			(1 << 24)
+#define FLASH_CR_FSTPG			(1 << 18)
+#define FLASH_CR_OPTSTRT		(1 << 17)
+#define FLASH_CR_STRT			(1 << 16)
+
+#define FLASH_CR_PNB_SHIFT		3
+#define FLASH_CR_PNB_MASK		0x3f
+
+#define FLASH_CR_MER			(1 << 2)
+#define FLASH_CR_PER			(1 << 1)
+#define FLASH_CR_PG				(1 << 0)
+
+/* --- FLASH_ECCR values ---------------------------------------------------- */
+
+#define FLASH_ECCR_ECCD				(1 << 31)
+#define FLASH_ECCR_ECCC				(1 << 30)
+#define FLASH_ECCR_ECCIE			(1 << 24)
+#define FLASH_ECCR_SYSF_ECC			(1 << 20)
+#define FLASH_ECCR_ADDR_ECC_SHIFT	0
+#define FLASH_ECCR_ADDR_ECC_MASK	0x3fff
+/* --- FLASH_OPTR values ---------------------------------------------------- */
+
+#define FLASH_OPTR_IRHEN			(1 << 29)
+
+#define FLASH_OPTR_NRST_MODE_SHIFT	27
+#define FLASH_OPTR_NRST_MODE_MASK	0x03
+/** @defgroup flash_optr_nrst_mode NRST MODE
+* @brief NRST_MODE
+@{*/
+#define FLASH_OPTR_NRST_MODE_RESET	1
+#define FLASH_OPTR_NRST_MODE_GPIO	2
+#define FLASH_OPTR_NRST_MODE_BIDIR	3
+/**@}*/
+
+#define FLASH_OPTR_nBOOT0			(1 << 26)
+#define FLASH_OPTR_nBOOT1			(1 << 25)
+#define FLASH_OPTR_nBOOT_SEL		(1 << 24)
+#define FLASH_OPTR_RAM_PARITY_CHECK	(1 << 22)
+#define FLASH_OPTR_WWDG_SW			(1 << 19)
+#define FLASH_OPTR_IWDG_STDBY		(1 << 18)
+#define FLASH_OPTR_IWDG_STOP		(1 << 17)
+#define FLASH_OPTR_IDWG_SW			(1 << 16)
+#define FLASH_OPTR_nRSTS_HDW		(1 << 15)
+#define FLASH_OPTR_nRST_STDBY		(1 << 14)
+#define FLASH_OPTR_nRST_STOP		(1 << 13)
+
+#define FLASH_OPTR_BORR_LEV_SHIFT	11
+#define FLASH_OPTR_BORR_LEV_MASK	0x03
+/** @defgroup flash_optr_borr_lev BORR LEV
+* @brief These bits contain the VDD supply level threshold that releases the reset.
+@{*/
+#define FLASH_OPTR_BORR_LEV_2V1		0
+#define FLASH_OPTR_BORR_LEV_2V3		1
+#define FLASH_OPTR_BORR_LEV_2V6		2
+#define FLASH_OPTR_BORR_LEV_2V9		3
+/**@}*/
+
+#define FLASH_OPTR_BORF_LEV_SHIFT	9
+#define FLASH_OPTR_BORF_LEV_MASK	0x03
+/** @defgroup flash_optr_borf_lev BOR FLEV
+* @brief These bits contain the VDD supply level threshold that activates the reset
+@{*/
+#define FLASH_OPTR_BORF_LEV_2V0		0
+#define FLASH_OPTR_BORF_LEV_2V2		1
+#define FLASH_OPTR_BORF_LEV_2V5		2
+#define FLASH_OPTR_BORF_LEV_2V8		3
+/**@}*/
+
+#define FLASH_OPTR_BOREN			(1 << 8)
+
+#define FLASH_OPTR_RDP_SHIFT		0
+#define FLASH_OPTR_RDP_MASK			0xff
+/** @defgroup flash_optr_rdp RDP
+* @brief Read protection level
+@{*/
+#define FLASH_OPTR_RDP_LEVEL_0		0xAA
+#define FLASH_OPTR_RDP_LEVEL_1		0xBB
+#define FLASH_OPTR_RDP_LEVEL_2		0xCC /* or any other value. */
+/**@}*/
+
+BEGIN_DECLS
+
+/** Enable instruction cache */
+void flash_icache_enable(void);
+/** Disable instruction cache */
+void flash_icache_disable(void);
+/** Reset instruction cache */
+void flash_icache_reset(void);
+
+/** Unlock program memory */
+void flash_unlock_progmem(void);
+/** lock program memory */
+void flash_lock_progmem(void);
+
+/** Lock Option Byte Access */
+void flash_lock_option_bytes(void);
+
+END_DECLS
+
+#endif
+/**@}*/
diff --git a/include/libopencm3/stm32/g0/gpio.h b/include/libopencm3/stm32/g0/gpio.h
new file mode 100644
index 00000000..1b8357da
--- /dev/null
+++ b/include/libopencm3/stm32/g0/gpio.h
@@ -0,0 +1,75 @@
+/** @defgroup gpio_defines GPIO Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx General Purpose I/O</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/common/gpio_common_f24.h>
+
+/*****************************************************************************/
+/* Module definitions                                                        */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* Register definitions                                                      */
+/*****************************************************************************/
+
+#define GPIO_BRR(port)			MMIO32((port) + 0x28)
+#define GPIOA_BRR			GPIO_BRR(GPIOA)
+#define GPIOB_BRR			GPIO_BRR(GPIOB)
+#define GPIOC_BRR			GPIO_BRR(GPIOC)
+#define GPIOD_BRR			GPIO_BRR(GPIOD)
+#define GPIOE_BRR			GPIO_BRR(GPIOE)
+#define GPIOF_BRR			GPIO_BRR(GPIOF)
+
+/*****************************************************************************/
+/* Register values                                                           */
+/*****************************************************************************/
+
+/** @defgroup gpio_speed GPIO Output Pin Speed
+@{*/
+#define GPIO_OSPEED_LOW		0x0
+#define GPIO_OSPEED_MED		0x1
+#define GPIO_OSPEED_HIGH	0x2
+#define GPIO_OSPEED_VERYHIGH	0x3
+/**@}*/
+
+/*****************************************************************************/
+/* API definitions                                                           */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* API Functions                                                             */
+/*****************************************************************************/
+
+BEGIN_DECLS
+
+END_DECLS
+
+#endif
+/**@}*/
diff --git a/include/libopencm3/stm32/g0/i2c.h b/include/libopencm3/stm32/g0/i2c.h
new file mode 100644
index 00000000..d91cc779
--- /dev/null
+++ b/include/libopencm3/stm32/g0/i2c.h
@@ -0,0 +1,34 @@
+/** @defgroup i2c_defines I2C Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx I2C</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_I2C_H
+#define LIBOPENCM3_I2C_H
+
+#include <libopencm3/stm32/common/i2c_common_v2.h>
+
+#endif
+
diff --git a/include/libopencm3/stm32/g0/irq.json b/include/libopencm3/stm32/g0/irq.json
new file mode 100644
index 00000000..aa43cbc1
--- /dev/null
+++ b/include/libopencm3/stm32/g0/irq.json
@@ -0,0 +1,39 @@
+{
+    "irqs": [
+        "wwdg", 
+        "pvd",
+        "rtc", 
+        "flash", 
+        "rcc", 
+        "exti0_1", 
+        "exti2_3", 
+        "exti4_15", 
+        "ucpd1_ucpd2", 
+        "dma1_channel1", 
+        "dma1_channel2_3", 
+        "dma1_channel4_7_dmamux", 
+        "adc_comp", 
+        "tim1_brk_up_trg_com", 
+        "tim1_cc",
+        "tim2", 
+        "tim3", 
+        "tim6_dac_lptim1", 
+        "tim7_lptim2",
+        "tim14", 
+        "tim15", 
+        "tim16",
+        "tim17", 
+        "i2c1", 
+        "i2c2", 
+        "spi1", 
+        "spi2", 
+        "usart1", 
+        "usart2", 
+        "usart3_usart4_lpuart1",
+        "cec", 
+        "aes_rng"
+    ], 
+    "partname_humanreadable": "STM32 G0 series", 
+    "partname_doxygen": "STM32G0", 
+    "includeguard": "LIBOPENCM3_STM32_G0_NVIC_H"
+}
diff --git a/include/libopencm3/stm32/g0/iwdg.h b/include/libopencm3/stm32/g0/iwdg.h
new file mode 100644
index 00000000..76af04bb
--- /dev/null
+++ b/include/libopencm3/stm32/g0/iwdg.h
@@ -0,0 +1,33 @@
+/** @defgroup iwdg_defines IWDG Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx Independent Watchdog Timer</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_IWDG_H
+#define LIBOPENCM3_IWDG_H
+
+#include <libopencm3/stm32/common/iwdg_common_v2.h>
+
+#endif
diff --git a/include/libopencm3/stm32/g0/lptimer.h b/include/libopencm3/stm32/g0/lptimer.h
new file mode 100644
index 00000000..e3606d7c
--- /dev/null
+++ b/include/libopencm3/stm32/g0/lptimer.h
@@ -0,0 +1,70 @@
+/** @defgroup lptimer_defines LPTIM Defines
+ *
+ * @ingroup STM32G0xx_defines
+ * 
+ * @brief <b>libopencm3 Defined Constants and Types for the STM32G0xx Low Power Timer</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_LPTIMER_H
+#define LIBOPENCM3_LPTIMER_H
+/**@{*/
+
+#include <libopencm3/stm32/common/lptimer_common_all.h>
+
+/** @defgroup lptim_reg_base Low Power Timer register base addresses
+@{*/
+#define LPTIM1				LPTIM1_BASE
+#define LPTIM2				LPTIM2_BASE
+/**@}*/
+
+/** LPTIM_CFGR2 LPTIM configuration register 2 */
+#define LPTIM_CFGR2(tim_base)			MMIO32((tim_base) + 0x24)
+
+/** @addtogroup lptim_cr
+@{*/
+/** COUNTRST Counter reset **/
+#define LPTIM_CR_COUNTRST		(1 << 3)
+/** RSTARE Reset after read enable **/
+#define LPTIM_CR_RSTARE		(1 << 4)
+/**@}*/
+
+/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2
+@{*/
+
+#define LPTIM_CFGR2_IN2SEL_SHIFT	4
+#define LPTIM_CFGR2_IN2SEL_MASK		0x03
+
+#define LPTIM_CFGR2_IN1SEL_SHIFT	0
+#define LPTIM_CFGR2_IN1SEL_MASK		0x03
+
+/**@}*/
+
+
+BEGIN_DECLS
+
+END_DECLS
+
+/**@}*/
+#endif
diff --git a/include/libopencm3/stm32/g0/memorymap.h b/include/libopencm3/stm32/g0/memorymap.h
new file mode 100644
index 00000000..d6069ccc
--- /dev/null
+++ b/include/libopencm3/stm32/g0/memorymap.h
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+#define PERIPH_BASE			(0x40000000U)
+#define IOPORT_BASE			(0x50000000U)
+#define INFO_BASE			(0x1fff7500U)
+#define PERIPH_BASE_APB			(PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_AHB			(PERIPH_BASE + 0x20000)
+
+/* APB */
+#define TIM2_BASE			(PERIPH_BASE_APB + 0x0000)
+#define TIM3_BASE			(PERIPH_BASE_APB + 0x0400)
+#define TIM6_BASE			(PERIPH_BASE_APB + 0x1000)
+#define TIM7_BASE			(PERIPH_BASE_APB + 0x1400)
+#define TIM14_BASE			(PERIPH_BASE_APB + 0x2000)
+#define RTC_BASE			(PERIPH_BASE_APB + 0x2800)
+#define WWDG_BASE			(PERIPH_BASE_APB + 0x2c00)
+#define IWDG_BASE			(PERIPH_BASE_APB + 0x3000)
+#define SPI2_BASE			(PERIPH_BASE_APB + 0x3800)
+#define USART2_BASE			(PERIPH_BASE_APB + 0x4400)
+#define USART3_BASE			(PERIPH_BASE_APB + 0x4800)
+#define USART4_BASE			(PERIPH_BASE_APB + 0x4C00)
+#define I2C1_BASE			(PERIPH_BASE_APB + 0x5400)
+#define I2C2_BASE			(PERIPH_BASE_APB + 0x5800)
+#define POWER_CONTROL_BASE		(PERIPH_BASE_APB + 0x7000)
+#define DAC_BASE			(PERIPH_BASE_APB + 0x7400)
+#define CEC_BASE			(PERIPH_BASE_APB + 0x7800)
+#define LPTIM1_BASE			(PERIPH_BASE_APB + 0x7c00)
+#define LPUART1_BASE			(PERIPH_BASE_APB + 0x8000)
+#define LPTIM2_BASE			(PERIPH_BASE_APB + 0x9400)
+#define UCPD1_BASE			(PERIPH_BASE_APB + 0xA000)
+#define UCPD2_BASE			(PERIPH_BASE_APB + 0xA400)
+#define TAMP_BASE			(PERIPH_BASE_APB + 0xB000)
+#define SYSCFG_BASE			(PERIPH_BASE_APB + 0x10000)
+#define VREFBUF_BASE		(PERIPH_BASE_APB + 0x10030)
+#define SYSCFG_ITLINE_BASE	(PERIPH_BASE_APB + 0x10080)
+#define COMP_BASE			(PERIPH_BASE_APB + 0x10200)
+#define ADC1_BASE			(PERIPH_BASE_APB + 0x12400)
+#define TIM1_BASE			(PERIPH_BASE_APB + 0x12C00)
+#define SPI1_BASE			(PERIPH_BASE_APB + 0x13000)
+#define USART1_BASE			(PERIPH_BASE_APB + 0x13800)
+#define TIM15_BASE			(PERIPH_BASE_APB + 0x14000)
+#define TIM16_BASE			(PERIPH_BASE_APB + 0x14400)
+#define TIM17_BASE			(PERIPH_BASE_APB + 0x14800)
+#define DBGMCU_BASE			(PERIPH_BASE_APB + 0x15800)
+
+/* AHB */
+#define DMA1_BASE			(PERIPH_BASE_AHB + 0x00000)
+#define DMAMUX_BASE			(PERIPH_BASE_AHB + 0x00800)
+#define RCC_BASE			(PERIPH_BASE_AHB + 0x01000)
+#define EXTI_BASE			(PERIPH_BASE_AHB + 0x01800)
+#define FLASH_MEM_INTERFACE_BASE	(PERIPH_BASE_AHB + 0x02000)
+#define CRC_BASE			(PERIPH_BASE_AHB + 0x03000)
+#define RNG_BASE			(PERIPH_BASE_AHB + 0x05000)
+#define AES_BASE			(PERIPH_BASE_AHB + 0x06000)
+
+#define GPIO_PORT_A_BASE		(IOPORT_BASE + 0x00000)
+#define GPIO_PORT_B_BASE		(IOPORT_BASE + 0x00400)
+#define GPIO_PORT_C_BASE		(IOPORT_BASE + 0x00800)
+#define GPIO_PORT_D_BASE		(IOPORT_BASE + 0x00c00)
+#define GPIO_PORT_E_BASE		(IOPORT_BASE + 0x01000)
+#define GPIO_PORT_F_BASE		(IOPORT_BASE + 0x01400)
+
+/* ST provided factory calibration values @ 3.0V */
+#define ST_VREFINT_CAL			MMIO16((INFO_BASE + 0xAA))
+#define ST_TSENSE_CAL1_30C		MMIO16((INFO_BASE + 0xA8))
+#define ST_TSENSE_CAL2_130C		MMIO16((INFO_BASE + 0xCA))
+
+#endif
diff --git a/include/libopencm3/stm32/g0/pwr.h b/include/libopencm3/stm32/g0/pwr.h
new file mode 100644
index 00000000..c2264d94
--- /dev/null
+++ b/include/libopencm3/stm32/g0/pwr.h
@@ -0,0 +1,202 @@
+/** @defgroup pwr_defines PWR Defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx PWR Control</b>
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_PWR_H
+#define LIBOPENCM3_PWR_H
+/**@{*/
+
+/** @defgroup pwr_registers PWR Registers
+@{*/
+/** Power control register 1 (PWR_CR1) */
+#define PWR_CR1				MMIO32(POWER_CONTROL_BASE + 0x00)
+
+/** Power control register 2 (PWR_CR2) */
+#define PWR_CR2				MMIO32(POWER_CONTROL_BASE + 0x04)
+
+/** Power control register 3 (PWR_CR3) */
+#define PWR_CR3				MMIO32(POWER_CONTROL_BASE + 0x08)
+
+/** Power control register 4 (PWR_CR4) */
+#define PWR_CR4				MMIO32(POWER_CONTROL_BASE + 0x0c)
+
+/** Power status register 1 (PWR_SR1) */
+#define PWR_SR1				MMIO32(POWER_CONTROL_BASE + 0x10)
+
+/** Power status registery 2 (PWR_SR2) */
+#define PWR_SR2				MMIO32(POWER_CONTROL_BASE + 0x14)
+
+/** Power status clear register (PWR_SCR) */
+#define PWR_SCR				MMIO32(POWER_CONTROL_BASE + 0x18)
+
+#define PWR_PORT_A		MMIO32(POWER_CONTROL_BASE + 0x20)
+#define PWR_PORT_B		MMIO32(POWER_CONTROL_BASE + 0x28)
+#define PWR_PORT_C		MMIO32(POWER_CONTROL_BASE + 0x30)
+#define PWR_PORT_D		MMIO32(POWER_CONTROL_BASE + 0x38)
+#define PWR_PORT_E		MMIO32(POWER_CONTROL_BASE + 0x40)
+#define PWR_PORT_F		MMIO32(POWER_CONTROL_BASE + 0x48)
+
+#define PWR_PUCR(pwr_port)	MMIO32((pwr_port) + 0x00)
+#define PWR_PDCR(pwr_port)	MMIO32((pwr_port) + 0x04)
+/**@}*/
+
+/* --- PWR_CR1 values ------------------------------------------------------- */
+
+#define PWR_CR1_LPR				(1 << 14)
+
+#define PWR_CR1_VOS_SHIFT		9
+#define PWR_CR1_VOS_MASK		0x3
+/** @defgroup pwr_cr1_vos VOS
+ * @brief Voltage scaling range selection.
+@{*/
+#define PWR_CR1_VOS_RANGE_1		1
+#define PWR_CR1_VOS_RANGE_2		2
+/**@}*/
+
+#define PWR_CR1_DBP				(1 << 8)
+
+#define PWR_CR1_FPD_LPSLP		(1 << 5)
+#define PWR_CR1_FPD_LPRUN		(1 << 4)
+#define PWR_CR1_FPD_STOP		(1 << 3)
+
+#define PWR_CR1_LPMS_SHIFT		0
+#define PWR_CR1_LPMS_MASK		0x07
+/** @defgroup pwr_cr1_lpms LPMS
+ * @ingroup STM32G0xx_pwr_defines
+ * @brief Low-power mode selection
+@{*/
+#define PWR_CR1_LPMS_STOP_0		0
+#define PWR_CR1_LPMS_STOP_1		1
+#define PWR_CR1_LPMS_STANDBY	3
+#define PWR_CR1_LPMS_SHUTDOWN	4
+/**@}*/
+
+/* --- PWR_CR2 values ------------------------------------------------------- */
+
+#define PWR_CR2_PVDRT_SHIFT	4
+#define PWR_CR2_PVDRT_MASK	0x07
+/** @defgroup pwr_cr2_pvdrt PVDRT
+ * @brief Power voltage detector rising threshold selection
+@{*/
+#define PWR_CR2_PVDRT_2V1	0x00
+#define PWR_CR2_PVDRT_2V2	0x01
+#define PWR_CR2_PVDRT_2V5	0x02
+#define PWR_CR2_PVDRT_2V6	0x03
+#define PWR_CR2_PVDRT_2V7	0x04
+#define PWR_CR2_PVDRT_2V9	0x05
+#define PWR_CR2_PVDRT_3V0	0x06
+#define PWR_CR2_PVDRT_PVD_IN	0x07
+/**@}*/
+
+#define PWR_CR2_PVDFT_SHIFT	1
+#define PWR_CR2_PVDFT_MASK	0x07
+/** @defgroup pwr_cr2_pvdft PVDFT
+ * @brief Power voltage detector falling threshold selection
+@{*/
+#define PWR_CR2_PVDFT_2V0	0x00
+#define PWR_CR2_PVDFT_2V2	0x01
+#define PWR_CR2_PVDFT_2V4	0x02
+#define PWR_CR2_PVDFT_2V5	0x03
+#define PWR_CR2_PVDFT_2V6	0x04
+#define PWR_CR2_PVDFT_2V8	0x05
+#define PWR_CR2_PVDFT_2V9	0x06
+/**@}*/
+
+#define PWR_CR2_PVDE		(1 << 0)
+
+/* --- PWR_CR3 values ------------------------------------------------------- */
+
+#define PWR_CR3_EIWUL		(1 << 15)
+#define PWR_CR3_APC			(1 << 10)
+#define PWR_CR3_ULPEN		(1 << 9)
+#define PWR_CR3_RRS			(1 << 8)
+#define PWR_CR3_EWUP6		(1 << 5)
+#define PWR_CR3_EWUP5		(1 << 4)
+#define PWR_CR3_EWUP4		(1 << 3)
+#define PWR_CR3_EWUP2		(1 << 1)
+#define PWR_CR3_EWUP1		(1 << 0)
+
+/* --- PWR_CR4 values ------------------------------------------------------- */
+
+#define PWR_CR4_VBRS		(1 << 9)
+#define PWR_CR4_VBE			(1 << 8)
+#define PWR_CR4_WP6			(1 << 5)
+#define PWR_CR4_WP5			(1 << 4)
+#define PWR_CR4_WP4			(1 << 3)
+#define PWR_CR4_WP2			(1 << 1)
+#define PWR_CR4_WP1			(1 << 0)
+
+/* --- PWR_SR1 values ------------------------------------------------------- */
+
+#define PWR_SR1_WUFI		(1 << 15)
+#define PWR_SR1_SBF			(1 << 8)
+#define PWR_SR1_WUF6		(1 << 5)
+#define PWR_SR1_WUF5		(1 << 4)
+#define PWR_SR1_WUF4		(1 << 3)
+#define PWR_SR1_WUF2		(1 << 1)
+#define PWR_SR1_WUF1		(1 << 0)
+
+/* --- PWR_SR2 values ------------------------------------------------------- */
+
+#define PWR_SR2_PVDO		(1 << 11)
+#define PWR_SR2_VOSF		(1 << 10)
+#define PWR_SR2_REGLPF		(1 << 9)
+#define PWR_SR2_REGLPS		(1 << 8)
+#define PWR_SR2_FLASHRDY	(1 << 8)
+
+/* --- PWR_SCR values ------------------------------------------------------- */
+
+#define PWR_SCR_CSBF		(1 << 8)
+#define PWR_SCR_CWUF6		(1 << 5)
+#define PWR_SCR_CWUF5		(1 << 4)
+#define PWR_SCR_CWUF4		(1 << 3)
+#define PWR_SCR_CWUF2		(1 << 1)
+#define PWR_SCR_CWUF1		(1 << 0)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+enum pwr_vos_scale {
+	PWR_SCALE1 = PWR_CR1_VOS_RANGE_1,
+	PWR_SCALE2 = PWR_CR1_VOS_RANGE_2,
+};
+
+BEGIN_DECLS
+
+void pwr_set_vos_scale(enum pwr_vos_scale scale);
+
+void pwr_disable_backup_domain_write_protect(void);
+void pwr_enable_backup_domain_write_protect(void);
+
+void pwr_set_low_power_mode_selection(uint32_t lpms);
+
+void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level);
+void pwr_disable_power_voltage_detect(void);
+
+END_DECLS
+
+/**@}*/
+#endif
+
diff --git a/include/libopencm3/stm32/g0/rcc.h b/include/libopencm3/stm32/g0/rcc.h
new file mode 100644
index 00000000..dd989cef
--- /dev/null
+++ b/include/libopencm3/stm32/g0/rcc.h
@@ -0,0 +1,842 @@
+/** @defgroup rcc_defines RCC Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx Reset and Clock Control</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/**@{*/
+
+#ifndef LIBOPENCM3_RCC_H
+#define LIBOPENCM3_RCC_H
+
+#include <libopencm3/stm32/pwr.h>
+
+/* --- RCC registers ------------------------------------------------------- */
+
+#define RCC_CR				MMIO32(RCC_BASE + 0x00)
+#define RCC_ICSCR			MMIO32(RCC_BASE + 0x04)
+#define RCC_CFGR			MMIO32(RCC_BASE + 0x08)
+#define RCC_PLLCFGR			MMIO32(RCC_BASE + 0x0c)
+#define RCC_CIER			MMIO32(RCC_BASE + 0x18)
+#define RCC_CIFR			MMIO32(RCC_BASE + 0x1c)
+#define RCC_CICR			MMIO32(RCC_BASE + 0x20)
+#define RCC_IOPRSTR_OFFSET			0x24
+#define RCC_IOPRSTR					MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET)
+#define RCC_AHBRSTR_OFFSET			0x28
+#define RCC_AHBRSTR					MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET)
+#define RCC_APBRSTR1_OFFSET			0x2c
+#define RCC_APBRSTR1				MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET)
+#define RCC_APBRSTR2_OFFSET			0x30
+#define RCC_APBRSTR2				MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET)
+#define RCC_IOPENR_OFFSET			0x34
+#define RCC_IOPENR					MMIO32(RCC_BASE + RCC_IOPENR_OFFSET)
+#define RCC_AHBENR_OFFSET			0x38
+#define RCC_AHBENR					MMIO32(RCC_BASE + RCC_AHBENR_OFFSET)
+#define RCC_APBENR1_OFFSET			0x3c
+#define RCC_APBENR1					MMIO32(RCC_BASE + RCC_APBENR1_OFFSET)
+#define RCC_APBENR2_OFFSET			0x40
+#define RCC_APBENR2					MMIO32(RCC_BASE + RCC_APBENR2_OFFSET)
+#define RCC_IOPSMENR_OFFSET			0x44
+#define RCC_IOPSMENR				MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET)
+#define RCC_AHBSMENR_OFFSET			0x48
+#define RCC_AHBSMENR				MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET)
+#define RCC_APBSMENR1_OFFSET		0x4c
+#define RCC_APBSMENR1				MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET)
+#define RCC_APBSMENR2_OFFSET		0x50
+#define RCC_APBSMENR2				MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET)
+#define RCC_CCIPR			MMIO32(RCC_BASE + 0x54)
+#define RCC_BDCR			MMIO32(RCC_BASE + 0x5c)
+#define RCC_CSR				MMIO32(RCC_BASE + 0x60)
+
+
+
+/* --- RCC_CR values ------------------------------------------------------- */
+
+#define RCC_CR_PLLRDY			(1 << 25)
+#define RCC_CR_PLLON			(1 << 24)
+#define RCC_CR_CSSON			(1 << 19)
+#define RCC_CR_HSEBYP			(1 << 18)
+#define RCC_CR_HSERDY			(1 << 17)
+#define RCC_CR_HSEON			(1 << 16)
+
+#define RCC_CR_HSIDIV_SHIFT		11
+#define RCC_CR_HSIDIV_MASK		0x7
+/** @defgroup rcc_cr_hsidiv HSI Div
+ * @brief Division factor of the HSI16 oscillator to produce HSISYS clock
+@sa rcc_cr_hsidiv
+@{*/
+#define RCC_CR_HSIDIV_DIV1		0
+#define RCC_CR_HSIDIV_DIV2		1
+#define RCC_CR_HSIDIV_DIV4		2
+#define RCC_CR_HSIDIV_DIV8		3
+#define RCC_CR_HSIDIV_DIV16		4
+#define RCC_CR_HSIDIV_DIV32		5
+#define RCC_CR_HSIDIV_DIV64		6
+#define RCC_CR_HSIDIV_DIV128	7
+/**@}*/
+
+#define RCC_CR_HSIRDY			(1 << 10)
+#define RCC_CR_HSIKERON			(1 << 9)
+#define RCC_CR_HSION			(1 << 8)
+
+/* --- RCC_ICSCR values ---------------------------------------------------- */
+
+#define RCC_ICSCR_HSITRIM_SHIFT		8
+#define RCC_ICSCR_HSITRIM_MASK		0x1f
+#define RCC_ICSCR_HSICAL_SHIFT		0
+#define RCC_ICSCR_HSICAL_MASK		0xff
+
+/* --- RCC_CFGR values ----------------------------------------------------- */
+
+#define RCC_CFGR_MCOPRE_SHIFT	    28
+#define RCC_CFGR_MCOPRE_MASK	    0x7
+/** @defgroup rcc_cfgr_mcopre MCO Pre
+ * @brief Division factor of microcontroler clock output
+@sa rcc_cfgr_mcopre
+@{*/
+#define RCC_CFGR_MCOPRE_DIV1	    0
+#define RCC_CFGR_MCOPRE_DIV2	    1
+#define RCC_CFGR_MCOPRE_DIV4	    2
+#define RCC_CFGR_MCOPRE_DIV8	    3
+#define RCC_CFGR_MCOPRE_DIV16	    4
+#define RCC_CFGR_MCOPRE_DIV32	    5
+#define RCC_CFGR_MCOPRE_DIV64	    6
+#define RCC_CFGR_MCOPRE_DIV128	    7
+/**@}*/
+
+#define RCC_CFGR_MCO_SHIFT			24
+#define RCC_CFGR_MCO_MASK			0xf
+
+/** @defgroup rcc_cfgr_mcosel MCO Sel
+ * @brief Microcontroler clock output selector
+@sa rcc_cfgr_mcosel
+@{*/
+#define RCC_CFGR_MCO_NOCLK			0x0
+#define RCC_CFGR_MCO_SYSCLK			0x1
+#define RCC_CFGR_MCO_HSI16			0x3
+#define RCC_CFGR_MCO_HSE			0x4
+#define RCC_CFGR_MCO_PLLRCLK		0x5
+#define RCC_CFGR_MCO_LSI			0x6
+#define RCC_CFGR_MCO_LSE			0x7
+/**@}*/
+
+#define RCC_CFGR_PPRE_MASK		0x7
+#define RCC_CFGR_PPRE_SHIFT		12
+
+/** @defgroup rcc_cfgr_ppre PPRE
+ * @brief APB Prescaler
+@sa rcc_cfgr_ppre
+@{*/
+#define RCC_CFGR_PPRE_NODIV		0x0
+#define RCC_CFGR_PPRE_DIV2		0x4
+#define RCC_CFGR_PPRE_DIV4		0x5
+#define RCC_CFGR_PPRE_DIV8		0x6
+#define RCC_CFGR_PPRE_DIV16		0x7
+/**@}*/
+
+#define RCC_CFGR_HPRE_MASK		0xf
+#define RCC_CFGR_HPRE_SHIFT		8
+/** @defgroup rcc_cfgr_hpre HPRE
+ * @brief APB Prescaler
+@sa rcc_cfgr_hpre
+@{*/
+#define RCC_CFGR_HPRE_NODIV		0x0
+#define RCC_CFGR_HPRE_DIV2		0x8
+#define RCC_CFGR_HPRE_DIV4		0x9
+#define RCC_CFGR_HPRE_DIV8		0xa
+#define RCC_CFGR_HPRE_DIV16		0xb
+#define RCC_CFGR_HPRE_DIV64		0xc
+#define RCC_CFGR_HPRE_DIV128	0xd
+#define RCC_CFGR_HPRE_DIV256	0xe
+#define RCC_CFGR_HPRE_DIV512	0xf
+/**@}*/
+
+#define RCC_CFGR_SWS_MASK			0x3
+#define RCC_CFGR_SWS_SHIFT			3
+/** @defgroup rcc_cfgr_sws SWS
+ * @brief System clock switch status
+@sa rcc_cfgr_sws
+@{*/
+#define RCC_CFGR_SWS_HSISYS			0x0
+#define RCC_CFGR_SWS_HSE			0x1
+#define RCC_CFGR_SWS_PLLRCLK		0x2
+#define RCC_CFGR_SWS_LSI			0x3
+#define RCC_CFGR_SWS_LSE			0x4
+/**@}*/
+
+#define RCC_CFGR_SW_MASK			0x3
+#define RCC_CFGR_SW_SHIFT			0
+/** @defgroup rcc_cfgr_sws SW
+ * @brief System clock switch
+@sa rcc_cfgr_sw
+@{*/
+#define RCC_CFGR_SW_HSISYS			0x0
+#define RCC_CFGR_SW_HSE				0x1
+#define RCC_CFGR_SW_PLLRCLK			0x2
+#define RCC_CFGR_SW_LSI				0x3
+#define RCC_CFGR_SW_LSE				0x4
+/**@}*/
+
+/* --- RCC_PLLCFGR - PLL Configuration Register */
+
+#define RCC_PLLCFGR_PLLR_SHIFT		29
+#define RCC_PLLCFGR_PLLR_MASK		0x7
+/** @defgroup rcc_pllcfgr_pllr PLLR
+ * @brief VCO Division factor R for PLLRCLK clock output [2..8]. Frequency must not exceed 64mhz in voltage range 1, or 16mhz in voltage range 2.
+@sa rcc_pllcfgr_pllr
+@{*/
+#define RCC_PLLCFGR_PLLR_DIV(x)		((x)-1)
+/**@}*/
+
+#define RCC_PLLCFGR_PLLREN			(1<<28)
+
+#define RCC_PLLCFGR_PLLQ_SHIFT		25
+#define RCC_PLLCFGR_PLLQ_MASK		0x7
+/** @defgroup rcc_pllcfgr_pllq PLLQ
+ * @brief VCO Division factor Q for PLLQCLK clock output [2..8]. Frequency must not exceed 128mhz in voltage range 1, or 32mhz in range 2
+@sa rcc_pllcfgr_pllq
+@{*/
+#define RCC_PLLCFGR_PLLQ_DIV(x)		((x)-1)
+/**@}*/
+
+#define RCC_PLLCFGR_PLLQEN		(1 << 24)
+
+#define RCC_PLLCFGR_PLLP_SHIFT		17
+#define RCC_PLLCFGR_PLLP_MASK		0x1f
+/** @defgroup rcc_pllcfgr_pllp PLLP
+ * @brief VCO Division factor P for PLLPCLK clock output [2..32]. Frequency must not exceed 122mhz in voltage range 1, or 40mhz in range 2
+@sa rcc_pllcfgr_pllp
+@{*/
+#define RCC_PLLCFGR_PLLP_DIV(x)		((x)-1)
+/**@}*/
+
+#define RCC_PLLCFGR_PLLPEN			(1 << 16)
+
+#define RCC_PLLCFGR_PLLN_SHIFT		0x8
+#define RCC_PLLCFGR_PLLN_MASK		0x7f
+/** @defgroup rcc_pllcfgr_plln PLLN
+ * @brief Multiplication factor N [8..86] for PLL VCO output frequency. Frequency must be between 64mhz and 344mhz.
+@{*/
+#define RCC_PLLCFGR_PLLN_MUL(x)		(x)
+/**@}*/
+
+#define RCC_PLLCFGR_PLLM_SHIFT		0x4
+#define RCC_PLLCFGR_PLLM_MASK		0x7
+/** @defgroup rcc_pllcfgr_pllm PLLM
+ * @brief Division factor M [1..8] for PLL input clock. Input frequency must be between 4mhz and 16mhz. 
+@{*/
+#define RCC_PLLCFGR_PLLM_DIV(x)		((x)-1)
+/**@}*/
+
+#define RCC_PLLCFGR_PLLSRC_SHIFT	0
+#define RCC_PLLCFGR_PLLSRC_MASK		0x3
+/** @defgroup rcc_pllcfgr_pllsrc PLLSRC
+ * @brief PLL input clock source
+@sa rcc_pllcfgr_pllsrc
+@{*/
+#define RCC_PLLCFGR_PLLSRC_NONE		0
+#define RCC_PLLCFGR_PLLSRC_HSI16	2
+#define RCC_PLLCFGR_PLLSRC_HSE		3
+/**@}*/
+
+/* --- RCC_CIER - Clock interrupt enable register */
+
+#define RCC_CIER_PLLRDYIE			(1 << 5)
+#define RCC_CIER_HSERDYIE			(1 << 4)
+#define RCC_CIER_HSIRDYIE			(1 << 3)
+#define RCC_CIER_LSERDYIE			(1 << 1)
+#define RCC_CIER_LSIRDYIE			(1 << 0)
+
+/* --- RCC_CIFR - Clock interrupt flag register */
+
+#define RCC_CIFR_LSECSSF			(1 << 9)
+#define RCC_CIFR_CSSF				(1 << 8)
+#define RCC_CIFR_PLLRDYF			(1 << 5)
+#define RCC_CIFR_HSERDYF			(1 << 4)
+#define RCC_CIFR_HSIRDYF			(1 << 3)
+#define RCC_CIFR_LSERDYF			(1 << 1)
+#define RCC_CIFR_LSIRDYF			(1 << 0)
+
+/* --- RCC_CICR - Clock interrupt flag register */
+
+#define RCC_CICR_LSECSSC			(1 << 9)
+#define RCC_CICR_CSSC				(1 << 8)
+#define RCC_CICR_PLLRDYC			(1 << 5)
+#define RCC_CICR_HSERDYC			(1 << 4)
+#define RCC_CICR_HSIRDYC			(1 << 3)
+#define RCC_CICR_LSERDYC			(1 << 1)
+#define RCC_CICR_LSIRDYC			(1 << 0)
+
+/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
+@{*/
+#define RCC_AHBRSTR_RNGRST			(1 << 18)
+#define RCC_AHBRSTR_AESRST			(1 << 16)
+#define RCC_AHBRSTR_CRCRST			(1 << 12)
+#define RCC_AHBRSTR_FLASHRST		(1 << 8)
+#define RCC_AHBRSTR_DMARST			(1 << 0)
+/**@}*/
+
+/** @defgroup rcc_apb1rstr_rst RCC_APBRSTRx reset values (full set)
+@{*/
+/** @defgroup rcc_apbrstr1_rst RCC_APBRSTR1 reset values
+@{*/
+#define RCC_APBRSTR1_LPTIM1RST			(1 << 31)
+#define RCC_APBRSTR1_LPTIM2RST			(1 << 30)
+#define RCC_APBRSTR1_DAC1RST			(1 << 29)
+#define RCC_APBRSTR1_PWRRST				(1 << 28)
+#define RCC_APBRSTR1_DBGRST				(1 << 27)
+#define RCC_APBRSTR1_UCPD2RST			(1 << 26)
+#define RCC_APBRSTR1_UCPD1RST			(1 << 25)
+#define RCC_APBRSTR1_I2C2RST			(1 << 22)
+#define RCC_APBRSTR1_I2C1RST			(1 << 21)
+#define RCC_APBRSTR1_LPUART1RST			(1 << 20)
+#define RCC_APBRSTR1_USART4RST			(1 << 19)
+#define RCC_APBRSTR1_USART3RST			(1 << 18)
+#define RCC_APBRSTR1_USART2RST			(1 << 17)
+#define RCC_APBRSTR1_SPI2RST			(1 << 14)
+#define RCC_APBRSTR1_TIM7RST			(1 << 5)
+#define RCC_APBRSTR1_TIM6RST			(1 << 4)
+#define RCC_APBRSTR1_TIM3RST			(1 << 1)
+#define RCC_APBRSTR1_TIM2RST			(1 << 0)
+/**@}*/
+
+/** @defgroup rcc_apbrstr2_rst RCC_APBRSTR2 reset values
+@{*/
+#define RCC_APBRSTR2_ADCRST				(1 << 20)
+#define RCC_APBRSTR2_TIM17RST			(1 << 18)
+#define RCC_APBRSTR2_TIM16RST			(1 << 17)
+#define RCC_APBRSTR2_TIM16RST			(1 << 17)
+#define RCC_APBRSTR2_TIM15RST			(1 << 16)
+#define RCC_APBRSTR2_TIM14RST			(1 << 15)
+#define RCC_APBRSTR2_USART1RST			(1 << 14)
+#define RCC_APBRSTR2_SPI1RST			(1 << 12)
+#define RCC_APBRSTR2_TIM1RST			(1 << 11)
+#define RCC_APBRSTR2_SYSCFGRST			(1 << 0)
+/**@}*/
+/**@}*/
+
+/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values
+@{*/
+#define RCC_AHBENR_RNGEN			(1 << 18)
+#define RCC_AHBENR_AESEN			(1 << 16)
+#define RCC_AHBENR_CRCEN			(1 << 12)
+#define RCC_AHBENR_FLASHEN			(1 << 8)
+#define RCC_AHBENR_DMAEN			(1 << 0)
+/**@}*/
+
+/** @defgroup rcc_apb1enr_en RCC_APBENRx enable values (full set)
+@{*/
+/** @defgroup rcc_apbenr1_en RCC_APBENR1 enable values
+@{*/
+#define RCC_APBENR1_LPTIM1EN		(1 << 31)
+#define RCC_APBENR1_LPTIM2EN		(1 << 30)
+#define RCC_APBENR1_DAC1EN			(1 << 29)
+#define RCC_APBENR1_PWREN			(1 << 28)
+#define RCC_APBENR1_DBGEN			(1 << 27)
+#define RCC_APBENR1_UCPD2EN			(1 << 26)
+#define RCC_APBENR1_UCPD1EN			(1 << 25)
+#define RCC_APBENR1_CECEN			(1 << 24)
+#define RCC_APBENR1_I2C2EN			(1 << 22)
+#define RCC_APBENR1_I2C1EN			(1 << 21)
+#define RCC_APBENR1_LPUART1EN		(1 << 20)
+#define RCC_APBENR1_USART4EN		(1 << 19)
+#define RCC_APBENR1_USART3EN		(1 << 18)
+#define RCC_APBENR1_USART2EN		(1 << 17)
+#define RCC_APBENR1_SPI2EN			(1 << 14)
+#define RCC_APBENR1_WWDGEN			(1 << 11)
+#define RCC_APBENR1_RTCAPBEN		(1 << 10)
+#define RCC_APBENR1_TIM7EN			(1 << 5)
+#define RCC_APBENR1_TIM6EN			(1 << 4)
+#define RCC_APBENR1_TIM3EN			(1 << 1)
+#define RCC_APBENR1_TIM2EN			(1 << 0)
+/**@}*/
+
+/** @defgroup rcc_apbenr2_en RCC_APBENR2 enable values
+@{*/
+#define RCC_APBENR2_ADCEN			(1 << 20)
+#define RCC_APBENR2_TIM17EN			(1 << 18)
+#define RCC_APBENR2_TIM16EN			(1 << 17)
+#define RCC_APBENR2_TIM16EN			(1 << 17)
+#define RCC_APBENR2_TIM15EN			(1 << 16)
+#define RCC_APBENR2_TIM14EN			(1 << 15)
+#define RCC_APBENR2_USART1EN		(1 << 14)
+#define RCC_APBENR2_SPI1EN			(1 << 12)
+#define RCC_APBENR2_TIM1EN			(1 << 11)
+#define RCC_APBENR2_SYSCFGEN		(1 << 0)
+/**@}*/
+/**@}*/
+
+/* --- RCC_AHBSMENR values ------------------------------------------------- */
+
+/** @defgroup rcc_aphbsmenr_en RCC_AHBSMENR enable in sleep/stop mode values
+@{*/
+#define RCC_AHBSMENR_RNGSMEN			(1 << 18)
+#define RCC_AHBSMENR_AESSMEN			(1 << 16)
+#define RCC_AHBSMENR_CRCSMEN			(1 << 12)
+#define RCC_AHBSMENR_SRAMSMEN			(1 << 9)
+#define RCC_AHBSMENR_FLASHSMEN			(1 << 8)
+#define RCC_AHBSMENR_DMASMEN			(1 << 0)
+/**@}*/
+
+/* --- RCC_APBSMENR1 values ------------------------------------------------- */
+
+/** @defgroup rcc_apbsmenr_en RCC_APBSMENR1 enable in sleep/stop mode values
+@{*/
+#define RCC_APBSMENR1_LPTIM1SMEN		(1 << 31)
+#define RCC_APBSMENR1_LPTIM2SMEN		(1 << 30)
+#define RCC_APBSMENR1_DAC1SMEN			(1 << 29)
+#define RCC_APBSMENR1_PWRSMEN			(1 << 28)
+#define RCC_APBSMENR1_DBGSMEN			(1 << 27)
+#define RCC_APBSMENR1_UCPD2SMEN			(1 << 26)
+#define RCC_APBSMENR1_UCPD1SMEN			(1 << 25)
+#define RCC_APBSMENR1_CECSMEN			(1 << 24)
+#define RCC_APBSMENR1_I2C2SMEN			(1 << 22)
+#define RCC_APBSMENR1_I2C1SMEN			(1 << 21)
+#define RCC_APBSMENR1_LPUART1SMEN		(1 << 20)
+#define RCC_APBSMENR1_USART4SMEN		(1 << 19)
+#define RCC_APBSMENR1_USART3SMEN		(1 << 18)
+#define RCC_APBSMENR1_USART2SMEN		(1 << 17)
+#define RCC_APBSMENR1_SPI2SMEN			(1 << 14)
+#define RCC_APBSMENR1_WWDGSMEN			(1 << 11)
+#define RCC_APBSMENR1_RTCAPBSMEN			(1 << 10)
+#define RCC_APBSMENR1_TIM7SMEN			(1 << 5)
+#define RCC_APBSMENR1_TIM6SMEN			(1 << 4)
+#define RCC_APBSMENR1_TIM3SMEN			(1 << 1)
+#define RCC_APBSMENR1_TIM2SMEN			(1 << 0)
+/**@}*/
+
+/* --- RCC_APBSMENR2 values ------------------------------------------------- */
+
+/** @defgroup rcc_apbsmenr2_en RCC_APBSMENR2 enable in sleep/stop mode values
+@{*/
+#define RCC_APBSMENR2_ADCSMEN			(1 << 20)
+#define RCC_APBSMENR2_TIM17SMEN			(1 << 18)
+#define RCC_APBSMENR2_TIM16SMEN			(1 << 17)
+#define RCC_APBSMENR2_TIM16SMEN			(1 << 17)
+#define RCC_APBSMENR2_TIM15SMEN			(1 << 16)
+#define RCC_APBSMENR2_TIM14SMEN			(1 << 15)
+#define RCC_APBSMENR2_USART1SMEN		(1 << 14)
+#define RCC_APBSMENR2_SPI1SMEN			(1 << 12)
+#define RCC_APBSMENR2_TIM1SMEN			(1 << 11)
+#define RCC_APBSMENR2_SYSCFGSMEN		(1 << 0)
+/**@}*/
+
+/* --- RCC_CCIPR - Peripherals independent clock config register ----------- */
+
+#define RCC_CCIPR_ADCSEL_MASK		0x3
+#define RCC_CCIPR_ADCSEL_SHIFT		30
+/** @defgroup rcc_ccipr_adcsel ADCSEL
+@{*/
+#define RCC_CCIPR_ADCSEL_SYSCLK		0
+#define RCC_CCIPR_ADCSEL_PLLPCLK	1
+#define RCC_CCIPR_ADCSEL_HSI16		2
+/**@}*/
+
+#define RCC_CCIPR_RNGDIV_MASK		0x3
+#define RCC_CCIPR_RNGDIV_SHIFT		28
+/** @defgroup rcc_ccipr_rngdiv RNGDIV
+@{*/
+#define RCC_CCIPR_RNGDIV_1		0
+#define RCC_CCIPR_RNGDIV_2 		1
+#define RCC_CCIPR_RNGDIV_4		2
+#define RCC_CCIPR_RNGDIV_8		3
+/**@}*/
+
+#define RCC_CCIPR_RNGSEL_MASK		0x3
+#define RCC_CCIPR_RNGSEL_SHIFT		26
+/** @defgroup rcc_ccipr_rngsel RNGSEL
+@{*/
+#define RCC_CCIPR_RNGSEL_NONE		0
+#define RCC_CCIPR_RNGSEL_HSI16 		1
+#define RCC_CCIPR_RNGSEL_SYSCLK		2
+#define RCC_CCIPR_RNGSEL_PLLQCLK	3
+/**@}*/
+
+#define RCC_CCIPR_TIM15SEL_MASK		0x1
+#define RCC_CCIPR_TIM15SEL_SHIFT	24
+/** @defgroup rcc_ccipr_tim15sel TIM15SEL
+@{*/
+#define RCC_CCIPR_TIM15SEL_TIMPCLK		0
+#define RCC_CCIPR_TIM15SEL_PLLQCLK 		1
+/**@}*/
+
+#define RCC_CCIPR_TIM1SEL_MASK		0x1
+#define RCC_CCIPR_TIM1SEL_SHIFT		20
+/** @defgroup rcc_ccipr_tim1sel TIM1SEL
+@{*/
+#define RCC_CCIPR_TIM1SEL_TIMPCLK		0
+#define RCC_CCIPR_TIM1SEL_PLLQCLK 		1
+/**@}*/
+
+#define RCC_CCIPR_LPTIM2SEL_MASK		0x3
+#define RCC_CCIPR_LPTIM2SEL_SHIFT		20
+/** @defgroup rcc_ccipr_lptim2sel LPTIM2SEL LPTIM2 Clock source selection
+@{*/
+#define RCC_CCIPR_LPTIM2SEL_PCLK		0
+#define RCC_CCIPR_LPTIM2SEL_LSI		 	1
+#define RCC_CCIPR_LPTIM2SEL_HSI16 		2
+#define RCC_CCIPR_LPTIM2SEL_LSE			3
+/**@}*/
+
+#define RCC_CCIPR_LPTIM1SEL_MASK		0x3
+#define RCC_CCIPR_LPTIM1SEL_SHIFT		18
+/** @defgroup rcc_ccipr_lptim1sel LPTIM1SEL LPTIM1 Clock source selection
+@{*/
+#define RCC_CCIPR_LPTIM1SEL_PCLK		0
+#define RCC_CCIPR_LPTIM1SEL_LSI			1
+#define RCC_CCIPR_LPTIM1SEL_HSI16 		2
+#define RCC_CCIPR_LPTIM1SEL_LSE			3
+/**@}*/
+
+#define RCC_CCIPR_I2S1SEL_MASK		0x3
+#define RCC_CCIPR_I2S1SEL_SHIFT		14
+/** @defgroup rcc_ccipr_i2s1sel I2S1SEL I2S1 Clock source selection
+@{*/
+#define RCC_CCIPR_I2S1SEL_SYSCLK		0
+#define RCC_CCIPR_I2S1SEL_PLLPLCK		1
+#define RCC_CCIPR_I2S1SEL_HSI16 		2
+#define RCC_CCIPR_I2S1SEL_I2S_CKIN 		2
+/**@}*/
+
+#define RCC_CCIPR_I2C1SEL_MASK		0x3
+#define RCC_CCIPR_I2C1SEL_SHIFT		12
+/** @defgroup rcc_ccipr_i2c1sel I2C1SEL I2C1 Clock source selection
+@{*/
+#define RCC_CCIPR_I2C1SEL_PCLK			0
+#define RCC_CCIPR_I2C1SEL_SYSCLK		1
+#define RCC_CCIPR_I2C1SEL_HSI16 		2
+/**@}*/
+
+#define RCC_CCIPR_LPUART1SEL_MASK		0x3
+#define RCC_CCIPR_LPUART1SEL_SHIFT		10
+/** @defgroup rcc_ccipr_lpuart1sel LPUART1SEL LPUART1 Clock source selection
+@{*/
+#define RCC_CCIPR_LPUART1SEL_PCLK			0
+#define RCC_CCIPR_LPUART1SEL_SYSCLK			1
+#define RCC_CCIPR_LPUART1SEL_HSI16 			2
+#define RCC_CCIPR_LPUART1SEL_LSE			3
+/**@}*/
+
+#define RCC_CCIPR_CECSEL_MASK			0x1
+#define RCC_CCIPR_CECSEL_SHIFT			6
+/** @defgroup rcc_ccipr_cecsel CECSEL CEC Clock souce selection
+@{*/
+#define RCC_CCIPR_CECSEL_HSI16			0
+#define RCC_CCIPR_CECSEL_LSE 			1
+/**@}*/
+
+#define RCC_CCIPR_USART2SEL_MASK		0x3
+#define RCC_CCIPR_USART2SEL_SHIFT		2
+/** @defgroup rcc_ccipr_usart2sel USART2SEL USART2 Clock source selection
+@{*/
+#define RCC_CCIPR_USART2SEL_PCLK		0
+#define RCC_CCIPR_USART2SEL_SYSCLK	 	1
+#define RCC_CCIPR_USART2SEL_HSI16 		2
+#define RCC_CCIPR_USART2SEL_LSE			3
+/**@}*/
+
+#define RCC_CCIPR_USART1SEL_MASK		0x3
+#define RCC_CCIPR_USART1SEL_SHIFT		0
+/** @defgroup rcc_ccipr_usart1sel USART1SEL USART1 Clock source selection
+@{*/
+#define RCC_CCIPR_USART1SEL_PCLK		0
+#define RCC_CCIPR_USART1SEL_SYSCLK		1
+#define RCC_CCIPR_USART1SEL_HSI16 		2
+#define RCC_CCIPR_USART1SEL_LSE			3
+/**@}*/
+
+/* --- RCC_BDCR - PLL Configuration Register */
+
+#define RCC_BDCR_LSCOSEL		(1 << 25)
+#define RCC_BDCR_LSCOEN			(1 << 24)
+#define RCC_BDCR_BDRST			(1 << 16)
+#define RCC_BDCR_RTCEN			(1 << 15)
+
+#define RCC_BDCR_RTCSEL_SHIFT		8
+#define RCC_BDCR_RTCSEL_MASK		0x3
+/** @defgroup rcc_bdcr_rtcsel RTCSEL RTC Clock source selection
+@{*/
+#define RCC_BDCR_RTCSEL_NONE		0
+#define RCC_BDCR_RTCSEL_LSE		1
+#define RCC_BDCR_RTCSEL_LSI		2
+#define RCC_BDCR_RTCSEL_HSE_DIV32	3
+/**@}*/
+
+#define RCC_BDCR_LSEDRV_SHIFT		3
+#define RCC_BDCR_LSEDRV_MASK		0x3
+/** @defgroup rcc_bdcr_lsedrv LSEDRV LSE Oscillator drive capacity
+@{*/
+#define RCC_BDCR_LSEDRV_LOW			0
+#define RCC_BDCR_LSEDRV_MEDLOW		1
+#define RCC_BDCR_LSEDRV_MEDHIGH		2
+#define RCC_BDCR_LSEDRV_HIGH		3
+/**@}*/
+
+#define RCC_BDCR_LSEBYP				(1 << 2)
+#define RCC_BDCR_LSERDY				(1 << 1)
+#define RCC_BDCR_LSEON				(1 << 0)
+
+/* --- RCC_CSR - Control/Status register ----------------------------------- */
+
+#define RCC_CSR_LPWRRSTF			(1 << 31)
+#define RCC_CSR_WWDGRSTF			(1 << 30)
+#define RCC_CSR_IWDGRSTF			(1 << 29)
+#define RCC_CSR_SFTRSTF				(1 << 28)
+#define RCC_CSR_PWRSTF				(1 << 27)
+#define RCC_CSR_PINRSTF				(1 << 26)
+#define RCC_CSR_OBLRSTF				(1 << 25)
+#define RCC_CSR_RMVF				(1 << 23)
+#define RCC_CSR_LSIRDY				(1 << 1)
+#define RCC_CSR_LSION				(1 << 0)
+
+/* --- Variable definitions ------------------------------------------------ */
+
+extern uint32_t rcc_ahb_frequency;
+extern uint32_t rcc_apb1_frequency;
+/*
+ * as done for F0, fake out apb2_frequency as the device does not really have
+ * apb2 clock.
+ */
+#define rcc_apb2_frequency rcc_apb1_frequency
+
+/* --- Function prototypes ------------------------------------------------- */
+ 
+#define _REG_BIT(offset, bit)            (((offset) << 5) + (bit))
+
+enum rcc_osc {
+	RCC_HSI,
+	RCC_HSE,
+	RCC_PLL,
+	RCC_LSE,
+	RCC_LSI,
+};
+
+enum rcc_periph_clken {
+	RCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5),
+	RCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4),
+	RCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3),
+	RCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2),
+	RCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1),
+	RCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0),
+
+	RCC_RNG = _REG_BIT(RCC_AHBENR_OFFSET, 18),
+	RCC_AES = _REG_BIT(RCC_AHBENR_OFFSET, 16),
+	RCC_CRC = _REG_BIT(RCC_AHBENR_OFFSET, 12),
+	RCC_FLASH = _REG_BIT(RCC_AHBENR_OFFSET, 8),
+	RCC_DMA = _REG_BIT(RCC_AHBENR_OFFSET, 0),
+	RCC_DMA1 = _REG_BIT(RCC_AHBENR_OFFSET, 0), /* Compatibility */
+
+	RCC_LPTIM1 = _REG_BIT(RCC_APBENR1_OFFSET, 31),
+	RCC_LPTIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 30),
+	RCC_DAC1 = _REG_BIT(RCC_APBENR1_OFFSET, 29),
+	RCC_PWR = _REG_BIT(RCC_APBENR1_OFFSET, 28),
+	RCC_DBG = _REG_BIT(RCC_APBENR1_OFFSET, 27),
+	RCC_UCPD1 = _REG_BIT(RCC_APBENR1_OFFSET, 26),
+	RCC_UCPD2 = _REG_BIT(RCC_APBENR1_OFFSET, 25),
+	RCC_CEC = _REG_BIT(RCC_APBENR1_OFFSET, 24),
+	RCC_I2C2 = _REG_BIT(RCC_APBENR1_OFFSET, 22),
+	RCC_I2C1 = _REG_BIT(RCC_APBENR1_OFFSET, 21),
+	RCC_LPUART1 = _REG_BIT(RCC_APBENR1_OFFSET, 20),
+	RCC_USART4 = _REG_BIT(RCC_APBENR1_OFFSET, 19),
+	RCC_USART3 = _REG_BIT(RCC_APBENR1_OFFSET, 18),
+	RCC_USART2 = _REG_BIT(RCC_APBENR1_OFFSET, 17),
+	RCC_SPI2 = _REG_BIT(RCC_APBENR1_OFFSET, 14),
+	RCC_TIM7 = _REG_BIT(RCC_APBENR1_OFFSET, 5),
+	RCC_TIM6 = _REG_BIT(RCC_APBENR1_OFFSET, 4),
+	RCC_TIM3 = _REG_BIT(RCC_APBENR1_OFFSET, 1),
+	RCC_TIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 0),
+
+	RCC_ADC = _REG_BIT(RCC_APBENR2_OFFSET, 20),
+	RCC_TIM17 = _REG_BIT(RCC_APBENR2_OFFSET, 18),
+	RCC_TIM16 = _REG_BIT(RCC_APBENR2_OFFSET, 17),
+	RCC_TIM15 = _REG_BIT(RCC_APBENR2_OFFSET, 16),
+	RCC_TIM14 = _REG_BIT(RCC_APBENR2_OFFSET, 15),
+	RCC_USART1 = _REG_BIT(RCC_APBENR2_OFFSET, 14),
+	RCC_SPI1 = _REG_BIT(RCC_APBENR2_OFFSET, 12),
+	RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11),
+	RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0),
+
+	SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5),
+	SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4),
+	SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3),
+	SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2),
+	SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1),
+	SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0),
+
+	SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18),
+	SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16),
+	SCC_CRC = _REG_BIT(RCC_AHBSMENR_OFFSET, 12),
+	SCC_FLASH = _REG_BIT(RCC_AHBSMENR_OFFSET, 8),
+	SCC_DMA = _REG_BIT(RCC_AHBSMENR_OFFSET, 0),
+	SCC_DMA1 = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), /* Compatibility */
+
+	SCC_LPTIM1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 31),
+	SCC_LPTIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 30),
+	SCC_DAC1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 29),
+	SCC_PWR = _REG_BIT(RCC_APBSMENR1_OFFSET, 28),
+	SCC_DBG = _REG_BIT(RCC_APBSMENR1_OFFSET, 27),
+	SCC_UCPD1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 26),
+	SCC_UCPD2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 25),
+	SCC_CEC = _REG_BIT(RCC_APBSMENR1_OFFSET, 24),
+	SCC_I2C2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 22),
+	SCC_I2C1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 21),
+	SCC_LPUART1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 20),
+	SCC_USART4 = _REG_BIT(RCC_APBSMENR1_OFFSET, 19),
+	SCC_USART3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 18),
+	SCC_USART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 17),
+	SCC_SPI2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 14),
+	SCC_TIM7 = _REG_BIT(RCC_APBSMENR1_OFFSET, 5),
+	SCC_TIM6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 4),
+	SCC_TIM3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 1),
+	SCC_TIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 0),
+
+	SCC_ADC = _REG_BIT(RCC_APBSMENR2_OFFSET, 20),
+	SCC_TIM17 = _REG_BIT(RCC_APBSMENR2_OFFSET, 18),
+	SCC_TIM16 = _REG_BIT(RCC_APBSMENR2_OFFSET, 17),
+	SCC_TIM15 = _REG_BIT(RCC_APBSMENR2_OFFSET, 16),
+	SCC_TIM14 = _REG_BIT(RCC_APBSMENR2_OFFSET, 15),
+	SCC_USART1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 14),
+	SCC_SPI1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 12),
+	SCC_TIM1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 11),
+	SCC_SYSCFG = _REG_BIT(RCC_APBSMENR2_OFFSET, 0),
+};
+
+enum rcc_periph_rst {
+	RST_GPIOF = _REG_BIT(RCC_IOPRSTR_OFFSET, 5),
+	RST_GPIOE = _REG_BIT(RCC_IOPRSTR_OFFSET, 4),
+	RST_GPIOD = _REG_BIT(RCC_IOPRSTR_OFFSET, 3),
+	RST_GPIOC = _REG_BIT(RCC_IOPRSTR_OFFSET, 2),
+	RST_GPIOB = _REG_BIT(RCC_IOPRSTR_OFFSET, 1),
+	RST_GPIOA = _REG_BIT(RCC_IOPRSTR_OFFSET, 0),
+
+	RST_RNG = _REG_BIT(RCC_AHBRSTR_OFFSET, 18),
+	RST_AES = _REG_BIT(RCC_AHBRSTR_OFFSET, 16),
+	RST_CRC = _REG_BIT(RCC_AHBRSTR_OFFSET, 12),
+	RST_FLASH = _REG_BIT(RCC_AHBRSTR_OFFSET, 8),
+	RST_DMA = _REG_BIT(RCC_AHBRSTR_OFFSET, 0),
+	RST_DMA1 = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), /* Compatibility */
+
+	RST_LPTIM1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 31),
+	RST_LPTIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 30),
+	RST_DAC1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 29),
+	RST_PWR = _REG_BIT(RCC_APBRSTR1_OFFSET, 28),
+	RST_DBG = _REG_BIT(RCC_APBRSTR1_OFFSET, 27),
+	RST_UCPD1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 26),
+	RST_UCPD2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 25),
+	RST_CEC = _REG_BIT(RCC_APBRSTR1_OFFSET, 24),
+	RST_I2C2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 22),
+	RST_I2C1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 21),
+	RST_LPUART1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 20),
+	RST_USART4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 19),
+	RST_USART3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 18),
+	RST_USART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 17),
+	RST_SPI2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 14),
+	RST_TIM7 = _REG_BIT(RCC_APBRSTR1_OFFSET, 5),
+	RST_TIM6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 4),
+	RST_TIM3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 1),
+	RST_TIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 0),
+
+	RST_ADC = _REG_BIT(RCC_APBRSTR2_OFFSET, 20),
+	RST_TIM17 = _REG_BIT(RCC_APBRSTR2_OFFSET, 18),
+	RST_TIM16 = _REG_BIT(RCC_APBRSTR2_OFFSET, 17),
+	RST_TIM15 = _REG_BIT(RCC_APBRSTR2_OFFSET, 16),
+	RST_TIM14 = _REG_BIT(RCC_APBRSTR2_OFFSET, 15),
+	RST_USART1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 14),
+	RST_SPI1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 12),
+	RST_TIM1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 11),
+	RST_SYSCFG = _REG_BIT(RCC_APBRSTR2_OFFSET, 0),
+};
+
+struct rcc_clock_scale {
+	enum rcc_osc sysclock_source;
+		
+	/* PLL as sysclock source cfg */
+	uint8_t pll_source;
+	uint8_t pll_div;
+	uint8_t pll_mul;
+	uint8_t pllp_div;
+	uint8_t pllq_div;
+	uint8_t pllr_div;
+
+	/* HSI as sysclock source cfg */
+	uint8_t hsisys_div;
+
+	uint8_t hpre;
+	uint8_t ppre;
+	uint8_t flash_waitstates;
+	enum pwr_vos_scale voltage_scale;
+	uint32_t ahb_frequency;
+	uint32_t apb_frequency;
+};
+
+enum rcc_clock {
+	RCC_CLOCK_CONFIG_LSI_32KHZ,
+	RCC_CLOCK_CONFIG_HSI_4MHZ,
+	RCC_CLOCK_CONFIG_HSI_16MHZ,
+	RCC_CLOCK_CONFIG_HSI_PLL_32MHZ,
+	RCC_CLOCK_CONFIG_HSI_PLL_64MHZ,
+	RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ,
+	RCC_CLOCK_CONFIG_END
+};
+
+extern const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END];
+
+#include <libopencm3/stm32/common/rcc_common_all.h>
+
+BEGIN_DECLS
+
+void rcc_osc_on(enum rcc_osc osc);
+void rcc_osc_off(enum rcc_osc osc);
+
+void rcc_css_enable(void);
+void rcc_css_disable(void);
+void rcc_css_int_clear(void);
+int rcc_css_int_flag(void);
+
+void rcc_set_sysclk_source(enum rcc_osc osc);
+void rcc_wait_for_sysclk_status(enum rcc_osc osc);
+enum rcc_osc rcc_system_clock_source(void);
+
+void rcc_set_pll_source(uint32_t pllsrc);
+void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr);
+void rcc_enable_pllp(bool enable);
+void rcc_enable_pllq(bool enable);
+void rcc_enable_pllr(bool enable);
+
+void rcc_set_ppre(uint32_t ppre);
+void rcc_set_hpre(uint32_t hpre);
+void rcc_set_hsisys_div(uint32_t hsidiv);
+void rcc_set_mcopre(uint32_t mcopre);
+
+void rcc_clock_setup(const struct rcc_clock_scale *clock);
+
+void rcc_set_rng_clk_div(uint32_t rng_div);
+void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel);
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/g0/rng.h b/include/libopencm3/stm32/g0/rng.h
new file mode 100644
index 00000000..5df67dba
--- /dev/null
+++ b/include/libopencm3/stm32/g0/rng.h
@@ -0,0 +1,40 @@
+/** @defgroup rng_defines RNG Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx EXTI Control</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+#ifndef LIBOPENCM3_RNG_H
+#define LIBOPENCM3_RNG_H
+
+#include <libopencm3/stm32/common/rng_common_v1.h>
+
+/* --- RNG_CR values ------------------------------------------------------- */
+
+/** Clock error detection : CED = 0 : Detection Enabled */
+#define RNG_CR_CED		(1 << 5)
+
+#endif
+/**@}*/
diff --git a/include/libopencm3/stm32/g0/spi.h b/include/libopencm3/stm32/g0/spi.h
new file mode 100644
index 00000000..0fbe0765
--- /dev/null
+++ b/include/libopencm3/stm32/g0/spi.h
@@ -0,0 +1,34 @@
+/** @defgroup spi_defines SPI Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx SPI</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_SPI_H
+#define LIBOPENCM3_SPI_H
+
+#include <libopencm3/stm32/common/spi_common_all.h>
+#include <libopencm3/stm32/common/spi_common_v1_frf.h>
+
+#endif
diff --git a/include/libopencm3/stm32/g0/timer.h b/include/libopencm3/stm32/g0/timer.h
new file mode 100644
index 00000000..1f102ba8
--- /dev/null
+++ b/include/libopencm3/stm32/g0/timer.h
@@ -0,0 +1,74 @@
+/** @defgroup timer_defines Timer Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx Timers</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_TIMER_H
+#define LIBOPENCM3_TIMER_H
+
+#include <libopencm3/stm32/common/timer_common_all.h>
+
+/**@{*/
+
+/* Option Register (TIMx_OR1) */
+#define TIM_OR1(tim_base)		MMIO32((tim_base) + 0x50)
+#define TIM2_OR1			TIM_OR1(TIM2)
+#define TIM3_OR1			TIM_OR1(TIM3)
+
+/* Alternate Function (TIMx_AF1) */
+#define TIM_AF1(tim_base)		MMIO32((tim_base) + 0x60)
+#define TIM2_AF1			TIM_AF1(TIM2)
+#define TIM3_AF1			TIM_AF1(TIM3)
+#define TIM16_AF1			TIM_AF1(TIM16)
+#define TIM17_AF1			TIM_AF1(TIM17)
+
+/* Input Selection Register (TIMx_TISEL) */
+#define TIM_TISEL(tim_base)		MMIO32((tim_base) + 0x68)
+#define TIM2_TISEL			TIM_TISEL(TIM2)
+#define TIM3_TISEL			TIM_TISEL(TIM3)
+#define TIM14_TISEL			TIM_TISEL(TIM14)
+#define TIM16_TISEL			TIM_TISEL(TIM16)
+#define TIM17_TISEL			TIM_TISEL(TIM17)
+
+/* --- TIMx_OR1 values ---------------------------------------------------- */
+
+/* OCREF_CLR: ocref_clr Source Selection */
+#define TIM_OR1_OCREF_CLR			(1 << 0)
+
+/** @defgroup tim_or1_ocref_clr TIM_OR1_OCREF_CLR Source Selection
+@{*/
+#define TIM_OR1_OCREF_CLR_COMP1			(0)
+#define TIM_OR1_OCREF_CLR_COMP2			(1)
+/**@}*/
+
+BEGIN_DECLS
+
+END_DECLS
+
+/**@}*/
+
+#endif
diff --git a/include/libopencm3/stm32/g0/usart.h b/include/libopencm3/stm32/g0/usart.h
new file mode 100644
index 00000000..2078bf53
--- /dev/null
+++ b/include/libopencm3/stm32/g0/usart.h
@@ -0,0 +1,48 @@
+/** @defgroup usart_defines USART Defines
+ *
+ * @ingroup STM32G0xx_defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32G0xx USART</b>
+ *
+ * @version 1.0.0
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_USART_H
+#define LIBOPENCM3_USART_H
+
+#include <libopencm3/stm32/common/usart_common_all.h>
+#include <libopencm3/stm32/common/usart_common_v2.h>
+
+/**@{*/
+
+/** @defgroup usart_reg_base USART register base addresses
+ * Holds all the U(S)ART peripherals supported.
+ * @{
+ */
+#define USART1				USART1_BASE
+#define USART2				USART2_BASE
+#define USART3				USART3_BASE
+#define USART4				USART4_BASE
+#define LPUART1				LPUART1_BASE
+/**@}*/
+
+/**@}*/
+#endif