[Style] Fixed style in the newly added F3 code.

8 files changed, 135 insertions, 116 deletions

diff --git a/include/libopencm3/stm32/common/gpio_common_f234.h b/include/libopencm3/stm32/common/gpio_common_f234.h
index 5d52635e..0b4191db 100644
--- a/include/libopencm3/stm32/common/gpio_common_f234.h
+++ b/include/libopencm3/stm32/common/gpio_common_f234.h
@@ -54,7 +54,7 @@ specific memorymap.h header before including this header file.*/
 
 /**@}*/
 
-/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------------- */
+/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
 
 /* Port mode register (GPIOx_MODER) */
 #define GPIO_MODER(port)		MMIO32(port + 0x00)
diff --git a/include/libopencm3/stm32/common/gpio_common_f24.h b/include/libopencm3/stm32/common/gpio_common_f24.h
index d9f7ecf7..2b37b97f 100644
--- a/include/libopencm3/stm32/common/gpio_common_f24.h
+++ b/include/libopencm3/stm32/common/gpio_common_f24.h
@@ -51,7 +51,7 @@ specific memorymap.h header before including this header file.*/
 #define GPIOI				GPIO_PORT_I_BASE
 /**@}*/
 
-/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------------- */
+/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
 
 /* Port mode register (GPIOx_MODER) */
 #define GPIOG_MODER			GPIO_MODER(GPIOG)
@@ -108,4 +108,4 @@ specific memorymap.h header before including this header file.*/
 #else
 #warning "gpio_common_f24.h should not be included explicitly, only via gpio.h"
 #endif
-/** @endcond */
\ No newline at end of file
+/** @endcond */
diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h
index dacba8d7..6bac5acc 100644
--- a/include/libopencm3/stm32/f3/adc.h
+++ b/include/libopencm3/stm32/f3/adc.h
@@ -416,7 +416,10 @@
 /* OVRMOD: Overrun Mode */
 #define ADC_CFGR_OVRMOD		(1 << 12)
 
-/* EXTEN[1:0]: External trigger enable and polarity selection for regular channels */
+/*
+ * EXTEN[1:0]: External trigger enable and polarity selection for regular
+ * channels
+ */
 #define ADC_CFGR_EXTEN_DISABLED		(0x0 << 10)
 #define ADC_CFGR_EXTEN_RISING_EDGE	(0x1 << 10)
 #define ADC_CFGR_EXTEN_FALLING_EDGE	(0x2 << 10)
@@ -619,7 +622,10 @@
 
 /* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */
 
-/* JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels */
+/*
+ * JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected
+ * channels
+ */
 #define ADC_JSQR_JEXTEN_DISABLED	(0x0 << 6)
 #define ADC_JSQR_JEXTEN_RISING_EDGE	(0x1 << 6)
 #define ADC_JSQR_JEXTEN_FALLING_EDGE	(0x2 << 6)
@@ -661,7 +667,10 @@
 
 /* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */
 
-/* Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits OFFSET1_CH[4:0] */
+/*
+ * Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits
+ * OFFSET1_CH[4:0]
+ */
 
 
 /*------- ADC_OFR2 values ---------*/
@@ -671,7 +680,10 @@
 
 /* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */
 
-/* Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits OFFSET2_CH[4:0] */
+/*
+ * Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits
+ * OFFSET2_CH[4:0]
+ */
 
 
 /*------- ADC_OFR3 values ---------*/
@@ -681,7 +693,10 @@
 
 /* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */
 
-/* Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits OFFSET3_CH[4:0] */
+/*
+ * Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits
+ * OFFSET3_CH[4:0]
+ */
 
 
 /*------- ADC_OFR4 values ---------*/
@@ -691,7 +706,10 @@
 
 /* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */
 
-/* Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits OFFSET4_CH[4:0] */
+/*
+ * Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits
+ * OFFSET4_CH[4:0]
+ */
 
 
 /*------- ADC_JDRy, y= 1..4 values -------*/
@@ -795,13 +813,13 @@
 /*-------- ADC_CCR values ------------*/
 
 /* VBATEN: VBAT enable */
-#define ADC_CCR_VBATEN  		(1 << 24)
+#define ADC_CCR_VBATEN			(1 << 24)
 
 /* TSEN: Temperature sensor enable */
-#define ADC_CCR_TSEN  			(1 << 23)
+#define ADC_CCR_TSEN			(1 << 23)
 
 /* VREFEN: VREFINT enable */
-#define ADC_CCR_VREFEN 			(1 << 22)
+#define ADC_CCR_VREFEN			(1 << 22)
 
 /* CKMODE[1:0]: ADC clock mode */
 #define ADC_CCR_CKMODE_CKX		(0x0 << 16)
@@ -813,7 +831,7 @@
 
 /* MDMA[1:0]: Direct memory access mode for dual ADC mode */
 #define ADC_CCR_MDMA_DISABLE		(0x0 << 14)
-//#define ADC_CCR_MDMA_RESERVED		(0x1 << 14)
+/*#define ADC_CCR_MDMA_RESERVED		(0x1 << 14)*/
 #define ADC_CCR_MDMA_12_10_BIT		(0x2 << 14)
 #define ADC_CCR_MDMA_8_6_BIT		(0x3 << 14)
 
@@ -850,9 +868,10 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc);
 void adc_enable_automatic_injected_group_conversion(uint32_t adc);
 void adc_disable_automatic_injected_group_conversion(uint32_t adc);
 void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
-void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel);
-//void adc_enable_scan_mode(uint32_t adc);
-//void adc_disable_scan_mode(uint32_t adc);
+void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
+						    uint8_t channel);
+/*void adc_enable_scan_mode(uint32_t adc);*/
+/*void adc_disable_scan_mode(uint32_t adc);*/
 void adc_enable_eoc_interrupt_injected(uint32_t adc);
 void adc_disable_eoc_interrupt_injected(uint32_t adc);
 void adc_enable_all_awd_interrupt(uint32_t adc);
@@ -883,8 +902,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
 
 void adc_set_clk_prescale(uint32_t prescaler);
 void adc_set_multi_mode(uint32_t mode);
-void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity);
-void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity);
+void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
+					 uint32_t polarity);
+void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
+					  uint32_t polarity);
 void adc_set_resolution(uint32_t adc, uint16_t resolution);
 void adc_enable_overrun_interrupt(uint32_t adc);
 void adc_disable_overrun_interrupt(uint32_t adc);
@@ -893,15 +914,12 @@ void adc_clear_overrun_flag(uint32_t adc);
 bool adc_awd(uint32_t adc);
 void adc_eoc_after_each(uint32_t adc);
 void adc_eoc_after_group(uint32_t adc);
-//void adc_set_dma_continue(uint32_t adc);
-//void adc_set_dma_terminate(uint32_t adc);
+/*void adc_set_dma_continue(uint32_t adc);*/
+/*void adc_set_dma_terminate(uint32_t adc);*/
 void adc_enable_temperature_sensor(void);
 void adc_disable_temperature_sensor(void);
 
 END_DECLS
 
 
-#endif 
-
-
-
+#endif
diff --git a/include/libopencm3/stm32/f3/crc.h b/include/libopencm3/stm32/f3/crc.h
index b6c66109..8e76f354 100644
--- a/include/libopencm3/stm32/f3/crc.h
+++ b/include/libopencm3/stm32/f3/crc.h
@@ -36,7 +36,7 @@ LGPL License Terms @ref lgpl_license
 #include <libopencm3/stm32/memorymap.h>
 #include <libopencm3/stm32/common/crc_common_all.h>
 
-/* --- CRC registers ------------------------------------------------------- */ 
+/* --- CRC registers ------------------------------------------------------- */
 
 /* Initial CRC value (CRC_INIT) */
 #define CRC_INIT			MMIO32(CRC_BASE + 0x10)
@@ -61,11 +61,11 @@ LGPL License Terms @ref lgpl_license
 #define CRC_CR_POLYSIZE_8		(0x2 << 3)
 #define CRC_CR_POLYSIZE_7		(0x3 << 3)
 
-/* --- CRC_INIT values ------------------------------------------------------- */
+/* --- CRC_INIT values ----------------------------------------------------- */
 
 /* Bits 31:0 CRC_INIT: Programmable initial CRC value */
 
-/* --- CRC_POL values ------------------------------------------------------- */
+/* --- CRC_POL values ------------------------------------------------------ */
 
 /* Bits 31:0 POL[31:0]: Programmable polynomial */
 
diff --git a/include/libopencm3/stm32/f3/i2c.h b/include/libopencm3/stm32/f3/i2c.h
index 09cc9677..652f57e3 100644
--- a/include/libopencm3/stm32/f3/i2c.h
+++ b/include/libopencm3/stm32/f3/i2c.h
@@ -39,7 +39,7 @@ LGPL License Terms @ref lgpl_license
 /* --- Convenience macros -------------------------------------------------- */
 
 /* I2C register base addresses (for convenience) */
-/****************************************************************************/
+/*****************************************************************************/
 /** @defgroup i2c_reg_base I2C register base address
 @ingroup i2c_defines
 
@@ -225,7 +225,7 @@ LGPL License Terms @ref lgpl_license
 
 /* OA1EN: Own Address 1 enable */
 #define I2C_OAR1_OA1EN_DISABLE		(0x0 << 15)
-#define I2C_OAR1_OA1EN_ENABLE		(0x1 <<15)
+#define I2C_OAR1_OA1EN_ENABLE		(0x1 << 15)
 
 /* OA1MODE Own Address 1 10-bit mode */
 #define I2C_OAR1_OA1MODE		(1 << 10)
@@ -258,7 +258,7 @@ LGPL License Terms @ref lgpl_license
 
 /* OA2[7:1]: Interface address */
 
-/* --- I2Cx_TIMINGR values ---------------------------------------------------- */
+/* --- I2Cx_TIMINGR values ------------------------------------------------- */
 
 /* PRESC[3:0]: Timing prescaler (31,28) */
 #define I2C_TIMINGR_PRESC_SHIFT 28
@@ -280,12 +280,12 @@ LGPL License Terms @ref lgpl_license
 #define I2C_TIMINGR_SCLL_SHIFT 0
 #define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)
 
-/* --- I2Cx_TIEMOUTR values ---------------------------------------------------- */
+/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */
 
 /* TEXTEN: Extended clock timeout enable */
 #define I2C_TIEMOUTR_TEXTEN		(1 << 31)
 
-//Not clear yet.
+/* XXX: Not clear yet. */
 /* TIMEOUTB[11:0]: Bus timeout B */
 
 /* TIMOUTEN: Clock timeout enable */
@@ -295,14 +295,14 @@ LGPL License Terms @ref lgpl_license
 #define I2C_TIEMOUTR_TIDLE_SCL_LOW	(0x0 << 12)
 #define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH	(0x1 << 12)
 
-//Not clear yet.
+/* XXX: Not clear yet. */
 /* TIMEOUTA[11:0]: Bus Timeout A */
 
-/* --- I2Cx_ISR values ---------------------------------------------------- */
+/* --- I2Cx_ISR values ----------------------------------------------------- */
 
 /* Bits 31:24 Reserved, must be kept at reset value */
 
-//Not clear yet.
+/* XXX: Not clear yet. */
 /* ADDCODE[6:0]: Address match code (Slave mode) */
 
 /* DIR: Transfer direction (Slave mode) */
@@ -354,7 +354,7 @@ LGPL License Terms @ref lgpl_license
 /* TXE: Transmit data register empty (transmitters) */
 #define I2C_ISR_TXE			(1 << 0)
 
-/* --- I2Cx_ICR values ---------------------------------------------------- */
+/* --- I2Cx_ICR values ----------------------------------------------------- */
 
 /* ALERTCF: Alert flag clear */
 #define I2C_ICR_ALERTCF			(1 << 13)
@@ -435,12 +435,13 @@ void i2c_enable_rxdma(uint32_t i2c);
 void i2c_disable_rxdma(uint32_t i2c);
 void i2c_enable_txdma(uint32_t i2c);
 void i2c_disable_txdma(uint32_t i2c);
-void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data);
-void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data);
+void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
+	       uint8_t size, uint8_t *data);
+void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
+	      uint8_t size, uint8_t *data);
 
 END_DECLS
 
 /**@}*/
 
 #endif
-
diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h
index d03826a4..45683499 100644
--- a/include/libopencm3/stm32/f3/rcc.h
+++ b/include/libopencm3/stm32/f3/rcc.h
@@ -67,7 +67,7 @@
 /* MCO: Microcontroller clock output */
 #define RCC_CFGR_MCO_SHIFT			24
 #define RCC_CFGR_MCO_DISABLED			0x0
-//Reserve RCC_CFGR_MCO				0x1
+/*Reserve RCC_CFGR_MCO				0x1*/
 #define RCC_CFGR_MCO_LSI			0x2
 #define RCC_CFGR_MCO_LSE			0x3
 #define RCC_CFGR_MCO_SYSCLK			0x4
@@ -100,47 +100,47 @@
 
 /* PPRE2: APB high-speed prescaler (APB2) */
 #define RCC_CFGR_PPRE2_SHIFT			11
-// 0XX: HCLK not divided
-#define RCC_CFGR_PPRE2_DIV_NONE            0x0
+/* 0XX: HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV_NONE			0x0
 
-#define RCC_CFGR_PPRE2_DIV_2               0x4
-#define RCC_CFGR_PPRE2_DIV_4               0x5
-#define RCC_CFGR_PPRE2_DIV_8               0x6
-#define RCC_CFGR_PPRE2_DIV_16              0x7
+#define RCC_CFGR_PPRE2_DIV_2			0x4
+#define RCC_CFGR_PPRE2_DIV_4			0x5
+#define RCC_CFGR_PPRE2_DIV_8			0x6
+#define RCC_CFGR_PPRE2_DIV_16			0x7
 
 /* PPRE1:APB Low-speed prescaler (APB1) */
 #define RCC_CFGR_PPRE1_SHIFT			8
-// 0XX: HCLK not divided
-#define RCC_CFGR_PPRE1_DIV_NONE            0x0
-#define RCC_CFGR_PPRE1_DIV_2               0x4
-#define RCC_CFGR_PPRE1_DIV_4               0x5
-#define RCC_CFGR_PPRE1_DIV_8               0x6
-#define RCC_CFGR_PPRE1_DIV_16              0x7
+/* 0XX: HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV_NONE			0x0
+#define RCC_CFGR_PPRE1_DIV_2			0x4
+#define RCC_CFGR_PPRE1_DIV_4			0x5
+#define RCC_CFGR_PPRE1_DIV_8			0x6
+#define RCC_CFGR_PPRE1_DIV_16			0x7
 
 /* HPRE: HLCK prescaler */
-#define RCC_CFGR_HPRE_SHIFT                     4
-// 0XXX: SYSCLK not divided
-#define RCC_CFGR_HPRE_DIV_NONE  	         0x0
-#define RCC_CFGR_HPRE_DIV_2     	         0x8
-#define RCC_CFGR_HPRE_DIV_4     	         0x9
-#define RCC_CFGR_HPRE_DIV_8     	         0xA
-#define RCC_CFGR_HPRE_DIV_16    	         0xB
-#define RCC_CFGR_HPRE_DIV_64    	         0xC
-#define RCC_CFGR_HPRE_DIV_128   	         0xD
-#define RCC_CFGR_HPRE_DIV_256   	         0xE
-#define RCC_CFGR_HPRE_DIV_512	                 0xF
+#define RCC_CFGR_HPRE_SHIFT			4
+/* 0XXX: SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV_NONE			0x0
+#define RCC_CFGR_HPRE_DIV_2			0x8
+#define RCC_CFGR_HPRE_DIV_4			0x9
+#define RCC_CFGR_HPRE_DIV_8			0xA
+#define RCC_CFGR_HPRE_DIV_16			0xB
+#define RCC_CFGR_HPRE_DIV_64			0xC
+#define RCC_CFGR_HPRE_DIV_128			0xD
+#define RCC_CFGR_HPRE_DIV_256			0xE
+#define RCC_CFGR_HPRE_DIV_512			0xF
 
 /* SWS: System clock switch status */
-#define RCC_CFGR_SWS_SHIFT                      2
-#define RCC_CFGR_SWS_HSI                        0x0
-#define RCC_CFGR_SWS_HSE                        0x1
-#define RCC_CFGR_SWS_PLL                        0x2
+#define RCC_CFGR_SWS_SHIFT			2
+#define RCC_CFGR_SWS_HSI			0x0
+#define RCC_CFGR_SWS_HSE			0x1
+#define RCC_CFGR_SWS_PLL			0x2
 
 /* SW: System clock switch */
-#define RCC_CFGR_SW_SHIFT                       0
-#define RCC_CFGR_SW_HSI                         0x0
-#define RCC_CFGR_SW_HSE                         0x1
-#define RCC_CFGR_SW_PLL                         0x2
+#define RCC_CFGR_SW_SHIFT			0
+#define RCC_CFGR_SW_HSI				0x0
+#define RCC_CFGR_SW_HSE				0x1
+#define RCC_CFGR_SW_PLL				0x2
 
 /* --- RCC_CIR values ------------------------------------------------------ */
 
@@ -203,7 +203,7 @@
 #define RCC_APB1RSTR_TIM3RST			(1 << 1)
 #define RCC_APB1RSTR_TIM2RST			(1 << 0)
 
-/* --- RCC_AHBENR values ------------------------------------------------- */
+/* --- RCC_AHBENR values --------------------------------------------------- */
 #define RCC_AHBENR_ADC34EN			(1 << 29)
 #define RCC_AHBENR_ADC12EN			(1 << 28)
 #define RCC_AHBENR_TSCEN			(1 << 24)
@@ -215,7 +215,7 @@
 #define RCC_AHBENR_IOPAEN			(1 << 17)
 #define RCC_AHBENR_CRCEN			(1 << 1)
 
-/* --- RCC_APB2ENR values ------------------------------------------------- */
+/* --- RCC_APB2ENR values -------------------------------------------------- */
 
 #define RCC_APB2ENR_TIM17EN			(1 << 18)
 #define RCC_APB2ENR_TIM16EN			(1 << 17)
@@ -226,7 +226,7 @@
 #define RCC_APB2ENR_TIM1EN			(1 << 11)
 #define RCC_APB2ENR_SYSCFGEN			(1 << 0)
 
-/* --- RCC_APB1ENR values ------------------------------------------------- */
+/* --- RCC_APB1ENR values -------------------------------------------------- */
 
 #define RCC_APB1ENR_DACEN			(1 << 29)
 #define RCC_APB1ENR_PWREN			(1 << 28)
@@ -267,7 +267,7 @@
 #define RCC_CSR_LSIRDY				(1 << 1)
 #define RCC_CSR_LSION				(1 << 0)
 
-/* --- RCC_AHBRSTR values ------------------------------------------------------ */
+/* --- RCC_AHBRSTR values -------------------------------------------------- */
 #define RCC_AHBRSTR_ADC34RST			(1 << 29)
 #define RCC_AHBRSTR_ADC12RST			(1 << 28)
 #define RCC_AHBRSTR_TSCRST			(1 << 24)
@@ -278,7 +278,7 @@
 #define RCC_AHBRSTR_IOPBRST			(1 << 18)
 #define RCC_AHBRSTR_IOPARST			(1 << 17)
 
-/* --- RCC_CFGR2 values ------------------------------------------------------ */
+/* --- RCC_CFGR2 values ---------------------------------------------------- */
 /* ADC34PRES: ADC34 prescaler */
 #define RCC_CFGR2_ADC34PRES_SHIFT		9
 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1	0x10
@@ -293,11 +293,11 @@
 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64	0x19
 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128	0x1A
 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256	0x1B
-//OTHERS
-//#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256	0x
+/* OTHERS */
+/* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256	0x */
 
 /* ADC12PRES ADC prescaler */
-//REVISAR DIRECCIONES
+/* REVISAR DIRECCIONES */
 #define RCC_CFGR2_ADC12PRES_SHIFT		4
 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1	0x10
 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2	0x11
@@ -311,11 +311,11 @@
 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64	0x19
 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128	0x1A
 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256	0x1B
-//OTHERS
-//#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256	0x
+/* OTHERS */
+/* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256	0x */
 
 /* PREDIV[3:0] PREDIV division factor */
-//REVISAR DIRECCIONES
+/* REVISAR DIRECCIONES */
 #define RCC_CFGR2_PREDIV_SHIFT			0
 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE	0x0
 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2	0x1
@@ -334,7 +334,7 @@
 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15	0xE
 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16	0xF
 
-/* --- RCC_CFGR3 values ------------------------------------------------------ */
+/* --- RCC_CFGR3 values ---------------------------------------------------- */
 #define RCC_CFGR3_TIM8SW			(1 << 9)
 #define RCC_CFGR3_TIM1SW			(1 << 8)
 #define RCC_CFGR3_I2C2SW			(1 << 5)
@@ -377,48 +377,48 @@ extern uint32_t rcc_ppre2_frequency;
 
 /* --- Function prototypes ------------------------------------------------- */
 
-typedef enum {
-  CLOCK_44MHZ,
-  CLOCK_48MHZ,
-  CLOCK_64MHZ,
-  CLOCK_END
-} rcc_clock_t;
+enum rcc_clock {
+	CLOCK_44MHZ,
+	CLOCK_48MHZ,
+	CLOCK_64MHZ,
+	CLOCK_END
+};
 
 typedef struct {
-  uint8_t pll;
-  uint8_t pllsrc;
-  uint32_t flash_config;
-  uint8_t hpre;
-  uint8_t ppre1;
-  uint8_t ppre2;
-  uint8_t power_save;
-  uint32_t apb1_frequency;
-  uint32_t apb2_frequency;
+	uint8_t pll;
+	uint8_t pllsrc;
+	uint32_t flash_config;
+	uint8_t hpre;
+	uint8_t ppre1;
+	uint8_t ppre2;
+	uint8_t power_save;
+	uint32_t apb1_frequency;
+	uint32_t apb2_frequency;
 } clock_scale_t;
 
 extern const clock_scale_t hsi_8mhz[CLOCK_END];
 
-typedef enum {
+enum osc {
 	PLL, HSE, HSI, LSE, LSI
 } osc_t;
 
 BEGIN_DECLS
 
-void rcc_osc_ready_int_clear(osc_t osc);
-void rcc_osc_ready_int_enable(osc_t osc);
-void rcc_osc_ready_int_disable(osc_t osc);
-int rcc_osc_ready_int_flag(osc_t osc);
+void rcc_osc_ready_int_clear(enum osc osc);
+void rcc_osc_ready_int_enable(enum osc osc);
+void rcc_osc_ready_int_disable(enum osc osc);
+int rcc_osc_ready_int_flag(enum osc osc);
 void rcc_css_int_clear(void);
 int rcc_css_int_flag(void);
-void rcc_wait_for_osc_ready(osc_t osc);
-void rcc_wait_for_osc_not_ready(osc_t osc);
-void rcc_wait_for_sysclk_status(osc_t osc);
-void rcc_osc_on(osc_t osc);
-void rcc_osc_off(osc_t osc);
+void rcc_wait_for_osc_ready(enum osc osc);
+void rcc_wait_for_osc_not_ready(enum osc osc);
+void rcc_wait_for_sysclk_status(enum osc osc);
+void rcc_osc_on(enum osc osc);
+void rcc_osc_off(enum osc osc);
 void rcc_css_enable(void);
 void rcc_css_disable(void);
-void rcc_osc_bypass_enable(osc_t osc);
-void rcc_osc_bypass_disable(osc_t osc);
+void rcc_osc_bypass_enable(enum osc osc);
+void rcc_osc_bypass_disable(enum osc osc);
 void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
 void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
 void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);
diff --git a/include/libopencm3/stm32/f3/spi.h b/include/libopencm3/stm32/f3/spi.h
index e4bbf277..6b13b3a5 100644
--- a/include/libopencm3/stm32/f3/spi.h
+++ b/include/libopencm3/stm32/f3/spi.h
@@ -63,7 +63,7 @@ LGPL License Terms @ref lgpl_license
 #define SPI_CR2_FRXTH			(1 << 12)
 
 /* DS [3:0]: Data size */
-// 0x0 - 0x2 NOT USED
+/* 0x0 - 0x2 NOT USED */
 #define SPI_CR2_DS_4BIT			(0x3 << 8)
 #define SPI_CR2_DS_5BIT			(0x4 << 8)
 #define SPI_CR2_DS_6BIT			(0x5 << 8)
@@ -109,4 +109,4 @@ uint8_t spi_read8(uint32_t spi);
 
 END_DECLS
 
-#endif
\ No newline at end of file
+#endif
diff --git a/include/libopencm3/stm32/f3/usart.h b/include/libopencm3/stm32/f3/usart.h
index 42b846c7..34f68a85 100644
--- a/include/libopencm3/stm32/f3/usart.h
+++ b/include/libopencm3/stm32/f3/usart.h
@@ -253,7 +253,7 @@ LGPL License Terms @ref lgpl_license
 /* ADDM7:7-bit Address Detection/4-bit Address Detection */
 #define USART_CR2_ADDM7			(1 << 4)
 
-/* ADD[3:0]: Addres of the usart node 
+/* ADD[3:0]: Addres of the usart node
 #define USART_CR2_ADD_MASK              0xF */
 
 /* --- USART_CR3 values ---------------------------------------------------- */
@@ -263,13 +263,13 @@ LGPL License Terms @ref lgpl_license
 
 /* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */
 #define USART_CR3_WUS_ON		(0x0 << 20)
-// RESERVE #define USART_CR3_WUS	(0x1 << 20)
+/* RESERVE #define USART_CR3_WUS	(0x1 << 20) */
 #define USART_CR3_WUS_START_BIT		(0x2 << 20)
 #define USART_CR3_WUS_RXNE		(0x3 << 20)
 
 /* SCARCNT[2:0]: Smartcard auto-retry count */
 #define USART_CR3_SCARCNT_OFF		(0x0 << 17)
-// 0x1 to 0x7: number of automatic retransmission attempts
+/* 0x1 to 0x7: number of automatic retransmission attempts */
 
 /* DEP: Driver enable polarity selection */
 #define USART_CR3_DEP			(1 << 15)
@@ -345,7 +345,7 @@ LGPL License Terms @ref lgpl_license
 
 /* --- USART_RTOR values --------------------------------------------------- */
 
-//Preguntar
+/* XXX: Preguntar */
 /* BLEN[7:0]: Block Length */
 #define USART_RTOR_BLEN1_MASK             (0xFF << 24)