diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2019-06-17 23:37:09 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2019-06-18 01:33:32 +0300 |
| commit | 2d0d29d9469cdc82cda27f85879e1b9ffbd323ca (patch) | |
| tree | 97418a060ede01646f63f2d73302cd41abc39895 /include | |
| parent | c28a5a81cf17e47af2907de2c6b1146bf2afa98e (diff) | |
doc: stm32l1: timer: fix params, missing groupings
Diffstat (limited to 'include')
| -rw-r--r-- | include/libopencm3/stm32/l1/timer.h | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/include/libopencm3/stm32/l1/timer.h b/include/libopencm3/stm32/l1/timer.h index aa993e86..faef4346 100644 --- a/include/libopencm3/stm32/l1/timer.h +++ b/include/libopencm3/stm32/l1/timer.h @@ -37,6 +37,8 @@ LGPL License Terms @ref lgpl_license #include <libopencm3/stm32/common/timer_common_all.h> +/**@{*/ + /* * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: * CNT, ARR, CCR1, CCR2, CCR3, CCR4 @@ -51,10 +53,7 @@ LGPL License Terms @ref lgpl_license /* ITR1_RMP */ /****************************************************************************/ -/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal -Trigger 1 Remap -@ingroup timer_defines - +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Internal Trigger 1 Remap @{*/ /** Internal Trigger 1 remapped to timer 10 output compare */ #define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0) @@ -67,9 +66,7 @@ Trigger 1 Remap /* ITR2_RMP */ /****************************************************************************/ -/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap -@ingroup timer_defines - +/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Internal Trigger 2 Remap @{*/ /** Internal Trigger 1 remapped to timer 11 output compare */ #define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0) @@ -86,4 +83,6 @@ void timer_set_option(uint32_t timer_peripheral, uint32_t option); END_DECLS +/**@}*/ + #endif |