swm050: new MCU family

SWM050 is a series of MCU made by Foshan Synwit Tech. It contains a
Cortex-M0 CPU core, 8KiB of Flash and 1KiB of SRAM. The only peripherals
are GPIO, Timer and WDT. There's only two parts in this series, with
either TSSOP-8 or SSOP-16 packages.

This commit introduces the interrupt vector and GPIO support for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

6 files changed, 169 insertions, 0 deletions

diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h
index 62be168c..b7e2810b 100644
--- a/include/libopencm3/dispatch/nvic.h
+++ b/include/libopencm3/dispatch/nvic.h
@@ -75,6 +75,9 @@
 #elif defined(VF6XX)
 #	include <libopencm3/vf6xx/nvic.h>
 
+#elif defined(SWM050)
+#       include <libopencm3/swm050/nvic.h>
+
 #else
 #	warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0"
 
diff --git a/include/libopencm3/swm050/gpio.h b/include/libopencm3/swm050/gpio.h
new file mode 100644
index 00000000..f31689a9
--- /dev/null
+++ b/include/libopencm3/swm050/gpio.h
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/swm050/memorymap.h>
+
+/* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup gpio_defines
+
+@{*/
+#define GPIO0				(1 << 0)
+#define GPIO1				(1 << 1)
+#define GPIO2				(1 << 2)
+#define GPIO3				(1 << 3)
+#define GPIO4				(1 << 4)
+#define GPIO5				(1 << 5)
+#define GPIO6				(1 << 6)
+#define GPIO7				(1 << 7)
+#define GPIO8				(1 << 8)
+#define GPIO9				(1 << 9)
+#define GPIO_ALL			0x3ff
+/**@}*/
+
+/* GPIO direction definitions */
+/** @defgroup gpio_dir GPIO Pin Direction
+@ingroup gpio_defines
+@{*/
+#define GPIO_INPUT			0x0
+#define GPIO_OUTPUT			0x1
+/**@}*/
+
+#define GPIO_DATA			MMIO32(GPIO_BASE + 0x0)
+#define GPIO_DIR			MMIO32(GPIO_BASE + 0x4)
+#define GPIO_EXT			MMIO32(GPIO_BASE + 0x4c)
+
+#define GPIO_INTEN			MMIO32(GPIO_BASE + 0x30)
+#define GPIO_INTMASK			MMIO32(GPIO_BASE + 0x34)
+#define GPIO_INTLEVEL			MMIO32(GPIO_BASE + 0x38)
+#define GPIO_INTPOLARITY		MMIO32(GPIO_BASE + 0x3c)
+#define GPIO_INTSTATUS			MMIO32(GPIO_BASE + 0x40)
+#define GPIO_INTRAWSTATUS		MMIO32(GPIO_BASE + 0x44)
+#define GPIO_INTEOI			MMIO32(GPIO_BASE + 0x48)
+
+#define SWD_SEL				MMIO32(SYSTEM_CON_BASE + 0x30)
+#define GPIO_SEL			MMIO32(SYSTEM_CON_BASE + 0x80)
+#define GPIO_PULLUP			MMIO32(SYSTEM_CON_BASE + 0x90)
+#define GPIO_INEN			MMIO32(SYSTEM_CON_BASE + 0xe0)
+
+BEGIN_DECLS
+
+void gpio_set(uint16_t gpios);
+void gpio_clear(uint16_t gpios);
+uint16_t gpio_get(uint16_t gpios);
+void gpio_toggle(uint16_t gpios);
+
+void gpio_input(uint16_t gpios);
+void gpio_output(uint16_t gpios);
+void gpio_sel_af(uint16_t gpios, bool af_en);
+void gpio_pullup(uint16_t gpios, bool en);
+void gpio_in_en(uint16_t gpios, bool en);
+
+void gpio_sel_swd(bool en);
+
+END_DECLS
+
+#endif
diff --git a/include/libopencm3/swm050/irq.json b/include/libopencm3/swm050/irq.json
new file mode 100644
index 00000000..339d81eb
--- /dev/null
+++ b/include/libopencm3/swm050/irq.json
@@ -0,0 +1,21 @@
+{
+    "irqs": [
+        "timer_se0",
+        "timer_se1",
+        "wdt",
+        "cp",
+	"gpioa0",
+	"gpioa1",
+	"gpioa2",
+	"gpioa3",
+	"gpioa4",
+	"gpioa5",
+	"gpioa6",
+	"gpioa7",
+	"gpioa8",
+	"gpioa9"
+    ],
+    "partname_humanreadable": "SWM050 series",
+    "partname_doxygen": "SWM050",
+    "includeguard": "LIBOPENCM3_SWM050_NVIC_H"
+}
diff --git a/include/libopencm3/swm050/memorymap.h b/include/libopencm3/swm050/memorymap.h
new file mode 100644
index 00000000..97fe23df
--- /dev/null
+++ b/include/libopencm3/swm050/memorymap.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* Memory map for all buses */
+#define PERIPH_BASE			(0x40000000U)
+
+#define SYSTEM_CON_BASE			(PERIPH_BASE + 0x0)
+#define GPIO_BASE			(PERIPH_BASE + 0x1000)
+#define TIMER_SE0_BASE			(PERIPH_BASE + 0x2000)
+#define TIMER_SE1_BASE			(PERIPH_BASE + 0x2400)
+#define WDT_BASE			(PERIPH_BASE + 0x19000)
+#define SYSCTL_BASE			(PERIPH_BASE + 0xf0000)
+
+#endif
diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h
index f7b039e4..e8ac859f 100644
--- a/include/libopencmsis/dispatch/irqhandlers.h
+++ b/include/libopencmsis/dispatch/irqhandlers.h
@@ -59,6 +59,8 @@
 /* Yes, we use the same interrupt table for both LM3S and LM4F */
 #	include <libopencmsis/lm3s/irqhandlers.h>
 
+#elif defined(SWM050)
+#	include <libopencmsis/swm050/irqhandlers.h>
 #else
 #	warning"no chipset defined; user interrupts are not redirected"
 
diff --git a/include/libopencmsis/swm050/irqhandlers.h b/include/libopencmsis/swm050/irqhandlers.h
new file mode 100644
index 00000000..ef8c95db
--- /dev/null
+++ b/include/libopencmsis/swm050/irqhandlers.h
@@ -0,0 +1,22 @@
+/* This file is part of the libopencm3 project.
+ *
+ * It was generated by the irq2nvic_h script.
+ *
+ * These definitions bend every interrupt handler that is defined CMSIS style
+ * to the weak symbol exported by libopencm3.
+ */
+
+#define TIMER_SE0_IRQHandler timer_se0_isr
+#define TIMER_SE1_IRQHandler timer_se1_isr
+#define WDT_IRQHandler wdt_isr
+#define CP_IRQHandler cp_isr
+#define GPIOA0_IRQHandler gpioa0_isr
+#define GPIOA1_IRQHandler gpioa1_isr
+#define GPIOA2_IRQHandler gpioa2_isr
+#define GPIOA3_IRQHandler gpioa3_isr
+#define GPIOA4_IRQHandler gpioa4_isr
+#define GPIOA5_IRQHandler gpioa5_isr
+#define GPIOA6_IRQHandler gpioa6_isr
+#define GPIOA7_IRQHandler gpioa7_isr
+#define GPIOA8_IRQHandler gpioa8_isr
+#define GPIOA9_IRQHandler gpioa9_isr