diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2019-06-13 01:08:29 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2019-06-13 02:06:28 +0300 |
| commit | 7b6ca4be6b24f2c0d863a800b5da3c4e1131db59 (patch) | |
| tree | f595d5075568991fcd5d2b25da8e8cdcd76fb6a4 /include | |
| parent | 5eefc214f6be9a78433d3dd81a1f3ee91d010d41 (diff) | |
doc: stm32l0: rcc: add groups and tags for bus prescalers
Diffstat (limited to 'include')
| -rw-r--r-- | include/libopencm3/stm32/l0/rcc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index 8fae070b..3bf89416 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -171,24 +171,32 @@ #define RCC_CFGR_STOPWUCK_HSI16 (1<<15) /* PPRE2: APB high-speed prescaler (APB2) */ +/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors +@{*/ #define RCC_CFGR_PPRE2_NODIV 0x0 #define RCC_CFGR_PPRE2_DIV2 0x4 #define RCC_CFGR_PPRE2_DIV4 0x5 #define RCC_CFGR_PPRE2_DIV8 0x6 #define RCC_CFGR_PPRE2_DIV16 0x7 +/**@}*/ #define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE2_SHIFT 11 /* PPRE1: APB low-speed prescaler (APB1) */ +/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors +@{*/ #define RCC_CFGR_PPRE1_NODIV 0x0 #define RCC_CFGR_PPRE1_DIV2 0x4 #define RCC_CFGR_PPRE1_DIV4 0x5 #define RCC_CFGR_PPRE1_DIV8 0x6 #define RCC_CFGR_PPRE1_DIV16 0x7 +/**@}*/ #define RCC_CFGR_PPRE1_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 8 /* HPRE: AHB prescaler */ +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors +@{*/ #define RCC_CFGR_HPRE_NODIV 0x0 #define RCC_CFGR_HPRE_DIV2 0x8 #define RCC_CFGR_HPRE_DIV4 0x9 @@ -198,6 +206,7 @@ #define RCC_CFGR_HPRE_DIV128 0xd #define RCC_CFGR_HPRE_DIV256 0xe #define RCC_CFGR_HPRE_DIV512 0xf +/**@}*/ #define RCC_CFGR_HPRE_MASK 0xf #define RCC_CFGR_HPRE_SHIFT 4 |