diff options
| -rw-r--r-- | Makefile | 3 | ||||
| -rw-r--r-- | include/libopencm3/dispatch/nvic.h | 2 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l4/irq.json | 89 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l4/memorymap.h | 126 | ||||
| -rw-r--r-- | lib/dispatch/vector_nvic.c | 2 | ||||
| -rw-r--r-- | lib/stm32/l4/Makefile | 48 | ||||
| -rw-r--r-- | lib/stm32/l4/libopencm3_stm32l4.ld | 106 |
7 files changed, 375 insertions, 1 deletions
@@ -34,7 +34,8 @@ space:= space+= SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib)) -TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 stm32/l0 stm32/l1 \ +TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ + stm32/l0 stm32/l1 stm32/l4 \ lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 lm3s lm4f \ efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg \ sam/3a sam/3n sam/3s sam/3u sam/3x \ diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index 89e87801..f554fe2a 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -18,6 +18,8 @@ # include <libopencm3/stm32/l0/nvic.h> #elif defined(STM32L1) # include <libopencm3/stm32/l1/nvic.h> +#elif defined(STM32L4) +# include <libopencm3/stm32/l4/nvic.h> #elif defined(EFM32TG) # include <libopencm3/efm32/efm32tg/nvic.h> diff --git a/include/libopencm3/stm32/l4/irq.json b/include/libopencm3/stm32/l4/irq.json new file mode 100644 index 00000000..2e575ac4 --- /dev/null +++ b/include/libopencm3/stm32/l4/irq.json @@ -0,0 +1,89 @@ +{ + "irqs": [ + "wwdg", + "pvd_pvm", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_channel1", + "dma1_channel2", + "dma1_channel3", + "dma1_channel4", + "dma1_channel5", + "dma1_channel6", + "dma1_channel7", + "adc1_2", + "can1_tx", + "can1_rx0", + "can1_rx1", + "can1_sce", + "exti9_5", + "tim1_brk_tim15", + "tim1_up_tim16", + "tim1_trg_com_tim17", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "dfsdm3", + "tim8_brk", + "tim8_up", + "tim8_trg_com", + "tim8_cc", + "adc3", + "fmc", + "sdmmc1", + "tim5", + "spi3", + "uart4", + "uart5", + "tim6_dacunder", + "tim7", + "dma2_channel1", + "dma2_channel2", + "dma2_channel3", + "dma2_channel4", + "dma2_channel5", + "dfsdm0", + "dfsdm1", + "dfsdm2", + "comp", + "lptim1", + "lptim2", + "otg_fs", + "dma2_channel6", + "dma2_channel7", + "lpuart1", + "quadspi", + "i2c3_ev", + "i2c3_er", + "sai1", + "sai2", + "swpmi1", + "tsc", + "lcd", + "aes", + "rng", + "fpu" + ], + "partname_humanreadable": "STM32 L4 series", + "partname_doxygen": "STM32L4", + "includeguard": "LIBOPENCM3_STM32_L4_NVIC_H" +} diff --git a/include/libopencm3/stm32/l4/memorymap.h b/include/libopencm3/stm32/l4/memorymap.h new file mode 100644 index 00000000..dbfe612f --- /dev/null +++ b/include/libopencm3/stm32/l4/memorymap.h @@ -0,0 +1,126 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include <libopencm3/cm3/memorymap.h> + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define FMC1_BANK_BASE (0x60000000U) +#define FMC3_BANK_BASE (0x80000000U) +#define QUADSPI_BANK_BASE (0x90000000U) +#define FMC_QUADSPI_BASE (0xA0000000U) +#define INFO_BASE (0x1fff0000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x80000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC1_BASE (PERIPH_BASE_APB1 + 0x7400) +#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7800) +#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) +#define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000) +#define SWPMI1_BASE (PERIPH_BASE_APB1 + 0x8800) +#define LPTIM2_BASE (PERIPH_BASE_APB1 + 0x9400) + + +/* APB2 */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) +#define VREFBUF_BASE (PERIPH_BASE_APB2 + 0x0030) +#define COMP_BASE (PERIPH_BASE_APB2 + 0x0200) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define FIREWALL_BASE (PERIPH_BASE_APB2 + 0x1C00) +#define SDMMC1_BASE (PERIPH_BASE_APB2 + 0x2800) +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) +#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5400) +#define SAI2_BASE (PERIPH_BASE_APB2 + 0x5800) +#define DFSDM_BASE (PERIPH_BASE_APB2 + 0x6000) + +/* AHB1 */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) + +/* AHB2 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x00000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x00000) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x00000) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x00000) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB2 + 0x1800) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB2 + 0x1c00) +/* Still AHB2, good job ST */ +#define OTG_FS_BASE (0x50000000U + 0x00000) +#define ADC1_BASE (0x50000000U + 0x40000) +#define AES_BASE (0x50000000U + 0x60000) +#define RNG_BASE (0x50000000U + 0x60800) + +/* Private peripherals */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x75e0) +#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7590) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14) +#define DESIG_PACKAGE MMIO16((INFO_BASE + 0x7500)) + +/* ST provided factory calibration values @ 3.0V */ +#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0x75aa)) +#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0x75a8)) +#define ST_TSENSE_CAL2_110C MMIO16((INFO_BASE + 0x75ca)) + +#endif diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 31afaa03..71397ea7 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -14,6 +14,8 @@ # include "../stm32/l0/vector_nvic.c" #elif defined(STM32L1) # include "../stm32/l1/vector_nvic.c" +#elif defined(STM32L4) +# include "../stm32/l4/vector_nvic.c" #elif defined(EFM32TG) # include "../efm32/efm32tg/vector_nvic.c" diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile new file mode 100644 index 00000000..27caaf06 --- /dev/null +++ b/lib/stm32/l4/Makefile @@ -0,0 +1,48 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2015 Karl Palsson <karlp@tweak.net.au> +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see <http://www.gnu.org/licenses/>. +## + +LIBNAME = libopencm3_stm32l4 +SRCLIBDIR ?= ../.. + +FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 +PREFIX ?= arm-none-eabi + +CC = $(PREFIX)-gcc +AR = $(PREFIX)-ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m4 -mthumb $(FP_FLAGS) \ + -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSTM32L4 +TGT_CFLAGS += $(DEBUG_FLAGS) +ARFLAGS = rcs + +# Specific objs +OBJS = + +# common/shared objs +OBJS += + +VPATH += ../../usb:../:../../cm3:../common +VPATH += ../../ethernet + +include ../../Makefile.include diff --git a/lib/stm32/l4/libopencm3_stm32l4.ld b/lib/stm32/l4/libopencm3_stm32l4.ld new file mode 100644 index 00000000..3fc2ccb6 --- /dev/null +++ b/lib/stm32/l4/libopencm3_stm32l4.ld @@ -0,0 +1,106 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* Generic linker script for STM32 targets using libopencm3. */ + +/* Memory regions must be defined in the ld script which includes this one. */ + +/* Enforce emmition of the vector table. */ +EXTERN (vector_table) + +/* Define the entry point of the output file. */ +ENTRY(reset_handler) + +/* Define sections. */ +SECTIONS +{ + .text : { + *(.vectors) /* Vector table */ + *(.text*) /* Program code */ + . = ALIGN(4); + *(.rodata*) /* Read-only data */ + . = ALIGN(4); + } >rom + + /* C++ Static constructors/destructors, also used for __attribute__ + * ((constructor)) and the likes */ + .preinit_array : { + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + } >rom + .init_array : { + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + } >rom + .fini_array : { + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + } >rom + + /* + * Another section used by C++ stuff, appears when using newlib with + * 64bit (long long) printf support + */ + .ARM.extab : { + *(.ARM.extab*) + } >rom + .ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >rom + + . = ALIGN(4); + _etext = .; + + .data : { + _data = .; + *(.data*) /* Read-write initialized data */ + . = ALIGN(4); + _edata = .; + } >ram AT >rom + _data_loadaddr = LOADADDR(.data); + + .bss : { + *(.bss*) /* Read-write zero initialized data */ + *(COMMON) + . = ALIGN(4); + _ebss = .; + } >ram + + /* + * The .eh_frame section appears to be used for C++ exception handling. + * You may need to fix this if you're using C++. + */ + /DISCARD/ : { *(.eh_frame) } + + . = ALIGN(4); + end = .; +} + +PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram)); + |