diff options
| -rw-r--r-- | include/libopencm3/stm32/l0/rcc.h | 8 | ||||
| -rw-r--r-- | lib/stm32/l0/rcc.c | 14 |
2 files changed, 13 insertions, 9 deletions
diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index 3bf89416..59194425 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -142,14 +142,17 @@ #define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO_MASK 0xf -/* PLL Output division selection */ +/** @defgroup rcc_cfgr_pdf PLLDIV PLL division factor + @{*/ #define RCC_CFGR_PLLDIV_DIV2 0x1 #define RCC_CFGR_PLLDIV_DIV3 0x2 #define RCC_CFGR_PLLDIV_DIV4 0x3 +/**@}*/ #define RCC_CFGR_PLLDIV_SHIFT 22 #define RCC_CFGR_PLLDIV_MASK 0x3 -/* PLLMUL: PLL multiplication factor */ +/** @defgroup rcc_cfgr_pmf PLLMUL PLL multiplication factor + @{*/ #define RCC_CFGR_PLLMUL_MUL3 0x0 #define RCC_CFGR_PLLMUL_MUL4 0x1 #define RCC_CFGR_PLLMUL_MUL6 0x2 @@ -159,6 +162,7 @@ #define RCC_CFGR_PLLMUL_MUL24 0x6 #define RCC_CFGR_PLLMUL_MUL32 0x7 #define RCC_CFGR_PLLMUL_MUL48 0x8 +/**@}*/ #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL_MASK 0xf diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index e1401924..39bdaff7 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -309,7 +309,7 @@ void rcc_set_sysclk_source(enum rcc_osc osc) * * @note This only has effect when the PLL is disabled. * - * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf + * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll_multiplier(uint32_t factor) @@ -325,7 +325,7 @@ void rcc_set_pll_multiplier(uint32_t factor) * * @note This only has effect when the PLL is disabled. * - * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf + * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pdf */ void rcc_set_pll_divider(uint32_t factor) @@ -353,7 +353,7 @@ void rcc_set_pll_source(uint32_t pllsrc) * * @note The APB1 clock frequency must not exceed 32MHz. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre + * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre1(uint32_t ppre) @@ -368,7 +368,7 @@ void rcc_set_ppre1(uint32_t ppre) * * @note The APB2 clock frequency must not exceed 32MHz. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre + * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb2pre */ void rcc_set_ppre2(uint32_t ppre) @@ -393,7 +393,7 @@ void rcc_set_hpre(uint32_t hpre) /*---------------------------------------------------------------------------*/ /** @brief Set the range of the MSI oscillator * - * @param range desired range @ref rcc_icscr_msirange + * @param msi_range desired range @ref rcc_icscr_msirange */ void rcc_set_msi_range(uint32_t msi_range) { @@ -448,8 +448,8 @@ void rcc_set_usart2_sel(uint32_t usart2_sel) /*---------------------------------------------------------------------------*/ /** @brief Set the peripheral clock source -* - * @param sel periphral clock source + * @param periph peripheral of desire, eg XXX_BASE + * @param sel peripheral clock source */ void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) { |