diff options
50 files changed, 559 insertions, 559 deletions
diff --git a/include/libopencm3/cm3/itm.h b/include/libopencm3/cm3/itm.h index 8b55119c..d549fc2f 100644 --- a/include/libopencm3/cm3/itm.h +++ b/include/libopencm3/cm3/itm.h @@ -30,9 +30,9 @@ /* --- ITM registers ------------------------------------------------------- */ /* Stimulus Port x (ITM_STIM<sz>(x)) */ -#define ITM_STIM8(n) (MMIO8(ITM_BASE + (n*4))) -#define ITM_STIM16(n) (MMIO16(ITM_BASE + (n*4))) -#define ITM_STIM32(n) (MMIO32(ITM_BASE + (n*4))) +#define ITM_STIM8(n) (MMIO8(ITM_BASE + ((n)*4))) +#define ITM_STIM16(n) (MMIO16(ITM_BASE + ((n)*4))) +#define ITM_STIM32(n) (MMIO32(ITM_BASE + ((n)*4))) /* Trace Enable ports (ITM_TER[x]) */ #define ITM_TER (&MMIO32(ITM_BASE + 0xE00)) diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index 56261beb..09a402b4 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -46,7 +46,7 @@ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \ - (iser_id * 4)) + ((iser_id) * 4)) /* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ @@ -54,7 +54,7 @@ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \ - (icer_id * 4)) + ((icer_id) * 4)) /* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ @@ -62,7 +62,7 @@ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \ - (ispr_id * 4)) + ((ispr_id) * 4)) /* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ @@ -70,7 +70,7 @@ /* Note: 8 32bit Registers */ /* Note: Single register on CM0 */ #define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \ - (icpr_id * 4)) + ((icpr_id) * 4)) /* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ @@ -79,7 +79,7 @@ /* IABR: Interrupt Active Bit Register */ /* Note: 8 32bit Registers */ #define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \ - (iabr_id * 4)) + ((iabr_id) * 4)) #endif /* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ @@ -88,7 +88,7 @@ /* Note: 240 8bit Registers */ /* Note: 32 8bit Registers on CM0 */ #define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \ - ipr_id) + (ipr_id)) #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) /* STIR: Software Trigger Interrupt Register */ diff --git a/include/libopencm3/cm3/scb.h b/include/libopencm3/cm3/scb.h index 0a6dcaef..7050ffae 100644 --- a/include/libopencm3/cm3/scb.h +++ b/include/libopencm3/cm3/scb.h @@ -46,7 +46,7 @@ /* SHP: System Handler Priority Registers */ /* Note: 12 8bit registers */ -#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id)) #define SCB_SHPR1 MMIO32(SCB_BASE + 0x18) #define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C) #define SCB_SHPR3 MMIO32(SCB_BASE + 0x20) diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h index 7bf98601..b4801549 100644 --- a/include/libopencm3/cm3/scs.h +++ b/include/libopencm3/cm3/scs.h @@ -44,7 +44,7 @@ /* System Handler Priority 8 bits Registers, SHPR1/2/3 */ /* Note: 12 8bit Registers */ -#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id) +#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id)) /* * Debug Halting Control and Status Register (DHCSR). diff --git a/include/libopencm3/ethernet/mac_stm32fxx7.h b/include/libopencm3/ethernet/mac_stm32fxx7.h index 28a0375b..881e822a 100644 --- a/include/libopencm3/ethernet/mac_stm32fxx7.h +++ b/include/libopencm3/ethernet/mac_stm32fxx7.h @@ -57,9 +57,9 @@ #define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) /* i=[0..3] */ -#define ETH_MACAHR(i) MMIO32(ETHERNET_BASE + 0x40+i*8) +#define ETH_MACAHR(i) MMIO32(ETHERNET_BASE + 0x40+(i)*8) /* i=[0..3] */ -#define ETH_MACALR(i) MMIO32(ETHERNET_BASE + 0x44+i*8) +#define ETH_MACALR(i) MMIO32(ETHERNET_BASE + 0x44+(i)*8) /* Ethernet MMC registers */ #define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) diff --git a/include/libopencm3/lm3s/gpio.h b/include/libopencm3/lm3s/gpio.h index 8b120789..f7fdd98c 100644 --- a/include/libopencm3/lm3s/gpio.h +++ b/include/libopencm3/lm3s/gpio.h @@ -64,27 +64,27 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ -#define GPIO_DATA(port) (&MMIO32(port + 0x000)) -#define GPIO_DIR(port) MMIO32(port + 0x400) -#define GPIO_IS(port) MMIO32(port + 0x404) -#define GPIO_IBE(port) MMIO32(port + 0x408) -#define GPIO_IEV(port) MMIO32(port + 0x40c) -#define GPIO_IM(port) MMIO32(port + 0x410) -#define GPIO_RIS(port) MMIO32(port + 0x414) -#define GPIO_MIS(port) MMIO32(port + 0x418) -#define GPIO_ICR(port) MMIO32(port + 0x41c) -#define GPIO_AFSEL(port) MMIO32(port + 0x420) -#define GPIO_DR2R(port) MMIO32(port + 0x500) -#define GPIO_DR4R(port) MMIO32(port + 0x504) -#define GPIO_DR8R(port) MMIO32(port + 0x508) -#define GPIO_ODR(port) MMIO32(port + 0x50c) -#define GPIO_PUR(port) MMIO32(port + 0x510) -#define GPIO_PDR(port) MMIO32(port + 0x514) -#define GPIO_SLR(port) MMIO32(port + 0x518) -#define GPIO_DEN(port) MMIO32(port + 0x51c) -#define GPIO_LOCK(port) MMIO32(port + 0x520) -#define GPIO_CR(port) MMIO32(port + 0x524) -#define GPIO_AMSEL(port) MMIO32(port + 0x528) +#define GPIO_DATA(port) (&MMIO32((port) + 0x000)) +#define GPIO_DIR(port) MMIO32((port) + 0x400) +#define GPIO_IS(port) MMIO32((port) + 0x404) +#define GPIO_IBE(port) MMIO32((port) + 0x408) +#define GPIO_IEV(port) MMIO32((port) + 0x40c) +#define GPIO_IM(port) MMIO32((port) + 0x410) +#define GPIO_RIS(port) MMIO32((port) + 0x414) +#define GPIO_MIS(port) MMIO32((port) + 0x418) +#define GPIO_ICR(port) MMIO32((port) + 0x41c) +#define GPIO_AFSEL(port) MMIO32((port) + 0x420) +#define GPIO_DR2R(port) MMIO32((port) + 0x500) +#define GPIO_DR4R(port) MMIO32((port) + 0x504) +#define GPIO_DR8R(port) MMIO32((port) + 0x508) +#define GPIO_ODR(port) MMIO32((port) + 0x50c) +#define GPIO_PUR(port) MMIO32((port) + 0x510) +#define GPIO_PDR(port) MMIO32((port) + 0x514) +#define GPIO_SLR(port) MMIO32((port) + 0x518) +#define GPIO_DEN(port) MMIO32((port) + 0x51c) +#define GPIO_LOCK(port) MMIO32((port) + 0x520) +#define GPIO_CR(port) MMIO32((port) + 0x524) +#define GPIO_AMSEL(port) MMIO32((port) + 0x528) BEGIN_DECLS diff --git a/include/libopencm3/lm4f/gpio.h b/include/libopencm3/lm4f/gpio.h index 5f90ad37..a2b02b5c 100644 --- a/include/libopencm3/lm4f/gpio.h +++ b/include/libopencm3/lm4f/gpio.h @@ -90,92 +90,92 @@ * ---------------------------------------------------------------------------*/ /* GPIO Data */ -#define GPIO_DATA(port) (&MMIO32(port + 0x000)) +#define GPIO_DATA(port) (&MMIO32((port) + 0x000)) /* GPIO Direction */ -#define GPIO_DIR(port) MMIO32(port + 0x400) +#define GPIO_DIR(port) MMIO32((port) + 0x400) /* GPIO Interrupt Sense */ -#define GPIO_IS(port) MMIO32(port + 0x404) +#define GPIO_IS(port) MMIO32((port) + 0x404) /* GPIO Interrupt Both Edges */ -#define GPIO_IBE(port) MMIO32(port + 0x408) +#define GPIO_IBE(port) MMIO32((port) + 0x408) /* GPIO Interrupt Event */ -#define GPIO_IEV(port) MMIO32(port + 0x40c) +#define GPIO_IEV(port) MMIO32((port) + 0x40c) /* GPIO Interrupt Mask */ -#define GPIO_IM(port) MMIO32(port + 0x410) +#define GPIO_IM(port) MMIO32((port) + 0x410) /* GPIO Raw Interrupt Status */ -#define GPIO_RIS(port) MMIO32(port + 0x414) +#define GPIO_RIS(port) MMIO32((port) + 0x414) /* GPIO Masked Interrupt Status */ -#define GPIO_MIS(port) MMIO32(port + 0x418) +#define GPIO_MIS(port) MMIO32((port) + 0x418) /* GPIO Interrupt Clear */ -#define GPIO_ICR(port) MMIO32(port + 0x41c) +#define GPIO_ICR(port) MMIO32((port) + 0x41c) /* GPIO Alternate Function Select */ -#define GPIO_AFSEL(port) MMIO32(port + 0x420) +#define GPIO_AFSEL(port) MMIO32((port) + 0x420) /* GPIO 2-mA Drive Select */ -#define GPIO_DR2R(port) MMIO32(port + 0x500) +#define GPIO_DR2R(port) MMIO32((port) + 0x500) /* GPIO 4-mA Drive Select */ -#define GPIO_DR4R(port) MMIO32(port + 0x504) +#define GPIO_DR4R(port) MMIO32((port) + 0x504) /* GPIO 8-mA Drive Select */ -#define GPIO_DR8R(port) MMIO32(port + 0x508) +#define GPIO_DR8R(port) MMIO32((port) + 0x508) /* GPIO Open Drain Select */ -#define GPIO_ODR(port) MMIO32(port + 0x50c) +#define GPIO_ODR(port) MMIO32((port) + 0x50c) /* GPIO Pull-Up Select */ -#define GPIO_PUR(port) MMIO32(port + 0x510) +#define GPIO_PUR(port) MMIO32((port) + 0x510) /* GPIO Pull-Down Select */ -#define GPIO_PDR(port) MMIO32(port + 0x514) +#define GPIO_PDR(port) MMIO32((port) + 0x514) /* GPIO Slew Rate Control Select */ -#define GPIO_SLR(port) MMIO32(port + 0x518) +#define GPIO_SLR(port) MMIO32((port) + 0x518) /* GPIO Digital Enable */ -#define GPIO_DEN(port) MMIO32(port + 0x51c) +#define GPIO_DEN(port) MMIO32((port) + 0x51c) /* GPIO Lock */ -#define GPIO_LOCK(port) MMIO32(port + 0x520) +#define GPIO_LOCK(port) MMIO32((port) + 0x520) /* GPIO Commit */ -#define GPIO_CR(port) MMIO32(port + 0x524) +#define GPIO_CR(port) MMIO32((port) + 0x524) /* GPIO Analog Mode Select */ -#define GPIO_AMSEL(port) MMIO32(port + 0x528) +#define GPIO_AMSEL(port) MMIO32((port) + 0x528) /* GPIO Port Control */ -#define GPIO_PCTL(port) MMIO32(port + 0x52C) +#define GPIO_PCTL(port) MMIO32((port) + 0x52C) /* GPIO ADC Control */ -#define GPIO_ADCCTL(port) MMIO32(port + 0x530) +#define GPIO_ADCCTL(port) MMIO32((port) + 0x530) /* GPIO DMA Control */ -#define GPIO_DMACTL(port) MMIO32(port + 0x534) +#define GPIO_DMACTL(port) MMIO32((port) + 0x534) /* GPIO Peripheral Identification */ -#define GPIO_PERIPH_ID4(port) MMIO32(port + 0xFD0) -#define GPIO_PERIPH_ID5(port) MMIO32(port + 0xFD4) -#define GPIO_PERIPH_ID6(port) MMIO32(port + 0xFD8) -#define GPIO_PERIPH_ID7(port) MMIO32(port + 0xFDC) -#define GPIO_PERIPH_ID0(port) MMIO32(port + 0xFE0) -#define GPIO_PERIPH_ID1(port) MMIO32(port + 0xFE4) -#define GPIO_PERIPH_ID2(port) MMIO32(port + 0xFE8) -#define GPIO_PERIPH_ID3(port) MMIO32(port + 0xFEC) +#define GPIO_PERIPH_ID4(port) MMIO32((port) + 0xFD0) +#define GPIO_PERIPH_ID5(port) MMIO32((port) + 0xFD4) +#define GPIO_PERIPH_ID6(port) MMIO32((port) + 0xFD8) +#define GPIO_PERIPH_ID7(port) MMIO32((port) + 0xFDC) +#define GPIO_PERIPH_ID0(port) MMIO32((port) + 0xFE0) +#define GPIO_PERIPH_ID1(port) MMIO32((port) + 0xFE4) +#define GPIO_PERIPH_ID2(port) MMIO32((port) + 0xFE8) +#define GPIO_PERIPH_ID3(port) MMIO32((port) + 0xFEC) /* GPIO PrimeCell Identification */ -#define GPIO_PCELL_ID0(port) MMIO32(port + 0xFF0) -#define GPIO_PCELL_ID1(port) MMIO32(port + 0xFF4) -#define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8) -#define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC) +#define GPIO_PCELL_ID0(port) MMIO32((port) + 0xFF0) +#define GPIO_PCELL_ID1(port) MMIO32((port) + 0xFF4) +#define GPIO_PCELL_ID2(port) MMIO32((port) + 0xFF8) +#define GPIO_PCELL_ID3(port) MMIO32((port) + 0xFFC) /* ============================================================================= * Convenience enums diff --git a/include/libopencm3/lm4f/ssi.h b/include/libopencm3/lm4f/ssi.h index be9e4a82..fb422819 100644 --- a/include/libopencm3/lm4f/ssi.h +++ b/include/libopencm3/lm4f/ssi.h @@ -57,53 +57,53 @@ * ---------------------------------------------------------------------------*/ /* SSI Control 0 */ -#define SSI_CR0(port) MMIO32(port + 0x000) +#define SSI_CR0(port) MMIO32((port) + 0x000) /* SSI Control 1 */ -#define SSI_CR1(port) MMIO32(port + 0x004) +#define SSI_CR1(port) MMIO32((port) + 0x004) /* SSI Data */ -#define SSI_DR(port) MMIO32(port + 0x008) +#define SSI_DR(port) MMIO32((port) + 0x008) /* SSI Satus */ -#define SSI_SR(port) MMIO32(port + 0x00C) +#define SSI_SR(port) MMIO32((port) + 0x00C) /* SSI Clock Prescale */ -#define SSI_CPSR(port) MMIO32(port + 0x010) +#define SSI_CPSR(port) MMIO32((port) + 0x010) /* SSI Interrupt Mask */ -#define SSI_IM(port) MMIO32(port + 0x014) +#define SSI_IM(port) MMIO32((port) + 0x014) /* SSI Raw Interrupt Status */ -#define SSI_RIS(port) MMIO32(port + 0x018) +#define SSI_RIS(port) MMIO32((port) + 0x018) /* SSI Masked Interrupt Status */ -#define SSI_MIS(port) MMIO32(port + 0x01C) +#define SSI_MIS(port) MMIO32((port) + 0x01C) /* SSI Interrupt Clear */ -#define SSI_ICR(port) MMIO32(port + 0x020) +#define SSI_ICR(port) MMIO32((port) + 0x020) /* SSI DMA Control */ -#define SSI_DMACTL(port) MMIO32(port + 0x024) +#define SSI_DMACTL(port) MMIO32((port) + 0x024) /* SSI Clock Configuration */ -#define SSI_CC(port) MMIO32(port + 0xFC8) +#define SSI_CC(port) MMIO32((port) + 0xFC8) /* SSI Peripheral Identification */ -#define SSI_PERIPH_ID4(port) MMIO32(port + 0xFD0) -#define SSI_PERIPH_ID5(port) MMIO32(port + 0xFD4) -#define SSI_PERIPH_ID6(port) MMIO32(port + 0xFD8) -#define SSI_PERIPH_ID7(port) MMIO32(port + 0xFDC) -#define SSI_PERIPH_ID0(port) MMIO32(port + 0xFE0) -#define SSI_PERIPH_ID1(port) MMIO32(port + 0xFE4) -#define SSI_PERIPH_ID2(port) MMIO32(port + 0xFE8) -#define SSI_PERIPH_ID3(port) MMIO32(port + 0xFEC) +#define SSI_PERIPH_ID4(port) MMIO32((port) + 0xFD0) +#define SSI_PERIPH_ID5(port) MMIO32((port) + 0xFD4) +#define SSI_PERIPH_ID6(port) MMIO32((port) + 0xFD8) +#define SSI_PERIPH_ID7(port) MMIO32((port) + 0xFDC) +#define SSI_PERIPH_ID0(port) MMIO32((port) + 0xFE0) +#define SSI_PERIPH_ID1(port) MMIO32((port) + 0xFE4) +#define SSI_PERIPH_ID2(port) MMIO32((port) + 0xFE8) +#define SSI_PERIPH_ID3(port) MMIO32((port) + 0xFEC) /* SSI PrimeCell Identification */ -#define SSI_PCELL_ID0(port) MMIO32(port + 0xFF0) -#define SSI_PCELL_ID1(port) MMIO32(port + 0xFF4) -#define SSI_PCELL_ID2(port) MMIO32(port + 0xFF8) -#define SSI_PCELL_ID3(port) MMIO32(port + 0xFFC) +#define SSI_PCELL_ID0(port) MMIO32((port) + 0xFF0) +#define SSI_PCELL_ID1(port) MMIO32((port) + 0xFF4) +#define SSI_PCELL_ID2(port) MMIO32((port) + 0xFF8) +#define SSI_PCELL_ID3(port) MMIO32((port) + 0xFFC) /* ============================================================================= * Function prototypes @@ -115,4 +115,4 @@ END_DECLS /**@}*/ #endif /* LM4F_SSI_H */ -
\ No newline at end of file + diff --git a/include/libopencm3/lm4f/uart.h b/include/libopencm3/lm4f/uart.h index 5bd7e378..d12f30e9 100644 --- a/include/libopencm3/lm4f/uart.h +++ b/include/libopencm3/lm4f/uart.h @@ -61,104 +61,104 @@ * ---------------------------------------------------------------------------*/ /* UART data register */ -#define UART_DR(uart_base) MMIO32(uart_base + 0x00) +#define UART_DR(uart_base) MMIO32((uart_base) + 0x00) /* UART Receive Status/Error Clear register */ -#define UART_RSR(uart_base) MMIO32(uart_base + 0x04) -#define UART_ECR(uart_base) MMIO32(uart_base + 0x04) +#define UART_RSR(uart_base) MMIO32((uart_base) + 0x04) +#define UART_ECR(uart_base) MMIO32((uart_base) + 0x04) /* UART Flag register */ -#define UART_FR(uart_base) MMIO32(uart_base + 0x18) +#define UART_FR(uart_base) MMIO32((uart_base) + 0x18) /* UART IrDA Low-Power register */ -#define UART_ILPR(uart_base) MMIO32(uart_base + 0x20) +#define UART_ILPR(uart_base) MMIO32((uart_base) + 0x20) /* UART Integer baudrate divisor */ -#define UART_IBRD(uart_base) MMIO32(uart_base + 0x24) +#define UART_IBRD(uart_base) MMIO32((uart_base) + 0x24) /* UART Fractional baudrate divisor */ -#define UART_FBRD(uart_base) MMIO32(uart_base + 0x28) +#define UART_FBRD(uart_base) MMIO32((uart_base) + 0x28) /* UART Line control */ -#define UART_LCRH(uart_base) MMIO32(uart_base + 0x2C) +#define UART_LCRH(uart_base) MMIO32((uart_base) + 0x2C) /* UART Control */ -#define UART_CTL(uart_base) MMIO32(uart_base + 0x30) +#define UART_CTL(uart_base) MMIO32((uart_base) + 0x30) /* UART Interrupt FIFO level select */ -#define UART_IFLS(uart_base) MMIO32(uart_base + 0x34) +#define UART_IFLS(uart_base) MMIO32((uart_base) + 0x34) /* UART Interrupt mask */ -#define UART_IM(uart_base) MMIO32(uart_base + 0x38) +#define UART_IM(uart_base) MMIO32((uart_base) + 0x38) /* UART Raw interrupt status */ -#define UART_RIS(uart_base) MMIO32(uart_base + 0x3C) +#define UART_RIS(uart_base) MMIO32((uart_base) + 0x3C) /* UART Masked Interrupt status */ -#define UART_MIS(uart_base) MMIO32(uart_base + 0x40) +#define UART_MIS(uart_base) MMIO32((uart_base) + 0x40) /* UART Interrupt Clear */ -#define UART_ICR(uart_base) MMIO32(uart_base + 0x44) +#define UART_ICR(uart_base) MMIO32((uart_base) + 0x44) /* UART DMA control */ -#define UART_DMACTL(uart_base) MMIO32(uart_base + 0x48) +#define UART_DMACTL(uart_base) MMIO32((uart_base) + 0x48) /* UART LIN control */ -#define UART_LCTL(uart_base) MMIO32(uart_base + 0x90) +#define UART_LCTL(uart_base) MMIO32((uart_base) + 0x90) /* UART LIN snap shot */ -#define UART_LSS(uart_base) MMIO32(uart_base + 0x94) +#define UART_LSS(uart_base) MMIO32((uart_base) + 0x94) /* UART LIN timer */ -#define UART_LTIM(uart_base) MMIO32(uart_base + 0x98) +#define UART_LTIM(uart_base) MMIO32((uart_base) + 0x98) /* UART 9-Bit self address */ -#define UART_9BITADDR(uart_base) MMIO32(uart_base + 0xA4) +#define UART_9BITADDR(uart_base) MMIO32((uart_base) + 0xA4) /* UART 9-Bit self address mask */ -#define UART_9BITAMASK(uart_base) MMIO32(uart_base + 0xA8) +#define UART_9BITAMASK(uart_base) MMIO32((uart_base) + 0xA8) /* UART Peripheral properties */ -#define UART_PP(uart_base) MMIO32(uart_base + 0xFC0) +#define UART_PP(uart_base) MMIO32((uart_base) + 0xFC0) /* UART Clock configuration */ -#define UART_CC(uart_base) MMIO32(uart_base + 0xFC8) +#define UART_CC(uart_base) MMIO32((uart_base) + 0xFC8) /* UART Peripheral Identification 4 */ -#define UART_PERIPH_ID4(uart_base) MMIO32(uart_base + 0xFD0) +#define UART_PERIPH_ID4(uart_base) MMIO32((uart_base) + 0xFD0) /* UART Peripheral Identification 5 */ -#define UART_PERIPH_ID5(uart_base) MMIO32(uart_base + 0xFD4) +#define UART_PERIPH_ID5(uart_base) MMIO32((uart_base) + 0xFD4) /* UART Peripheral Identification 6 */ -#define UART_PERIPH_ID6(uart_base) MMIO32(uart_base + 0xFD8) +#define UART_PERIPH_ID6(uart_base) MMIO32((uart_base) + 0xFD8) /* UART Peripheral Identification 7 */ -#define UART_PERIPH_ID7(uart_base) MMIO32(uart_base + 0xFDC) +#define UART_PERIPH_ID7(uart_base) MMIO32((uart_base) + 0xFDC) /* UART Peripheral Identification 0 */ -#define UART_PERIPH_ID0(uart_base) MMIO32(uart_base + 0xFE0) +#define UART_PERIPH_ID0(uart_base) MMIO32((uart_base) + 0xFE0) /* UART Peripheral Identification 1 */ -#define UART_PERIPH_ID1(uart_base) MMIO32(uart_base + 0xFE4) +#define UART_PERIPH_ID1(uart_base) MMIO32((uart_base) + 0xFE4) /* UART Peripheral Identification 2 */ -#define UART_PERIPH_ID2(uart_base) MMIO32(uart_base + 0xFE8) +#define UART_PERIPH_ID2(uart_base) MMIO32((uart_base) + 0xFE8) /* UART Peripheral Identification 3 */ -#define UART_PERIPH_ID3(uart_base) MMIO32(uart_base + 0xFEC) +#define UART_PERIPH_ID3(uart_base) MMIO32((uart_base) + 0xFEC) /* UART PrimeCell Identification 0 */ -#define UART_PCELL_ID0(uart_base) MMIO32(uart_base + 0xFF0) +#define UART_PCELL_ID0(uart_base) MMIO32((uart_base) + 0xFF0) /* UART PrimeCell Identification 1 */ -#define UART_PCELL_ID1(uart_base) MMIO32(uart_base + 0xFF4) +#define UART_PCELL_ID1(uart_base) MMIO32((uart_base) + 0xFF4) /* UART PrimeCell Identification 2 */ -#define UART_PCELL_ID2(uart_base) MMIO32(uart_base + 0xFF8) +#define UART_PCELL_ID2(uart_base) MMIO32((uart_base) + 0xFF8) /* UART PrimeCell Identification 3 */ -#define UART_PCELL_ID3(uart_base) MMIO32(uart_base + 0xFFC) +#define UART_PCELL_ID3(uart_base) MMIO32((uart_base) + 0xFFC) /* ============================================================================= diff --git a/include/libopencm3/lm4f/usb.h b/include/libopencm3/lm4f/usb.h index f22d7995..2a4cd2ad 100644 --- a/include/libopencm3/lm4f/usb.h +++ b/include/libopencm3/lm4f/usb.h @@ -114,25 +114,25 @@ #define USB_COUNT0 MMIO8(USB_BASE + 0x108) /* USB Maximum Transmit Data Endpoint [1-7] */ -#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10) +#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + (n)*0x10) /* USB Transmit Control and Status Endpoint [1-7] Low */ -#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10) +#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + (n)*0x10) /* USB Transmit Control and Status Endpoint [1-7] High */ -#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10) +#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + (n)*0x10) /* USB Maximum Receive Data Endpoint [1-7] */ -#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10) +#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + (n)*0x10) /* USB Receive Control and Status Endpoint [1-7] Low */ -#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10) +#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + (n)*0x10) /* USB Receive Control and Status Endpoint [1-7] High */ -#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10) +#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + (n)*0x10) /* USB Receive Byte Count Endpoint [1-7] */ -#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10) +#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + (n)*0x10) /* USB Receive Double Packet Buffer Disable */ #define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340) diff --git a/include/libopencm3/lpc13xx/gpio.h b/include/libopencm3/lpc13xx/gpio.h index 907533a3..f827ecac 100644 --- a/include/libopencm3/lpc13xx/gpio.h +++ b/include/libopencm3/lpc13xx/gpio.h @@ -50,42 +50,42 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ /* GPIO data register (GPIOn_DATA) */ -#define GPIO_DATA(port) MMIO32(port + 0x3ffc) +#define GPIO_DATA(port) MMIO32((port) + 0x3ffc) #define GPIO0_DATA GPIO_DATA(GPIO0) #define GPIO1_DATA GPIO_DATA(GPIO1) #define GPIO2_DATA GPIO_DATA(GPIO2) #define GPIO3_DATA GPIO_DATA(GPIO3) /* GPIO data direction register (GPIOn_DIR) */ -#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO_DIR(port) MMIO32((port) + 0x00) #define GPIO0_DIR GPIO_DIR(GPIO0) #define GPIO1_DIR GPIO_DIR(GPIO1) #define GPIO2_DIR GPIO_DIR(GPIO2) #define GPIO3_DIR GPIO_DIR(GPIO3) /* GPIO interrupt sense register (GPIOn_IS) */ -#define GPIO_IS(port) MMIO32(port + 0x04) +#define GPIO_IS(port) MMIO32((port) + 0x04) #define GPIO0_IS GPIO_IS(GPIO0) #define GPIO1_IS GPIO_IS(GPIO1) #define GPIO2_IS GPIO_IS(GPIO2) #define GPIO3_IS GPIO_IS(GPIO3) /* GPIO interrupt both edges sense register (GPIOn_IBE) */ -#define GPIO_IBE(port) MMIO32(port + 0x08) +#define GPIO_IBE(port) MMIO32((port) + 0x08) #define GPIO0_IBE GPIO_IBE(GPIO0) #define GPIO1_IBE GPIO_IBE(GPIO1) #define GPIO2_IBE GPIO_IBE(GPIO2) #define GPIO3_IBE GPIO_IBE(GPIO3) /* GPIO interrupt event register (GPIOn_IEV) */ -#define GPIO_IEV(port) MMIO32(port + 0x0c) +#define GPIO_IEV(port) MMIO32((port) + 0x0c) #define GPIO0_IEV GPIO_IEV(GPIO0) #define GPIO1_IEV GPIO_IEV(GPIO1) #define GPIO2_IEV GPIO_IEV(GPIO2) #define GPIO3_IEV GPIO_IEV(GPIO3) /* GPIO interrupt mask register (GPIOn_IE) */ -#define GPIO_IE(port) MMIO16(port + 0x10) +#define GPIO_IE(port) MMIO16((port) + 0x10) #define GPIO0_IE GPIO_IE(GPIO0) #define GPIO1_IE GPIO_IE(GPIO1) #define GPIO2_IE GPIO_IE(GPIO2) @@ -93,21 +93,21 @@ LGPL License Terms @ref lgpl_license /* FIXME: IRS or RIS? Datasheet is not consistent here. */ /* GPIO raw interrupt status register (GPIOn_IRS) */ -#define GPIO_IRS(port) MMIO16(port + 0x14) +#define GPIO_IRS(port) MMIO16((port) + 0x14) #define GPIO0_IRS GPIO_IRS(GPIO0) #define GPIO1_IRS GPIO_IRS(GPIO1) #define GPIO2_IRS GPIO_IRS(GPIO2) #define GPIO3_IRS GPIO_IRS(GPIO3) /* GPIO masked interrupt status register (GPIOn_MIS) */ -#define GPIO_MIS(port) MMIO16(port + 0x18) +#define GPIO_MIS(port) MMIO16((port) + 0x18) #define GPIO0_MIS GPIO_MIS(GPIO0) #define GPIO1_MIS GPIO_MIS(GPIO1) #define GPIO2_MIS GPIO_MIS(GPIO2) #define GPIO3_MIS GPIO_MIS(GPIO3) /* GPIO interrupt clear register (GPIOn_IC) */ -#define GPIO_IC(port) MMIO16(port + 0x1c) +#define GPIO_IC(port) MMIO16((port) + 0x1c) #define GPIO0_IC GPIO_IC(GPIO0) #define GPIO1_IC GPIO_IC(GPIO1) #define GPIO2_IC GPIO_IC(GPIO2) diff --git a/include/libopencm3/lpc17xx/gpio.h b/include/libopencm3/lpc17xx/gpio.h index 2aecd6b5..c357f470 100644 --- a/include/libopencm3/lpc17xx/gpio.h +++ b/include/libopencm3/lpc17xx/gpio.h @@ -85,7 +85,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ /* GPIO data direction register (GPIOn_DIR) */ -#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO_DIR(port) MMIO32((port) + 0x00) #define GPIO0_DIR GPIO_DIR(GPIO0) #define GPIO1_DIR GPIO_DIR(GPIO1) #define GPIO2_DIR GPIO_DIR(GPIO2) @@ -93,7 +93,7 @@ LGPL License Terms @ref lgpl_license #define GPIO4_DIR GPIO_DIR(GPIO4) /* GPIO fast mask register (GPIOn_DIR) */ -#define GPIO_MASK(port) MMIO32(port + 0x10) +#define GPIO_MASK(port) MMIO32((port) + 0x10) #define GPIO0_MASK GPIO_MASK(GPIO0) #define GPIO1_MASK GPIO_MASK(GPIO1) #define GPIO2_MASK GPIO_MASK(GPIO2) @@ -101,7 +101,7 @@ LGPL License Terms @ref lgpl_license #define GPIO4_MASK GPIO_MASK(GPIO4) /* GPIO port pin value register (GPIOn_PIN) */ -#define GPIO_PIN(port) MMIO32(port + 0x14) +#define GPIO_PIN(port) MMIO32((port) + 0x14) #define GPIO0_PIN GPIO_PIN(GPIO0) #define GPIO1_PIN GPIO_PIN(GPIO1) #define GPIO2_PIN GPIO_PIN(GPIO2) @@ -109,7 +109,7 @@ LGPL License Terms @ref lgpl_license #define GPIO4_PIN GPIO_PIN(GPIO4) /* GPIO port output set register (GPIOn_SET) */ -#define GPIO_SET(port) MMIO32(port + 0x18) +#define GPIO_SET(port) MMIO32((port) + 0x18) #define GPIO0_SET GPIO_SET(GPIO0) #define GPIO1_SET GPIO_SET(GPIO1) #define GPIO2_SET GPIO_SET(GPIO2) @@ -117,7 +117,7 @@ LGPL License Terms @ref lgpl_license #define GPIO4_SET GPIO_SET(GPIO4) /* GPIO port output clear register (GPIOn_CLR) */ -#define GPIO_CLR(port) MMIO32(port + 0x1C) +#define GPIO_CLR(port) MMIO32((port) + 0x1C) #define GPIO0_CLR GPIO_CLR(GPIO0) #define GPIO1_CLR GPIO_CLR(GPIO1) #define GPIO2_CLR GPIO_CLR(GPIO2) diff --git a/include/libopencm3/lpc43xx/adc.h b/include/libopencm3/lpc43xx/adc.h index c63c1e4c..d506524b 100644 --- a/include/libopencm3/lpc43xx/adc.h +++ b/include/libopencm3/lpc43xx/adc.h @@ -49,62 +49,62 @@ LGPL License Terms @ref lgpl_license /* --- ADC registers ------------------------------------------------------- */ /* A/D Control Register */ -#define ADC_CR(port) MMIO32(port + 0x000) +#define ADC_CR(port) MMIO32((port) + 0x000) #define ADC0_CR ADC_CR(ADC0) #define ADC1_CR ADC_CR(ADC1) /* A/D Global Data Register */ -#define ADC_GDR(port) MMIO32(port + 0x004) +#define ADC_GDR(port) MMIO32((port) + 0x004) #define ADC0_GDR ADC_GDR(ADC0) #define ADC1_GDR ADC_GDR(ADC1) /* A/D Interrupt Enable Register */ -#define ADC_INTEN(port) MMIO32(port + 0x00C) +#define ADC_INTEN(port) MMIO32((port) + 0x00C) #define ADC0_INTEN ADC_INTEN(ADC0) #define ADC1_INTEN ADC_INTEN(ADC1) /* A/D Channel 0 Data Register */ -#define ADC_DR0(port) MMIO32(port + 0x010) +#define ADC_DR0(port) MMIO32((port) + 0x010) #define ADC0_DR0 ADC_DR0(ADC0) #define ADC1_DR0 ADC_DR0(ADC1) /* A/D Channel 1 Data Register */ -#define ADC_DR1(port) MMIO32(port + 0x014) +#define ADC_DR1(port) MMIO32((port) + 0x014) #define ADC0_DR1 ADC_DR1(ADC0) #define ADC1_DR1 ADC_DR1(ADC1) /* A/D Channel 2 Data Register */ -#define ADC_DR2(port) MMIO32(port + 0x018) +#define ADC_DR2(port) MMIO32((port) + 0x018) #define ADC0_DR2 ADC_DR2(ADC0) #define ADC1_DR2 ADC_DR2(ADC1) /* A/D Channel 3 Data Register */ -#define ADC_DR3(port) MMIO32(port + 0x01C) +#define ADC_DR3(port) MMIO32((port) + 0x01C) #define ADC0_DR3 ADC_DR3(ADC0) #define ADC1_DR3 ADC_DR3(ADC1) /* A/D Channel 4 Data Register */ -#define ADC_DR4(port) MMIO32(port + 0x020) +#define ADC_DR4(port) MMIO32((port) + 0x020) #define ADC0_DR4 ADC_DR4(ADC0) #define ADC1_DR4 ADC_DR4(ADC1) /* A/D Channel 5 Data Register */ -#define ADC_DR5(port) MMIO32(port + 0x024) +#define ADC_DR5(port) MMIO32((port) + 0x024) #define ADC0_DR5 ADC_DR5(ADC0) #define ADC1_DR5 ADC_DR5(ADC1) /* A/D Channel 6 Data Register */ -#define ADC_DR6(port) MMIO32(port + 0x028) +#define ADC_DR6(port) MMIO32((port) + 0x028) #define ADC0_DR6 ADC_DR6(ADC0) #define ADC1_DR6 ADC_DR6(ADC1) /* A/D Channel 7 Data Register */ -#define ADC_DR7(port) MMIO32(port + 0x02C) +#define ADC_DR7(port) MMIO32((port) + 0x02C) #define ADC0_DR7 ADC_DR7(ADC0) #define ADC1_DR7 ADC_DR7(ADC1) /* A/D Status Register */ -#define ADC_STAT(port) MMIO32(port + 0x030) +#define ADC_STAT(port) MMIO32((port) + 0x030) #define ADC0_STAT ADC_STAT(ADC0) #define ADC1_STAT ADC_STAT(ADC1) diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h index 67474707..c97521a8 100644 --- a/include/libopencm3/lpc43xx/gpio.h +++ b/include/libopencm3/lpc43xx/gpio.h @@ -693,7 +693,7 @@ LGPL License Terms @ref lgpl_license #define GPIO_W255 (GPIO_PORT_BASE + 0x13FC) /* GPIO data direction register (GPIOn_DIR) */ -#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO_DIR(port) MMIO32((port) + 0x00) #define GPIO0_DIR GPIO_DIR(GPIO0) #define GPIO1_DIR GPIO_DIR(GPIO1) #define GPIO2_DIR GPIO_DIR(GPIO2) @@ -704,7 +704,7 @@ LGPL License Terms @ref lgpl_license #define GPIO7_DIR GPIO_DIR(GPIO7) /* GPIO fast mask register (GPIOn_MASK) */ -#define GPIO_MASK(port) MMIO32(port + 0x80) +#define GPIO_MASK(port) MMIO32((port) + 0x80) #define GPIO0_MASK GPIO_MASK(GPIO0) #define GPIO1_MASK GPIO_MASK(GPIO1) #define GPIO2_MASK GPIO_MASK(GPIO2) @@ -715,7 +715,7 @@ LGPL License Terms @ref lgpl_license #define GPIO7_MASK GPIO_MASK(GPIO7) /* GPIO port pin value register (GPIOn_PIN) */ -#define GPIO_PIN(port) MMIO32(port + 0x100) +#define GPIO_PIN(port) MMIO32((port) + 0x100) #define GPIO0_PIN GPIO_PIN(GPIO0) #define GPIO1_PIN GPIO_PIN(GPIO1) #define GPIO2_PIN GPIO_PIN(GPIO2) @@ -726,7 +726,7 @@ LGPL License Terms @ref lgpl_license #define GPIO7_PIN GPIO_PIN(GPIO7) /* GPIO port masked pin value register (GPIOn_MPIN) */ -#define GPIO_MPIN(port) MMIO32(port + 0x180) +#define GPIO_MPIN(port) MMIO32((port) + 0x180) #define GPIO0_MPIN GPIO_MPIN(GPIO0) #define GPIO1_MPIN GPIO_MPIN(GPIO1) #define GPIO2_MPIN GPIO_MPIN(GPIO2) @@ -737,7 +737,7 @@ LGPL License Terms @ref lgpl_license #define GPIO7_MPIN GPIO_MPIN(GPIO7) /* GPIO port output set register (GPIOn_SET) */ -#define GPIO_SET(port) MMIO32(port + 0x200) +#define GPIO_SET(port) MMIO32((port) + 0x200) #define GPIO0_SET GPIO_SET(GPIO0) #define GPIO1_SET GPIO_SET(GPIO1) #define GPIO2_SET GPIO_SET(GPIO2) @@ -748,7 +748,7 @@ LGPL License Terms @ref lgpl_license #define GPIO7_SET GPIO_SET(GPIO7) /* GPIO port output clear register (GPIOn_CLR) */ -#define GPIO_CLR(port) MMIO32(port + 0x280) +#define GPIO_CLR(port) MMIO32((port) + 0x280) #define GPIO0_CLR GPIO_CLR(GPIO0) #define GPIO1_CLR GPIO_CLR(GPIO1) #define GPIO2_CLR GPIO_CLR(GPIO2) @@ -759,7 +759,7 @@ LGPL License Terms @ref lgpl_license #define GPIO7_CLR GPIO_CLR(GPIO7) /* GPIO port toggle register (GPIOn_NOT) */ -#define GPIO_NOT(port) MMIO32(port + 0x300) +#define GPIO_NOT(port) MMIO32((port) + 0x300) #define GPIO0_NOT GPIO_NOT(GPIO0) #define GPIO1_NOT GPIO_NOT(GPIO1) #define GPIO2_NOT GPIO_NOT(GPIO2) diff --git a/include/libopencm3/lpc43xx/i2c.h b/include/libopencm3/lpc43xx/i2c.h index 2bab0b0d..23c88967 100644 --- a/include/libopencm3/lpc43xx/i2c.h +++ b/include/libopencm3/lpc43xx/i2c.h @@ -48,82 +48,82 @@ LGPL License Terms @ref lgpl_license /* --- I2C registers ------------------------------------------------------- */ /* I2C Control Set Register */ -#define I2C_CONSET(port) MMIO32(port + 0x000) +#define I2C_CONSET(port) MMIO32((port) + 0x000) #define I2C0_CONSET I2C_CONSET(I2C0) #define I2C1_CONSET I2C_CONSET(I2C1) /* I2C Status Register */ -#define I2C_STAT(port) MMIO32(port + 0x004) +#define I2C_STAT(port) MMIO32((port) + 0x004) #define I2C0_STAT I2C_STAT(I2C0) #define I2C1_STAT I2C_STAT(I2C1) /* I2C Data Register */ -#define I2C_DAT(port) MMIO32(port + 0x008) +#define I2C_DAT(port) MMIO32((port) + 0x008) #define I2C0_DAT I2C_DAT(I2C0) #define I2C1_DAT I2C_DAT(I2C1) /* I2C Slave Address Register 0 */ -#define I2C_ADR0(port) MMIO32(port + 0x00C) +#define I2C_ADR0(port) MMIO32((port) + 0x00C) #define I2C0_ADR0 I2C_ADR0(I2C0) #define I2C1_ADR0 I2C_ADR0(I2C1) /* SCH Duty Cycle Register High Half Word */ -#define I2C_SCLH(port) MMIO32(port + 0x010) +#define I2C_SCLH(port) MMIO32((port) + 0x010) #define I2C0_SCLH I2C_SCLH(I2C0) #define I2C1_SCLH I2C_SCLH(I2C1) /* SCL Duty Cycle Register Low Half Word */ -#define I2C_SCLL(port) MMIO32(port + 0x014) +#define I2C_SCLL(port) MMIO32((port) + 0x014) #define I2C0_SCLL I2C_SCLL(I2C0) #define I2C1_SCLL I2C_SCLL(I2C1) /* I2C Control Clear Register */ -#define I2C_CONCLR(port) MMIO32(port + 0x018) +#define I2C_CONCLR(port) MMIO32((port) + 0x018) #define I2C0_CONCLR I2C_CONCLR(I2C0) #define I2C1_CONCLR I2C_CONCLR(I2C1) /* Monitor mode control register */ -#define I2C_MMCTRL(port) MMIO32(port + 0x01C) +#define I2C_MMCTRL(port) MMIO32((port) + 0x01C) #define I2C0_MMCTRL I2C_MMCTRL(I2C0) #define I2C1_MMCTRL I2C_MMCTRL(I2C1) /* I2C Slave Address Register 1 */ -#define I2C_ADR1(port) MMIO32(port + 0x020) +#define I2C_ADR1(port) MMIO32((port) + 0x020) #define I2C0_ADR1 I2C_ADR1(I2C0) #define I2C1_ADR1 I2C_ADR1(I2C1) /* I2C Slave Address Register 2 */ -#define I2C_ADR2(port) MMIO32(port + 0x024) +#define I2C_ADR2(port) MMIO32((port) + 0x024) #define I2C0_ADR2 I2C_ADR2(I2C0) #define I2C1_ADR2 I2C_ADR2(I2C1) /* I2C Slave Address Register 3 */ -#define I2C_ADR3(port) MMIO32(port + 0x028) +#define I2C_ADR3(port) MMIO32((port) + 0x028) #define I2C0_ADR3 I2C_ADR3(I2C0) #define I2C1_ADR3 I2C_ADR3(I2C1) /* Data buffer register */ -#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C) +#define I2C_DATA_BUFFER(port) MMIO32((port) + 0x02C) #define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0) #define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1) /* I2C Slave address mask register 0 */ -#define I2C_MASK0(port) MMIO32(port + 0x030) +#define I2C_MASK0(port) MMIO32((port) + 0x030) #define I2C0_MASK0 I2C_MASK0(I2C0) #define I2C1_MASK0 I2C_MASK0(I2C1) /* I2C Slave address mask register 1 */ -#define I2C_MASK1(port) MMIO32(port + 0x034) +#define I2C_MASK1(port) MMIO32((port) + 0x034) #define I2C0_MASK1 I2C_MASK1(I2C0) #define I2C1_MASK1 I2C_MASK1(I2C1) /* I2C Slave address mask register 2 */ -#define I2C_MASK2(port) MMIO32(port + 0x038) +#define I2C_MASK2(port) MMIO32((port) + 0x038) #define I2C0_MASK2 I2C_MASK2(I2C0) #define I2C1_MASK2 I2C_MASK2(I2C1) /* I2C Slave address mask register 3 */ -#define I2C_MASK3(port) MMIO32(port + 0x03C) +#define I2C_MASK3(port) MMIO32((port) + 0x03C) #define I2C0_MASK3 I2C_MASK3(I2C0) #define I2C1_MASK3 I2C_MASK3(I2C1) diff --git a/include/libopencm3/lpc43xx/i2s.h b/include/libopencm3/lpc43xx/i2s.h index 63f7afb6..442f5bd5 100644 --- a/include/libopencm3/lpc43xx/i2s.h +++ b/include/libopencm3/lpc43xx/i2s.h @@ -48,72 +48,72 @@ LGPL License Terms @ref lgpl_license /* --- I2S registers ------------------------------------------------------- */ /* I2S Digital Audio Output Register */ -#define I2S_DAO(port) MMIO32(port + 0x000) +#define I2S_DAO(port) MMIO32((port) + 0x000) #define I2S0_DAO I2S_DAO(I2S0) #define I2S1_DAO I2S_DAO(I2S1) /* I2S Digital Audio Input Register */ -#define I2S_DAI(port) MMIO32(port + 0x004) +#define I2S_DAI(port) MMIO32((port) + 0x004) #define I2S0_DAI I2S_DAI(I2S0) #define I2S1_DAI I2S_DAI(I2S1) /* I2S Transmit FIFO */ -#define I2S_TXFIFO(port) MMIO32(port + 0x008) +#define I2S_TXFIFO(port) MMIO32((port) + 0x008) #define I2S0_TXFIFO I2S_TXFIFO(I2S0) #define I2S1_TXFIFO I2S_TXFIFO(I2S1) /* I2S Receive FIFO */ -#define I2S_RXFIFO(port) MMIO32(port + 0x00C) +#define I2S_RXFIFO(port) MMIO32((port) + 0x00C) #define I2S0_RXFIFO I2S_RXFIFO(I2S0) #define I2S1_RXFIFO I2S_RXFIFO(I2S1) /* I2S Status Feedback Register */ -#define I2S_STATE(port) MMIO32(port + 0x010) +#define I2S_STATE(port) MMIO32((port) + 0x010) #define I2S0_STATE I2S_STATE(I2S0) #define I2S1_STATE I2S_STATE(I2S1) /* I2S DMA Configuration Register 1 */ -#define I2S_DMA1(port) MMIO32(port + 0x014) +#define I2S_DMA1(port) MMIO32((port) + 0x014) #define I2S0_DMA1 I2S_DMA1(I2S0) #define I2S1_DMA1 I2S_DMA1(I2S1) /* I2S DMA Configuration Register 2 */ -#define I2S_DMA2(port) MMIO32(port + 0x018) +#define I2S_DMA2(port) MMIO32((port) + 0x018) #define I2S0_DMA2 I2S_DMA2(I2S0) #define I2S1_DMA2 I2S_DMA2(I2S1) /* I2S Interrupt Request Control Register */ -#define I2S_IRQ(port) MMIO32(port + 0x01C) +#define I2S_IRQ(port) MMIO32((port) + 0x01C) #define I2S0_IRQ I2S_IRQ(I2S0) #define I2S1_IRQ I2S_IRQ(I2S1) /* I2S Transmit MCLK divider */ -#define I2S_TXRATE(port) MMIO32(port + 0x020) +#define I2S_TXRATE(port) MMIO32((port) + 0x020) #define I2S0_TXRATE I2S_TXRATE(I2S0) #define I2S1_TXRATE I2S_TXRATE(I2S1) /* I2S Receive MCLK divider */ -#define I2S_RXRATE(port) MMIO32(port + 0x024) +#define I2S_RXRATE(port) MMIO32((port) + 0x024) #define I2S0_RXRATE I2S_RXRATE(I2S0) #define I2S1_RXRATE I2S_RXRATE(I2S1) /* I2S Transmit bit rate divider */ -#define I2S_TXBITRATE(port) MMIO32(port + 0x028) +#define I2S_TXBITRATE(port) MMIO32((port) + 0x028) #define I2S0_TXBITRATE I2S_TXBITRATE(I2S0) #define I2S1_TXBITRATE I2S_TXBITRATE(I2S1) /* I2S Receive bit rate divider */ -#define I2S_RXBITRATE(port) MMIO32(port + 0x02C) +#define I2S_RXBITRATE(port) MMIO32((port) + 0x02C) #define I2S0_RXBITRATE I2S_RXBITRATE(I2S0) #define I2S1_RXBITRATE I2S_RXBITRATE(I2S1) /* I2S Transmit mode control */ -#define I2S_TXMODE(port) MMIO32(port + 0x030) +#define I2S_TXMODE(port) MMIO32((port) + 0x030) #define I2S0_TXMODE I2S_TXMODE(I2S0) #define I2S1_TXMODE I2S_TXMODE(I2S1) /* I2S Receive mode control */ -#define I2S_RXMODE(port) MMIO32(port + 0x034) +#define I2S_RXMODE(port) MMIO32((port) + 0x034) #define I2S0_RXMODE I2S_RXMODE(I2S0) #define I2S1_RXMODE I2S_RXMODE(I2S1) diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index b869318a..548ac888 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -87,7 +87,7 @@ LGPL License Terms @ref lgpl_license /* Pin configuration registers */ -#define SCU_SFS(group, pin) MMIO32(group + pin) +#define SCU_SFS(group, pin) MMIO32((group) + (pin)) /* Pins P0_n */ #define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index a336652f..554f7076 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -50,22 +50,22 @@ LGPL License Terms @ref lgpl_license /* --- SSP registers ------------------------------------------------------- */ /* Control Register 0 */ -#define SSP_CR0(port) MMIO32(port + 0x000) +#define SSP_CR0(port) MMIO32((port) + 0x000) #define SSP0_CR0 SSP_CR0(SSP0) #define SSP1_CR0 SSP_CR0(SSP1) /* Control Register 1 */ -#define SSP_CR1(port) MMIO32(port + 0x004) +#define SSP_CR1(port) MMIO32((port) + 0x004) #define SSP0_CR1 SSP_CR1(SSP0) #define SSP1_CR1 SSP_CR1(SSP1) /* Data Register */ -#define SSP_DR(port) MMIO32(port + 0x008) +#define SSP_DR(port) MMIO32((port) + 0x008) #define SSP0_DR SSP_DR(SSP0) #define SSP1_DR SSP_DR(SSP1) /* Status Register */ -#define SSP_SR(port) MMIO32(port + 0x00C) +#define SSP_SR(port) MMIO32((port) + 0x00C) #define SSP0_SR SSP_SR(SSP0) #define SSP1_SR SSP_SR(SSP1) @@ -76,32 +76,32 @@ LGPL License Terms @ref lgpl_license #define SSP_SR_BSY BIT4 /* Clock Prescale Register */ -#define SSP_CPSR(port) MMIO32(port + 0x010) +#define SSP_CPSR(port) MMIO32((port) + 0x010) #define SSP0_CPSR SSP_CPSR(SSP0) #define SSP1_CPSR SSP_CPSR(SSP1) /* Interrupt Mask Set and Clear Register */ -#define SSP_IMSC(port) MMIO32(port + 0x014) +#define SSP_IMSC(port) MMIO32((port) + 0x014) #define SSP0_IMSC SSP_IMSC(SSP0) #define SSP1_IMSC SSP_IMSC(SSP1) /* Raw Interrupt Status Register */ -#define SSP_RIS(port) MMIO32(port + 0x018) +#define SSP_RIS(port) MMIO32((port) + 0x018) #define SSP0_RIS SSP_RIS(SSP0) #define SSP1_RIS SSP_RIS(SSP1) /* Masked Interrupt Status Register */ -#define SSP_MIS(port) MMIO32(port + 0x01C) +#define SSP_MIS(port) MMIO32((port) + 0x01C) #define SSP0_MIS SSP_MIS(SSP0) #define SSP1_MIS SSP_MIS(SSP1) /* SSPICR Interrupt Clear Register */ -#define SSP_ICR(port) MMIO32(port + 0x020) +#define SSP_ICR(port) MMIO32((port) + 0x020) #define SSP0_ICR SSP_ICR(SSP0) #define SSP1_ICR SSP_ICR(SSP1) /* SSP1 DMA control register */ -#define SSP_DMACR(port) MMIO32(port + 0x024) +#define SSP_DMACR(port) MMIO32((port) + 0x024) #define SSP0_DMACR SSP_DMACR(SSP0) #define SSP1_DMACR SSP_DMACR(SSP1) diff --git a/include/libopencm3/lpc43xx/timer.h b/include/libopencm3/lpc43xx/timer.h index 2c691e7b..660c618e 100644 --- a/include/libopencm3/lpc43xx/timer.h +++ b/include/libopencm3/lpc43xx/timer.h @@ -51,119 +51,119 @@ LGPL License Terms @ref lgpl_license /* --- Timer registers ----------------------------------------------------- */ /* Interrupt Register */ -#define TIMER_IR(timer) MMIO32(timer + 0x000) +#define TIMER_IR(timer) MMIO32((timer) + 0x000) #define TIMER0_IR TIMER_IR(TIMER0) #define TIMER1_IR TIMER_IR(TIMER1) #define TIMER2_IR TIMER_IR(TIMER2) #define TIMER3_IR TIMER_IR(TIMER3) /* Timer Control Register */ -#define TIMER_TCR(timer) MMIO32(timer + 0x004) +#define TIMER_TCR(timer) MMIO32((timer) + 0x004) #define TIMER0_TCR TIMER_TCR(TIMER0) #define TIMER1_TCR TIMER_TCR(TIMER1) #define TIMER2_TCR TIMER_TCR(TIMER2) #define TIMER3_TCR TIMER_TCR(TIMER3) /* Timer Counter */ -#define TIMER_TC(timer) MMIO32(timer + 0x008) +#define TIMER_TC(timer) MMIO32((timer) + 0x008) #define TIMER0_TC TIMER_TC(TIMER0) #define TIMER1_TC TIMER_TC(TIMER1) #define TIMER2_TC TIMER_TC(TIMER2) #define TIMER3_TC TIMER_TC(TIMER3) /* Prescale Register */ -#define TIMER_PR(timer) MMIO32(timer + 0x00C) +#define TIMER_PR(timer) MMIO32((timer) + 0x00C) #define TIMER0_PR TIMER_PR(TIMER0) #define TIMER1_PR TIMER_PR(TIMER1) #define TIMER2_PR TIMER_PR(TIMER2) #define TIMER3_PR TIMER_PR(TIMER3) /* Prescale Counter */ -#define TIMER_PC(timer) MMIO32(timer + 0x010) +#define TIMER_PC(timer) MMIO32((timer) + 0x010) #define TIMER0_PC TIMER_PC(TIMER0) #define TIMER1_PC TIMER_PC(TIMER1) #define TIMER2_PC TIMER_PC(TIMER2) #define TIMER3_PC TIMER_PC(TIMER3) /* Match Control Register */ -#define TIMER_MCR(timer) MMIO32(timer + 0x014) +#define TIMER_MCR(timer) MMIO32((timer) + 0x014) #define TIMER0_MCR TIMER_MCR(TIMER0) #define TIMER1_MCR TIMER_MCR(TIMER1) #define TIMER2_MCR TIMER_MCR(TIMER2) #define TIMER3_MCR TIMER_MCR(TIMER3) /* Match Register 0 */ -#define TIMER_MR0(timer) MMIO32(timer + 0x018) +#define TIMER_MR0(timer) MMIO32((timer) + 0x018) #define TIMER0_MR0 TIMER_MR0(TIMER0) #define TIMER1_MR0 TIMER_MR0(TIMER1) #define TIMER2_MR0 TIMER_MR0(TIMER2) #define TIMER3_MR0 TIMER_MR0(TIMER3) /* Match Register 1 */ -#define TIMER_MR1(timer) MMIO32(timer + 0x01C) +#define TIMER_MR1(timer) MMIO32((timer) + 0x01C) #define TIMER0_MR1 TIMER_MR1(TIMER0) #define TIMER1_MR1 TIMER_MR1(TIMER1) #define TIMER2_MR1 TIMER_MR1(TIMER2) #define TIMER3_MR1 TIMER_MR1(TIMER3) /* Match Register 2 */ -#define TIMER_MR2(timer) MMIO32(timer + 0x020) +#define TIMER_MR2(timer) MMIO32((timer) + 0x020) #define TIMER0_MR2 TIMER_MR2(TIMER0) #define TIMER1_MR2 TIMER_MR2(TIMER1) #define TIMER2_MR2 TIMER_MR2(TIMER2) #define TIMER3_MR2 TIMER_MR2(TIMER3) /* Match Register 3 */ -#define TIMER_MR3(timer) MMIO32(timer + 0x024) +#define TIMER_MR3(timer) MMIO32((timer) + 0x024) #define TIMER0_MR3 TIMER_MR3(TIMER0) #define TIMER1_MR3 TIMER_MR3(TIMER1) #define TIMER2_MR3 TIMER_MR3(TIMER2) #define TIMER3_MR3 TIMER_MR3(TIMER3) /* Capture Control Register */ -#define TIMER_CCR(timer) MMIO32(timer + 0x028) +#define TIMER_CCR(timer) MMIO32((timer) + 0x028) #define TIMER0_CCR TIMER_CCR(TIMER0) #define TIMER1_CCR TIMER_CCR(TIMER1) #define TIMER2_CCR TIMER_CCR(TIMER2) #define TIMER3_CCR TIMER_CCR(TIMER3) /* Capture Register 0 */ -#define TIMER_CR0(timer) MMIO32(timer + 0x02C) +#define TIMER_CR0(timer) MMIO32((timer) + 0x02C) #define TIMER0_CR0 TIMER_CR0(TIMER0) #define TIMER1_CR0 TIMER_CR0(TIMER1) #define TIMER2_CR0 TIMER_CR0(TIMER2) #define TIMER3_CR0 TIMER_CR0(TIMER3) /* Capture Register 1 */ -#define TIMER_CR1(timer) MMIO32(timer + 0x030) +#define TIMER_CR1(timer) MMIO32((timer) + 0x030) #define TIMER0_CR1 TIMER_CR1(TIMER0) #define TIMER1_CR1 TIMER_CR1(TIMER1) #define TIMER2_CR1 TIMER_CR1(TIMER2) #define TIMER3_CR1 TIMER_CR1(TIMER3) /* Capture Register 2 */ -#define TIMER_CR2(timer) MMIO32(timer + 0x034) +#define TIMER_CR2(timer) MMIO32((timer) + 0x034) #define TIMER0_CR2 TIMER_CR2(TIMER0) #define TIMER1_CR2 TIMER_CR2(TIMER1) #define TIMER2_CR2 TIMER_CR2(TIMER2) #define TIMER3_CR2 TIMER_CR2(TIMER3) /* Capture Register 3 */ -#define TIMER_CR3(timer) MMIO32(timer + 0x038) +#define TIMER_CR3(timer) MMIO32((timer) + 0x038) #define TIMER0_CR3 TIMER_CR3(TIMER0) #define TIMER1_CR3 TIMER_CR3(TIMER1) #define TIMER2_CR3 TIMER_CR3(TIMER2) #define TIMER3_CR3 TIMER_CR3(TIMER3) /* External Match Register */ -#define TIMER_EMR(timer) MMIO32(timer + 0x03C) +#define TIMER_EMR(timer) MMIO32((timer) + 0x03C) #define TIMER0_EMR TIMER_EMR(TIMER0) #define TIMER1_EMR TIMER_EMR(TIMER1) #define TIMER2_EMR TIMER_EMR(TIMER2) #define TIMER3_EMR TIMER_EMR(TIMER3) /* Count Control Register */ -#define TIMER_CTCR(timer) MMIO32(timer + 0x070) +#define TIMER_CTCR(timer) MMIO32((timer) + 0x070) #define TIMER0_CTCR TIMER_CTCR(TIMER0) #define TIMER1_CTCR TIMER_CTCR(TIMER1) #define TIMER2_CTCR TIMER_CTCR(TIMER2) diff --git a/include/libopencm3/lpc43xx/uart.h b/include/libopencm3/lpc43xx/uart.h index 28830e35..5ec45336 100644 --- a/include/libopencm3/lpc43xx/uart.h +++ b/include/libopencm3/lpc43xx/uart.h @@ -34,66 +34,66 @@ /* --- UART registers ------------------------------------------------------- */ /* Receiver Buffer Register (DLAB=0) Read Only */ -#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */ +#define UART_RBR(port) MMIO32((port) + 0x000) /* 8bits */ /* Transmitter Holding Register (DLAB=0) Write Only */ -#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */ +#define UART_THR(port) MMIO32((port) + 0x000) /* 8bits */ /* Divisor Latch LSB Register (DLAB=1) */ -#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */ +#define UART_DLL(port) MMIO32((port) + 0x000) /* 8bits */ /* Divisor Latch MSB Register (DLAB=1) */ -#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */ +#define UART_DLM(port) MMIO32((port) + 0x004) /* 8bits */ /* Interrupt Enable Register (DLAB=0) */ -#define UART_IER(port) MMIO32(port + 0x004) +#define UART_IER(port) MMIO32((port) + 0x004) /* Interrupt ID Register Read Only */ -#define UART_IIR(port) MMIO32(port + 0x008) +#define UART_IIR(port) MMIO32((port) + 0x008) /* FIFO Control Register Write Only */ -#define UART_FCR(port) MMIO32(port + 0x008) +#define UART_FCR(port) MMIO32((port) + 0x008) /* Line Control Register */ -#define UART_LCR(port) MMIO32(port + 0x00C) +#define UART_LCR(port) MMIO32((port) + 0x00C) /* MCR only for UART1 */ /* Line Status Register */ -#define UART_LSR(port) MMIO32(port + 0x014) +#define UART_LSR(port) MMIO32((port) + 0x014) /* Auto Baud Control Register */ -#define UART_ACR(port) MMIO32(port + 0x020) +#define UART_ACR(port) MMIO32((port) + 0x020) /* IrDA Control Register only for UART0/2/3 */ -#define UART_ICR(port) MMIO32(port + 0x024) +#define UART_ICR(port) MMIO32((port) + 0x024) /* Fractional Divider Register */ -#define UART_FDR(port) MMIO32(port + 0x028) +#define UART_FDR(port) MMIO32((port) + 0x028) /* Oversampling Register only for UART0/2/3 */ -#define UART_OSR(port) MMIO32(port + 0x02C) +#define UART_OSR(port) MMIO32((port) + 0x02C) /* Half-Duplex enable Register only for UART0/2/3 */ -#define UART_HDEN(port) MMIO32(port + 0x040) +#define UART_HDEN(port) MMIO32((port) + 0x040) /* Smart card Interface Register Only for UART0/2/3 */ -#define UART_SCICTRL(port) MMIO32(port + 0x048) +#define UART_SCICTRL(port) MMIO32((port) + 0x048) /* RS-485/EIA-485 Control Register */ -#define UART_RS485CTRL(port) MMIO32(port + 0x04C) +#define UART_RS485CTRL(port) MMIO32((port) + 0x04C) /* RS-485/EIA-485 Address Match Register */ -#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050) +#define UART_RS485ADRMATCH(port) MMIO32((port) + 0x050) /* RS-485/EIA-485 Direction Control Delay Register */ -#define UART_RS485DLY(port) MMIO32(port + 0x054) +#define UART_RS485DLY(port) MMIO32((port) + 0x054) /* Synchronous Mode Control Register only for UART0/2/3 */ -#define UART_SYNCCTRL(port) MMIO32(port + 0x058) +#define UART_SYNCCTRL(port) MMIO32((port) + 0x058) /* Transmit Enable Register */ -#define UART_TER(port) MMIO32(port + 0x05C) +#define UART_TER(port) MMIO32((port) + 0x05C) /* --------------------- BIT DEFINITIONS ----------------------------------- */ /*********************************************************************** @@ -291,7 +291,7 @@ /* IrDA fixed pulse width mode */ #define UART_ICR_FIXPULSE_EN (1 << 2) /* PulseDiv - Configures the pulse when FixPulseEn = 1 */ -#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) +#define UART_ICR_PULSEDIV(n) ((uint32_t)(((n)&0x07)<<3)) /* UART IRDA bit mask */ #define UART_ICR_BITMASK ((uint32_t)(0x3F)) @@ -311,9 +311,9 @@ /* ISO7816-3 protocol T1 is selected*/ #define UART_SCICTRL_PROTSEL_T1 (1 << 2) /* number of retransmission*/ -#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) +#define UART_SCICTRL_TXRETRY(n) ((uint32_t)(((n)&0x07)<<5)) /* Extra guard time*/ -#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) +#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)(((n)&0xFF)<<8)) /********************************************************************* * Macro defines for Macro defines for UART synchronous control register @@ -338,9 +338,9 @@ **********************************************************************/ /* Baud-rate generation pre-scaler divisor */ -#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) +#define UART_FDR_DIVADDVAL(n) ((uint32_t)((n)&0x0F)) /* Baud-rate pre-scaler multiplier value */ -#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) +#define UART_FDR_MULVAL(n) ((uint32_t)(((n)<<4)&0xF0)) /* UART Fractional Divider register bit mask */ #define UART_FDR_BITMASK ((uint32_t)(0xFF)) @@ -354,9 +354,9 @@ * Macro defines for Macro defines for UART FIFO Level register **********************************************************************/ /* Reflects the current level of the UART receiver FIFO */ -#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) +#define UART_FIFOLVL_RX(n) ((uint32_t)((n)&0x0F)) /* Reflects the current level of the UART transmitter FIFO */ -#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) +#define UART_FIFOLVL_TX(n) ((uint32_t)(((n)>>8)&0x0F)) /* UART FIFO Level Register bit mask */ #define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) diff --git a/include/libopencm3/lpc43xx/usb.h b/include/libopencm3/lpc43xx/usb.h index 2f1f1565..9132fb7f 100644 --- a/include/libopencm3/lpc43xx/usb.h +++ b/include/libopencm3/lpc43xx/usb.h @@ -51,7 +51,7 @@ struct usb_transfer_descriptor_t { #define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15) #define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES) -#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, x) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, (x)) #define USB_TD_DTD_TOKEN_IOC_SHIFT (15) #define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT) @@ -59,7 +59,7 @@ struct usb_transfer_descriptor_t { #define USB_TD_DTD_TOKEN_MULTO_SHIFT (10) #define USB_TD_DTD_TOKEN_MULTO_WIDTH (2) #define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO) -#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x) +#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, (x)) #define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7) #define USB_TD_DTD_TOKEN_STATUS_ACTIVE \ @@ -97,7 +97,7 @@ typedef struct { #define USB_QH_CAPABILITIES_MPL_SHIFT (16) #define USB_QH_CAPABILITIES_MPL_WIDTH (11) #define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) -#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, x) +#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, (x)) #define USB_QH_CAPABILITIES_ZLT_SHIFT (29) #define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT) @@ -105,7 +105,7 @@ typedef struct { #define USB_QH_CAPABILITIES_MULT_SHIFT (30) #define USB_QH_CAPABILITIES_MULT_WIDTH (2) #define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT) -#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, x) +#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, (x)) /* --- USB0 registers ------------------------------------------------------ */ @@ -218,7 +218,7 @@ typedef struct { /* Endpoint control */ #define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \ - (logical_ep * 4)) + ((logical_ep) * 4)) /* Endpoint control 0 */ #define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h index 53b0ef54..62db1f36 100644 --- a/include/libopencm3/stm32/can.h +++ b/include/libopencm3/stm32/can.h @@ -54,23 +54,23 @@ LGPL License Terms @ref lgpl_license /* --- CAN registers ------------------------------------------------------- */ /* CAN master control register (CAN_MCR) */ -#define CAN_MCR(can_base) MMIO32(can_base + 0x000) +#define CAN_MCR(can_base) MMIO32((can_base) + 0x000) /* CAN master status register (CAN_MSR) */ -#define CAN_MSR(can_base) MMIO32(can_base + 0x004) +#define CAN_MSR(can_base) MMIO32((can_base) + 0x004) /* CAN transmit status register (CAN_TSR) */ -#define CAN_TSR(can_base) MMIO32(can_base + 0x008) +#define CAN_TSR(can_base) MMIO32((can_base) + 0x008) /* CAN receive FIFO 0 register (CAN_RF0R) */ -#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) +#define CAN_RF0R(can_base) MMIO32((can_base) + 0x00C) /* CAN receive FIFO 1 register (CAN_RF1R) */ -#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) +#define CAN_RF1R(can_base) MMIO32((can_base) + 0x010) /* CAN interrupt enable register (CAN_IER) */ -#define CAN_IER(can_base) MMIO32(can_base + 0x014) +#define CAN_IER(can_base) MMIO32((can_base) + 0x014) /* CAN error status register (CAN_ESR) */ -#define CAN_ESR(can_base) MMIO32(can_base + 0x018) +#define CAN_ESR(can_base) MMIO32((can_base) + 0x018) /* CAN bit timing register (CAN_BTR) */ -#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) +#define CAN_BTR(can_base) MMIO32((can_base) + 0x01C) /* Registers in the offset range 0x020 to 0x17F are reserved. */ @@ -84,71 +84,71 @@ LGPL License Terms @ref lgpl_license #define CAN_FIFO1 0x1C0 /* CAN TX mailbox identifier register (CAN_TIxR) */ -#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) +#define CAN_TIxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x0) #define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) #define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) #define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) /* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ -#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) -#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) -#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) -#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) +#define CAN_TDTxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x4) +#define CAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0) +#define CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1) +#define CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2) /* CAN mailbox data low register (CAN_TDLxR) */ -#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) -#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) -#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) -#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) +#define CAN_TDLxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x8) +#define CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0) +#define CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1) +#define CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2) /* CAN mailbox data high register (CAN_TDHxR) */ -#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) -#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) -#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) -#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) +#define CAN_TDHxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0xC) +#define CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0) +#define CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1) +#define CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2) /* CAN RX FIFO identifier register (CAN_RIxR) */ -#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) -#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) -#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) +#define CAN_RIxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x0) +#define CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0) +#define CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1) /* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ -#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) -#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) -#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) +#define CAN_RDTxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x4) +#define CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0) +#define CAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1) /* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ -#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) -#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) -#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) +#define CAN_RDLxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x8) +#define CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0) +#define CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1) /* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ -#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) -#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) -#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) +#define CAN_RDHxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0xC) +#define CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0) +#define CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1) /* --- CAN filter registers ------------------------------------------------ */ /* CAN filter master register (CAN_FMR) */ -#define CAN_FMR(can_base) MMIO32(can_base + 0x200) +#define CAN_FMR(can_base) MMIO32((can_base) + 0x200) /* CAN filter mode register (CAN_FM1R) */ -#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) +#define CAN_FM1R(can_base) MMIO32((can_base) + 0x204) /* Register offset 0x208 is reserved. */ /* CAN filter scale register (CAN_FS1R) */ -#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) +#define CAN_FS1R(can_base) MMIO32((can_base) + 0x20C) /* Register offset 0x210 is reserved. */ /* CAN filter FIFO assignement register (CAN_FFA1R) */ -#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) +#define CAN_FFA1R(can_base) MMIO32((can_base) + 0x214) /* Register offset 0x218 is reserved. */ /* CAN filter activation register (CAN_FA1R) */ -#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) +#define CAN_FA1R(can_base) MMIO32((can_base) + 0x21C) /* Register offset 0x220 is reserved. */ @@ -159,10 +159,10 @@ LGPL License Terms @ref lgpl_license * Connectivity line devices have 28 banks so the bank ID spans 0..27 * all other devices have 14 banks so the bank ID spans 0..13. */ -#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \ - (bank * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \ - (bank * 0x8) + 0x4) +#define CAN_FiR1(can_base, bank) MMIO32((can_base) + 0x240 + \ + ((bank) * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32((can_base) + 0x240 + \ + ((bank) * 0x8) + 0x4) /* --- CAN_MCR values ------------------------------------------------------ */ diff --git a/include/libopencm3/stm32/common/adc_common_v1.h b/include/libopencm3/stm32/common/adc_common_v1.h index 3ab2dfd8..c8773fe6 100644 --- a/include/libopencm3/stm32/common/adc_common_v1.h +++ b/include/libopencm3/stm32/common/adc_common_v1.h @@ -49,19 +49,19 @@ specific memorymap.h header before including this header file.*/ /* --- ADC registers ------------------------------------------------------- */ /* ADC status register (ADC_SR) */ -#define ADC_SR(block) MMIO32(block + 0x00) +#define ADC_SR(block) MMIO32((block) + 0x00) /* ADC control register 1 (ADC_CR1) */ -#define ADC_CR1(block) MMIO32(block + 0x04) +#define ADC_CR1(block) MMIO32((block) + 0x04) /* ADC control register 2 (ADC_CR2) */ -#define ADC_CR2(block) MMIO32(block + 0x08) +#define ADC_CR2(block) MMIO32((block) + 0x08) /* ADC sample time register 1 (ADC_SMPR1) */ -#define ADC_SMPR1(block) MMIO32(block + 0x0c) +#define ADC_SMPR1(block) MMIO32((block) + 0x0c) /* ADC sample time register 2 (ADC_SMPR2) */ -#define ADC_SMPR2(block) MMIO32(block + 0x10) +#define ADC_SMPR2(block) MMIO32((block) + 0x10) #define ADC1_SR ADC_SR(ADC1) #define ADC1_CR1 ADC_CR1(ADC1) diff --git a/include/libopencm3/stm32/common/dma_common_f24.h b/include/libopencm3/stm32/common/dma_common_f24.h index 922a8b3a..e32114b1 100644 --- a/include/libopencm3/stm32/common/dma_common_f24.h +++ b/include/libopencm3/stm32/common/dma_common_f24.h @@ -60,8 +60,8 @@ specific memorymap.h header before including this header file.*/ /**@}*/ #define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n))) -#define DMA1_STREAM(n) DMA_STREAM(DMA1, n) -#define DMA2_STREAM(n) DMA_STREAM(DMA2, n) +#define DMA1_STREAM(n) DMA_STREAM(DMA1, (n)) +#define DMA2_STREAM(n) DMA_STREAM(DMA2, (n)) #define DMA1_STREAM0 DMA1_STREAM(0) #define DMA1_STREAM1 DMA1_STREAM(1) @@ -84,31 +84,31 @@ specific memorymap.h header before including this header file.*/ /* --- DMA controller registers -------------------------------------------- */ /* DMA low interrupt status register (DMAx_LISR) */ -#define DMA_LISR(port) MMIO32(port + 0x00) +#define DMA_LISR(port) MMIO32((port) + 0x00) #define DMA1_LISR DMA_LISR(DMA1) #define DMA2_LISR DMA_LISR(DMA2) /* DMA high interrupt status register (DMAx_HISR) */ -#define DMA_HISR(port) MMIO32(port + 0x04) +#define DMA_HISR(port) MMIO32((port) + 0x04) #define DMA1_HISR DMA_HISR(DMA1) #define DMA2_HISR DMA_HISR(DMA2) /* DMA low interrupt flag clear register (DMAx_LIFCR) */ -#define DMA_LIFCR(port) MMIO32(port + 0x08) +#define DMA_LIFCR(port) MMIO32((port) + 0x08) #define DMA1_LIFCR DMA_LIFCR(DMA1) #define DMA2_LIFCR DMA_LIFCR(DMA2) /* DMA high interrupt flag clear register (DMAx_HIFCR) */ -#define DMA_HIFCR(port) MMIO32(port + 0x0C) +#define DMA_HIFCR(port) MMIO32((port) + 0x0C) #define DMA1_HIFCR DMA_HIFCR(DMA1) #define DMA2_HIFCR DMA_HIFCR(DMA2) /* --- DMA stream registers ------------------------------------------------ */ /* DMA Stream x configuration register (DMA_SxCR) */ -#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00) -#define DMA1_SCR(n) DMA_SCR(DMA1, n) -#define DMA2_SCR(n) DMA_SCR(DMA2, n) +#define DMA_SCR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x00) +#define DMA1_SCR(n) DMA_SCR(DMA1, (n)) +#define DMA2_SCR(n) DMA_SCR(DMA2, (n)) #define DMA1_S0CR DMA1_SCR(0) #define DMA1_S1CR DMA1_SCR(1) @@ -129,9 +129,9 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7CR DMA2_SCR(7) /* DMA Stream x number of data register (DMA_SxNDTR) */ -#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04) -#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n) -#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n) +#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x04) +#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, (n)) +#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, (n)) #define DMA1_S0NDTR DMA1_SNDTR(0) #define DMA1_S1NDTR DMA1_SNDTR(1) @@ -153,9 +153,9 @@ specific memorymap.h header before including this header file.*/ /* DMA Stream x peripheral address register (DMA_SxPAR) */ #define DMA_SPAR(port, n) (*(volatile void **)\ - (DMA_STREAM(port, n) + 0x08)) -#define DMA1_SPAR(n) DMA_SPAR(DMA1, n) -#define DMA2_SPAR(n) DMA_SPAR(DMA2, n) + (DMA_STREAM((port), (n)) + 0x08)) +#define DMA1_SPAR(n) DMA_SPAR(DMA1, (n)) +#define DMA2_SPAR(n) DMA_SPAR(DMA2, (n)) #define DMA1_S0PAR DMA1_SPAR(0) #define DMA1_S1PAR DMA1_SPAR(1) @@ -177,9 +177,9 @@ specific memorymap.h header before including this header file.*/ /* DMA Stream x memory address 0 register (DMA_SxM0AR) */ #define DMA_SM0AR(port, n) (*(volatile void **) \ - (DMA_STREAM(port, n) + 0x0c)) -#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) -#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) + (DMA_STREAM((port), (n)) + 0x0c)) +#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, (n)) +#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, (n)) #define DMA1_S0M0AR DMA1_SM0AR(0) #define DMA1_S1M0AR DMA1_SM0AR(1) @@ -201,9 +201,9 @@ specific memorymap.h header before including this header file.*/ /* DMA Stream x memory address 1 register (DMA_SxM1AR) */ #define DMA_SM1AR(port, n) (*(volatile void **)\ - (DMA_STREAM(port, n) + 0x10)) -#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) -#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) + (DMA_STREAM((port), (n)) + 0x10)) +#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, (n)) +#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, (n)) #define DMA1_S0M1AR DMA1_SM1AR(0) #define DMA1_S1M1AR DMA1_SM1AR(1) @@ -224,9 +224,9 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7M1AR DMA2_SM1AR(7) /* DMA Stream x FIFO control register (DMA_SxFCR) */ -#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14) -#define DMA1_SFCR(n) DMA_SFCR(DMA1, n) -#define DMA2_SFCR(n) DMA_SFCR(DMA2, n) +#define DMA_SFCR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x14) +#define DMA1_SFCR(n) DMA_SFCR(DMA1, (n)) +#define DMA2_SFCR(n) DMA_SFCR(DMA2, (n)) #define DMA1_S0FCR DMA1_SFCR(0) #define DMA1_S1FCR DMA1_SFCR(1) @@ -269,7 +269,7 @@ being at the same relative location */ /* Offset within interrupt status register to start of stream interrupt flag * field */ -#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) +#define DMA_ISR_OFFSET(stream) (6*((stream) & 0x01)+16*(((stream) & 0x02) >> 1)) #define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ DMA_FEIF) #define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) @@ -501,7 +501,7 @@ being at the same relative location */ /**@}*/ #define DMA_SxCR_CHSEL_SHIFT 25 #define DMA_SxCR_CHSEL_MASK (7 << 25) -#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL(n) ((n) << DMA_SxCR_CHSEL_SHIFT) /* Reserved [31:28] */ diff --git a/include/libopencm3/stm32/common/dma_common_l1f013.h b/include/libopencm3/stm32/common/dma_common_l1f013.h index cb781a4c..a00834ab 100644 --- a/include/libopencm3/stm32/common/dma_common_l1f013.h +++ b/include/libopencm3/stm32/common/dma_common_l1f013.h @@ -48,17 +48,17 @@ specific memorymap.h header before including this header file.*/ /* --- DMA registers ------------------------------------------------------- */ /* DMA interrupt status register (DMAx_ISR) */ -#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA_ISR(dma_base) MMIO32((dma_base) + 0x00) #define DMA1_ISR DMA_ISR(DMA1) #define DMA2_ISR DMA_ISR(DMA2) /* DMA interrupt flag clear register (DMAx_IFCR) */ -#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA_IFCR(dma_base) MMIO32((dma_base) + 0x04) #define DMA1_IFCR DMA_IFCR(DMA1) #define DMA2_IFCR DMA_IFCR(DMA2) /* DMA channel configuration register (DMAx_CCRy) */ -#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ +#define DMA_CCR(dma_base, channel) MMIO32((dma_base) + 0x08 + \ (0x14 * ((channel) - 1))) #define DMA1_CCR(channel) DMA_CCR(DMA1, channel) @@ -78,7 +78,7 @@ specific memorymap.h header before including this header file.*/ #define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) /* DMA number of data register (DMAx_CNDTRy) */ -#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ +#define DMA_CNDTR(dma_base, channel) MMIO32((dma_base) + 0x0C + \ (0x14 * ((channel) - 1))) #define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) @@ -98,7 +98,7 @@ specific memorymap.h header before including this header file.*/ #define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) /* DMA peripheral address register (DMAx_CPARy) */ -#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ +#define DMA_CPAR(dma_base, channel) MMIO32((dma_base) + 0x10 + \ (0x14 * ((channel) - 1))) #define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) @@ -119,7 +119,7 @@ specific memorymap.h header before including this header file.*/ /* DMA memory address register (DMAx_CMARy) */ -#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ +#define DMA_CMAR(dma_base, channel) MMIO32((dma_base) + 0x14 + \ (0x14 * ((channel) - 1))) #define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) @@ -162,7 +162,7 @@ group. /* Offset within interrupt status register to start of channel interrupt flag * field */ -#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAG_OFFSET(channel) (4*((channel) - 1)) #define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ DMA_GIF) #define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) diff --git a/include/libopencm3/stm32/common/gpio_common_f234.h b/include/libopencm3/stm32/common/gpio_common_f234.h index e574a1b9..5fb03ae8 100644 --- a/include/libopencm3/stm32/common/gpio_common_f234.h +++ b/include/libopencm3/stm32/common/gpio_common_f234.h @@ -57,7 +57,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* Port mode register (GPIOx_MODER) */ -#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIO_MODER(port) MMIO32((port) + 0x00) #define GPIOA_MODER GPIO_MODER(GPIOA) #define GPIOB_MODER GPIO_MODER(GPIOB) #define GPIOC_MODER GPIO_MODER(GPIOC) @@ -66,7 +66,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_MODER GPIO_MODER(GPIOF) /* Port output type register (GPIOx_OTYPER) */ -#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIO_OTYPER(port) MMIO32((port) + 0x04) #define GPIOA_OTYPER GPIO_OTYPER(GPIOA) #define GPIOB_OTYPER GPIO_OTYPER(GPIOB) #define GPIOC_OTYPER GPIO_OTYPER(GPIOC) @@ -75,7 +75,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_OTYPER GPIO_OTYPER(GPIOF) /* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08) #define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) #define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) #define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) @@ -84,7 +84,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIO_PUPDR(port) MMIO32((port) + 0x0c) #define GPIOA_PUPDR GPIO_PUPDR(GPIOA) #define GPIOB_PUPDR GPIO_PUPDR(GPIOB) #define GPIOC_PUPDR GPIO_PUPDR(GPIOC) @@ -93,7 +93,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_PUPDR GPIO_PUPDR(GPIOF) /* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIO_IDR(port) MMIO32((port) + 0x10) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) @@ -102,7 +102,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_IDR GPIO_IDR(GPIOF) /* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIO_ODR(port) MMIO32((port) + 0x14) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) @@ -111,7 +111,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_ODR GPIO_ODR(GPIOF) /* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIO_BSRR(port) MMIO32((port) + 0x18) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) @@ -120,7 +120,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_BSRR GPIO_BSRR(GPIOF) /* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x1c) +#define GPIO_LCKR(port) MMIO32((port) + 0x1c) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) @@ -129,7 +129,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_LCKR GPIO_LCKR(GPIOF) /* Alternate function low register (GPIOx_AFRL) */ -#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIO_AFRL(port) MMIO32((port) + 0x20) #define GPIOA_AFRL GPIO_AFRL(GPIOA) #define GPIOB_AFRL GPIO_AFRL(GPIOB) #define GPIOC_AFRL GPIO_AFRL(GPIOC) @@ -138,7 +138,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_AFRL GPIO_AFRL(GPIOF) /* Alternate function high register (GPIOx_AFRH) */ -#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIO_AFRH(port) MMIO32((port) + 0x24) #define GPIOA_AFRH GPIO_AFRH(GPIOA) #define GPIOB_AFRH GPIO_AFRH(GPIOB) #define GPIOC_AFRH GPIO_AFRH(GPIOC) @@ -148,7 +148,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIOx_MODER values -------------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE(n, mode) ((mode) << (2 * (n))) #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode @ingroup gpio_defines @@ -172,7 +172,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIOx_OSPEEDR values ------------------------------------------------ */ -#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED(n, speed) ((speed) << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @@ -185,7 +185,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIOx_PUPDR values -------------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD(n, pupd) ((pupd) << (2 * (n))) #define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_pup GPIO Output Pin Pullup @ingroup gpio_defines @@ -218,7 +218,7 @@ specific memorymap.h header before including this header file.*/ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See datasheet table 6 (pg. 48) for alternate function mappings. */ -#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR(n, af) ((af) << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) /** @defgroup gpio_af_num Alternate Function Pin Selection @ingroup gpio_defines diff --git a/include/libopencm3/stm32/common/rtc_common_l1f024.h b/include/libopencm3/stm32/common/rtc_common_l1f024.h index 677caf0b..154652e3 100644 --- a/include/libopencm3/stm32/common/rtc_common_l1f024.h +++ b/include/libopencm3/stm32/common/rtc_common_l1f024.h @@ -95,7 +95,7 @@ specific memorymap.h header before including this header file.*/ /* RTC backup registers (RTC_BKPxR) */ #define RTC_BKP_BASE (RTC_BASE + 0x50) -#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg)) +#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4 * (reg))) /* RTC time register (RTC_TR) ----------------------------------- */ diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h index 949fec1d..4e75669a 100644 --- a/include/libopencm3/stm32/common/spi_common_all.h +++ b/include/libopencm3/stm32/common/spi_common_all.h @@ -55,58 +55,58 @@ specific memorymap.h header before including this header file.*/ /* Control register 1 (SPIx_CR1) */ /* Note: Not used in I2S mode. */ -#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI_CR1(spi_base) MMIO32((spi_base) + 0x00) #define SPI1_CR1 SPI_CR1(SPI1_BASE) #define SPI2_CR1 SPI_CR1(SPI2_BASE) #define SPI3_CR1 SPI_CR1(SPI3_BASE) /* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI_CR2(spi_base) MMIO32((spi_base) + 0x04) #define SPI1_CR2 SPI_CR2(SPI1_BASE) #define SPI2_CR2 SPI_CR2(SPI2_BASE) #define SPI3_CR2 SPI_CR2(SPI3_BASE) /* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI_SR(spi_base) MMIO32((spi_base) + 0x08) #define SPI1_SR SPI_SR(SPI1_BASE) #define SPI2_SR SPI_SR(SPI2_BASE) #define SPI3_SR SPI_SR(SPI3_BASE) /* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI_DR(spi_base) MMIO32((spi_base) + 0x0c) #define SPI1_DR SPI_DR(SPI1_BASE) #define SPI2_DR SPI_DR(SPI2_BASE) #define SPI3_DR SPI_DR(SPI3_BASE) /* CRC polynomial register (SPIx_CRCPR) */ /* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10) #define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) #define SPI2_CRCPR SPI_CRCPR(SPI2_BASE) #define SPI3_CRCPR SPI_CRCPR(SPI3_BASE) /* RX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14) #define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) #define SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE) #define SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE) /* TX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18) #define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) #define SPI2_TXCRCR SPI_TXCRCR(SPI2_BASE) #define SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE) /* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c) #define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) #define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE) #define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE) /* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20) #define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) #define SPI2_I2SPR SPI_I2SPR(SPI2_BASE) #define SPI3_I2SPR SPI_I2SPR(SPI3_BASE) diff --git a/include/libopencm3/stm32/common/spi_common_f03.h b/include/libopencm3/stm32/common/spi_common_f03.h index f9de9d4f..ac0f27d7 100644 --- a/include/libopencm3/stm32/common/spi_common_f03.h +++ b/include/libopencm3/stm32/common/spi_common_f03.h @@ -37,7 +37,7 @@ * applicable to the STM32F0/F3 series of devices */ -#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) +#define SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c) #define SPI1_DR8 SPI_DR8(SPI1_BASE) #define SPI2_DR8 SPI_DR8(SPI2_BASE) #define SPI3_DR8 SPI_DR8(SPI3_BASE) diff --git a/include/libopencm3/stm32/common/timer_common_all.h b/include/libopencm3/stm32/common/timer_common_all.h index 4e5ee62c..e315afab 100644 --- a/include/libopencm3/stm32/common/timer_common_all.h +++ b/include/libopencm3/stm32/common/timer_common_all.h @@ -86,7 +86,7 @@ specific memorymap.h header before including this header file.*/ /* --- Timer registers ----------------------------------------------------- */ /* Control register 1 (TIMx_CR1) */ -#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM_CR1(tim_base) MMIO32((tim_base) + 0x00) #define TIM1_CR1 TIM_CR1(TIM1) #define TIM2_CR1 TIM_CR1(TIM2) #define TIM3_CR1 TIM_CR1(TIM3) @@ -106,7 +106,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CR1 TIM_CR1(TIM17) /* Control register 2 (TIMx_CR2) */ -#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM_CR2(tim_base) MMIO32((tim_base) + 0x04) #define TIM1_CR2 TIM_CR2(TIM1) #define TIM2_CR2 TIM_CR2(TIM2) #define TIM3_CR2 TIM_CR2(TIM3) @@ -120,7 +120,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CR2 TIM_CR2(TIM17) /* Slave mode control register (TIMx_SMCR) */ -#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM_SMCR(tim_base) MMIO32((tim_base) + 0x08) #define TIM1_SMCR TIM_SMCR(TIM1) #define TIM2_SMCR TIM_SMCR(TIM2) #define TIM3_SMCR TIM_SMCR(TIM3) @@ -132,7 +132,7 @@ specific memorymap.h header before including this header file.*/ #define TIM15_SMCR TIM_SMCR(TIM15) /* DMA/Interrupt enable register (TIMx_DIER) */ -#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C) #define TIM1_DIER TIM_DIER(TIM1) #define TIM2_DIER TIM_DIER(TIM2) #define TIM3_DIER TIM_DIER(TIM3) @@ -152,7 +152,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_DIER TIM_DIER(TIM17) /* Status register (TIMx_SR) */ -#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM_SR(tim_base) MMIO32((tim_base) + 0x10) #define TIM1_SR TIM_SR(TIM1) #define TIM2_SR TIM_SR(TIM2) #define TIM3_SR TIM_SR(TIM3) @@ -172,7 +172,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_SR TIM_SR(TIM17) /* Event generation register (TIMx_EGR) */ -#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM_EGR(tim_base) MMIO32((tim_base) + 0x14) #define TIM1_EGR TIM_EGR(TIM1) #define TIM2_EGR TIM_EGR(TIM2) #define TIM3_EGR TIM_EGR(TIM3) @@ -192,7 +192,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_EGR TIM_EGR(TIM17) /* Capture/compare mode register 1 (TIMx_CCMR1) */ -#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18) #define TIM1_CCMR1 TIM_CCMR1(TIM1) #define TIM2_CCMR1 TIM_CCMR1(TIM2) #define TIM3_CCMR1 TIM_CCMR1(TIM3) @@ -210,7 +210,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CCMR1 TIM_CCMR1(TIM17) /* Capture/compare mode register 2 (TIMx_CCMR2) */ -#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C) #define TIM1_CCMR2 TIM_CCMR2(TIM1) #define TIM2_CCMR2 TIM_CCMR2(TIM2) #define TIM3_CCMR2 TIM_CCMR2(TIM3) @@ -219,7 +219,7 @@ specific memorymap.h header before including this header file.*/ #define TIM8_CCMR2 TIM_CCMR2(TIM8) /* Capture/compare enable register (TIMx_CCER) */ -#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM_CCER(tim_base) MMIO32((tim_base) + 0x20) #define TIM1_CCER TIM_CCER(TIM1) #define TIM2_CCER TIM_CCER(TIM2) #define TIM3_CCER TIM_CCER(TIM3) @@ -237,7 +237,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CCER TIM_CCER(TIM17) /* Counter (TIMx_CNT) */ -#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM_CNT(tim_base) MMIO32((tim_base) + 0x24) #define TIM1_CNT TIM_CNT(TIM1) #define TIM2_CNT TIM_CNT(TIM2) #define TIM3_CNT TIM_CNT(TIM3) @@ -257,7 +257,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CNT TIM_CNT(TIM17) /* Prescaler (TIMx_PSC) */ -#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM_PSC(tim_base) MMIO32((tim_base) + 0x28) #define TIM1_PSC TIM_PSC(TIM1) #define TIM2_PSC TIM_PSC(TIM2) #define TIM3_PSC TIM_PSC(TIM3) @@ -277,7 +277,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_PSC TIM_PSC(TIM17) /* Auto-reload register (TIMx_ARR) */ -#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C) #define TIM1_ARR TIM_ARR(TIM1) #define TIM2_ARR TIM_ARR(TIM2) #define TIM3_ARR TIM_ARR(TIM3) @@ -297,7 +297,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_ARR TIM_ARR(TIM17) /* Repetition counter register (TIMx_RCR) */ -#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM_RCR(tim_base) MMIO32((tim_base) + 0x30) #define TIM1_RCR TIM_RCR(TIM1) #define TIM8_RCR TIM_RCR(TIM8) #define TIM15_RCR TIM_RCR(TIM15) @@ -305,7 +305,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_RCR TIM_RCR(TIM17) /* Capture/compare register 1 (TIMx_CCR1) */ -#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34) #define TIM1_CCR1 TIM_CCR1(TIM1) #define TIM2_CCR1 TIM_CCR1(TIM2) #define TIM3_CCR1 TIM_CCR1(TIM3) @@ -323,7 +323,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CCR1 TIM_CCR1(TIM17) /* Capture/compare register 2 (TIMx_CCR2) */ -#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38) #define TIM1_CCR2 TIM_CCR2(TIM1) #define TIM2_CCR2 TIM_CCR2(TIM2) #define TIM3_CCR2 TIM_CCR2(TIM3) @@ -335,7 +335,7 @@ specific memorymap.h header before including this header file.*/ #define TIM15_CCR2 TIM_CCR2(TIM15) /* Capture/compare register 3 (TIMx_CCR3) */ -#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C) #define TIM1_CCR3 TIM_CCR3(TIM1) #define TIM2_CCR3 TIM_CCR3(TIM2) #define TIM3_CCR3 TIM_CCR3(TIM3) @@ -344,7 +344,7 @@ specific memorymap.h header before including this header file.*/ #define TIM8_CCR3 TIM_CCR3(TIM8) /* Capture/compare register 4 (TIMx_CCR4) */ -#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40) #define TIM1_CCR4 TIM_CCR4(TIM1) #define TIM2_CCR4 TIM_CCR4(TIM2) #define TIM3_CCR4 TIM_CCR4(TIM3) @@ -353,7 +353,7 @@ specific memorymap.h header before including this header file.*/ #define TIM8_CCR4 TIM_CCR4(TIM8) /* Break and dead-time register (TIMx_BDTR) */ -#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44) #define TIM1_BDTR TIM_BDTR(TIM1) #define TIM8_BDTR TIM_BDTR(TIM8) #define TIM15_BDTR TIM_BDTR(TIM15) @@ -361,7 +361,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_BDTR TIM_BDTR(TIM17) /* DMA control register (TIMx_DCR) */ -#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM_DCR(tim_base) MMIO32((tim_base) + 0x48) #define TIM1_DCR TIM_DCR(TIM1) #define TIM2_DCR TIM_DCR(TIM2) #define TIM3_DCR TIM_DCR(TIM3) @@ -373,7 +373,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_DCR TIM_DCR(TIM17) /* DMA address for full transfer (TIMx_DMAR) */ -#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C) #define TIM1_DMAR TIM_DMAR(TIM1) #define TIM2_DMAR TIM_DMAR(TIM2) #define TIM3_DMAR TIM_DMAR(TIM3) diff --git a/include/libopencm3/stm32/common/timer_common_f24.h b/include/libopencm3/stm32/common/timer_common_f24.h index 67ba593c..6f483d86 100644 --- a/include/libopencm3/stm32/common/timer_common_f24.h +++ b/include/libopencm3/stm32/common/timer_common_f24.h @@ -41,7 +41,7 @@ specific memorymap.h header before including this header file.*/ */ /* Timer 2/5 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM5_OR TIM_OR(TIM5) diff --git a/include/libopencm3/stm32/common/usart_common_f124.h b/include/libopencm3/stm32/common/usart_common_f124.h index 0bb85148..cd6f56ff 100644 --- a/include/libopencm3/stm32/common/usart_common_f124.h +++ b/include/libopencm3/stm32/common/usart_common_f124.h @@ -40,7 +40,7 @@ specific memorymap.h header before including this header file.*/ /* --- USART registers ----------------------------------------------------- */ /* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART_SR(usart_base) MMIO32((usart_base) + 0x00) #define USART1_SR USART_SR(USART1_BASE) #define USART2_SR USART_SR(USART2_BASE) #define USART3_SR USART_SR(USART3_BASE) @@ -48,7 +48,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_SR USART_SR(UART5_BASE) /* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART_DR(usart_base) MMIO32((usart_base) + 0x04) #define USART1_DR USART_DR(USART1_BASE) #define USART2_DR USART_DR(USART2_BASE) #define USART3_DR USART_DR(USART3_BASE) @@ -56,7 +56,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_DR USART_DR(UART5_BASE) /* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART_BRR(usart_base) MMIO32((usart_base) + 0x08) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) @@ -64,7 +64,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_BRR USART_BRR(UART5_BASE) /* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART_CR1(usart_base) MMIO32((usart_base) + 0x0c) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) @@ -72,7 +72,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_CR1 USART_CR1(UART5_BASE) /* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART_CR2(usart_base) MMIO32((usart_base) + 0x10) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) @@ -80,7 +80,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_CR2 USART_CR2(UART5_BASE) /* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART_CR3(usart_base) MMIO32((usart_base) + 0x14) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) @@ -88,7 +88,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_CR3 USART_CR3(UART5_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x18) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) diff --git a/include/libopencm3/stm32/f0/gpio.h b/include/libopencm3/stm32/f0/gpio.h index 85633c57..a5a22364 100644 --- a/include/libopencm3/stm32/f0/gpio.h +++ b/include/libopencm3/stm32/f0/gpio.h @@ -41,7 +41,7 @@ /* Register definitions */ /*****************************************************************************/ -#define GPIO_BRR(port) MMIO32(port + 0x28) +#define GPIO_BRR(port) MMIO32((port) + 0x28) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) diff --git a/include/libopencm3/stm32/f0/usart.h b/include/libopencm3/stm32/f0/usart.h index 8dba6833..a8d38985 100644 --- a/include/libopencm3/stm32/f0/usart.h +++ b/include/libopencm3/stm32/f0/usart.h @@ -44,67 +44,67 @@ /* Register definitions */ /*****************************************************************************/ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) #define USART4_CR1 USART_CR1(USART4_BASE) -#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) #define USART4_CR2 USART_CR2(USART4_BASE) -#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) #define USART4_CR3 USART_CR3(USART4_BASE) -#define USART_BRR(usart_base) MMIO32(usart_base + 0x0c) +#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0c) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) #define USART4_BRR USART_BRR(USART4_BASE) -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) #define USART4_GTPR USART_GTPR(USART4_BASE) -#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14) #define USART1_RTOR USART_RTOR(USART1_BASE) #define USART2_RTOR USART_RTOR(USART2_BASE) #define USART3_RTOR USART_RTOR(USART3_BASE) #define USART4_RTOR USART_RTOR(USART4_BASE) -#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18) #define USART1_RQR USART_RQR(USART1_BASE) #define USART2_RQR USART_RQR(USART2_BASE) #define USART3_RQR USART_RQR(USART3_BASE) #define USART4_RQR USART_RQR(USART4_BASE) -#define USART_ISR(usart_base) MMIO32(usart_base + 0x1c) +#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1c) #define USART1_ISR USART_ISR(USART1_BASE) #define USART2_ISR USART_ISR(USART2_BASE) #define USART3_ISR USART_ISR(USART3_BASE) #define USART4_ISR USART_ISR(USART4_BASE) -#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20) #define USART1_ICR USART_ICR(USART1_BASE) #define USART2_ICR USART_ICR(USART2_BASE) #define USART3_ICR USART_ICR(USART3_BASE) #define USART4_ICR USART_ICR(USART4_BASE) -#define USART_RDR(usart_base) MMIO8(usart_base + 0x24) +#define USART_RDR(usart_base) MMIO8((usart_base) + 0x24) #define USART1_RDR USART_RDR(USART1_BASE) #define USART2_RDR USART_RDR(USART2_BASE) #define USART3_RDR USART_RDR(USART3_BASE) #define USART4_RDR USART_RDR(USART4_BASE) -#define USART_TDR(usart_base) MMIO8(usart_base + 0x28) +#define USART_TDR(usart_base) MMIO8((usart_base) + 0x28) #define USART1_TDR USART_TDR(USART1_BASE) #define USART2_TDR USART_TDR(USART2_BASE) #define USART3_TDR USART_TDR(USART3_BASE) diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index ec7cabc0..d52a02c1 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -43,37 +43,37 @@ LGPL License Terms @ref lgpl_license /* --- Convenience macros -------------------------------------------------- */ /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x14) -#define ADC_JOFR2(block) MMIO32(block + 0x18) -#define ADC_JOFR3(block) MMIO32(block + 0x1c) -#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC_JOFR1(block) MMIO32((block) + 0x14) +#define ADC_JOFR2(block) MMIO32((block) + 0x18) +#define ADC_JOFR3(block) MMIO32((block) + 0x1c) +#define ADC_JOFR4(block) MMIO32((block) + 0x20) /* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC_HTR(block) MMIO32((block) + 0x24) /* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC_LTR(block) MMIO32((block) + 0x28) /* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC_SQR1(block) MMIO32((block) + 0x2c) /* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC_SQR2(block) MMIO32((block) + 0x30) /* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC_SQR3(block) MMIO32((block) + 0x34) /* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC_JSQR(block) MMIO32((block) + 0x38) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x3c) -#define ADC_JDR2(block) MMIO32(block + 0x40) -#define ADC_JDR3(block) MMIO32(block + 0x44) -#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC_JDR1(block) MMIO32((block) + 0x3c) +#define ADC_JDR2(block) MMIO32((block) + 0x40) +#define ADC_JDR3(block) MMIO32((block) + 0x44) +#define ADC_JDR4(block) MMIO32((block) + 0x48) /* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC_DR(block) MMIO32((block) + 0x4c) /* --- ADC Channels ------------------------------------------------------- */ #define ADC_CHANNEL_TEMP ADC_CHANNEL16 diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h index d520b216..2de19ce9 100644 --- a/include/libopencm3/stm32/f1/gpio.h +++ b/include/libopencm3/stm32/f1/gpio.h @@ -523,7 +523,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ /* Port configuration register low (GPIOx_CRL) */ -#define GPIO_CRL(port) MMIO32(port + 0x00) +#define GPIO_CRL(port) MMIO32((port) + 0x00) #define GPIOA_CRL GPIO_CRL(GPIOA) #define GPIOB_CRL GPIO_CRL(GPIOB) #define GPIOC_CRL GPIO_CRL(GPIOC) @@ -533,7 +533,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_CRL GPIO_CRL(GPIOG) /* Port configuration register low (GPIOx_CRH) */ -#define GPIO_CRH(port) MMIO32(port + 0x04) +#define GPIO_CRH(port) MMIO32((port) + 0x04) #define GPIOA_CRH GPIO_CRH(GPIOA) #define GPIOB_CRH GPIO_CRH(GPIOB) #define GPIOC_CRH GPIO_CRH(GPIOC) @@ -543,7 +543,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_CRH GPIO_CRH(GPIOG) /* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x08) +#define GPIO_IDR(port) MMIO32((port) + 0x08) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) @@ -553,7 +553,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_IDR GPIO_IDR(GPIOG) /* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x0c) +#define GPIO_ODR(port) MMIO32((port) + 0x0c) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) @@ -563,7 +563,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_ODR GPIO_ODR(GPIOG) /* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x10) +#define GPIO_BSRR(port) MMIO32((port) + 0x10) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) @@ -573,7 +573,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_BSRR GPIO_BSRR(GPIOG) /* Port bit reset register (GPIOx_BRR) */ -#define GPIO_BRR(port) MMIO16(port + 0x14) +#define GPIO_BRR(port) MMIO16((port) + 0x14) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) @@ -583,7 +583,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_BRR GPIO_BRR(GPIOG) /* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x18) +#define GPIO_LCKR(port) MMIO32((port) + 0x18) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index 56c97480..beb4bc4e 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -45,7 +45,7 @@ /*----------- ADC registers -------------------------------------- */ /* ADC interrupt and status register (ADCx_ISR, x=1..4) */ -#define ADC_ISR(adc_base) MMIO32(adc_base + 0x00) +#define ADC_ISR(adc_base) MMIO32((adc_base) + 0x00) #define ADC1_ISR ADC_ISR(ADC1_BASE) #define ADC2_ISR ADC_ISR(ADC2_BASE) #define ADC3_ISR ADC_ISR(ADC3_BASE) @@ -53,7 +53,7 @@ /* Interrupt Enable Register (ADCx_IER, x=1..4) IER */ -#define ADC_IER(adc_base) MMIO32(adc_base + 0x04) +#define ADC_IER(adc_base) MMIO32((adc_base) + 0x04) #define ADC1_IER ADC_IER(ADC1_BASE) #define ADC2_IER ADC_IER(ADC2_BASE) #define ADC3_IER ADC_IER(ADC3_BASE) @@ -61,7 +61,7 @@ /* Control Register (ADCx_CR, x=1..4) CR */ -#define ADC_CR(adc_base) MMIO32(adc_base + 0x08) +#define ADC_CR(adc_base) MMIO32((adc_base) + 0x08) #define ADC1_CR ADC_CR(ADC1_BASE) #define ADC2_CR ADC_CR(ADC2_BASE) #define ADC3_CR ADC_CR(ADC3_BASE) @@ -69,7 +69,7 @@ /* Configuration Register (ADCx_CFGR, x=1..4) CFGR */ -#define ADC_CFGR(adc_base) MMIO32(adc_base + 0x0C) +#define ADC_CFGR(adc_base) MMIO32((adc_base) + 0x0C) #define ADC1_CFGR ADC_CFGR(ADC1_BASE) #define ADC2_CFGR ADC_CFGR(ADC2_BASE) #define ADC3_CFGR ADC_CFGR(ADC3_BASE) @@ -77,7 +77,7 @@ /* Sample Time Register 1 (ADCx_SMPR1, x=1..4) SMPR1 */ -#define ADC_SMPR1(adc_base) MMIO32(adc_base + 0x14) +#define ADC_SMPR1(adc_base) MMIO32((adc_base) + 0x14) #define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) #define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) #define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) @@ -85,7 +85,7 @@ /* Sample Time Register 2 (ADCx_SMPR2, x=1..4) SMPR2 */ -#define ADC_SMPR2(adc_base) MMIO32(adc_base + 0x18) +#define ADC_SMPR2(adc_base) MMIO32((adc_base) + 0x18) #define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) #define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) #define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) @@ -93,7 +93,7 @@ /* Watchdog Threshold Register 1 (ADCx_TR1, x=1..4) TR1 */ -#define ADC_TR1(adc_base) MMIO32(adc_base + 0x20) +#define ADC_TR1(adc_base) MMIO32((adc_base) + 0x20) #define ADC1_TR1 ADC_TR1(ADC1_BASE) #define ADC2_TR1 ADC_TR1(ADC2_BASE) #define ADC3_TR1 ADC_TR1(ADC3_BASE) @@ -101,7 +101,7 @@ /* Watchdog Threshold Register 2 (ADCx_TR2, x=1..4) TR2 */ -#define ADC_TR2(adc_base) MMIO32(adc_base + 0x24) +#define ADC_TR2(adc_base) MMIO32((adc_base) + 0x24) #define ADC1_TR2 ADC_TR2(ADC1_BASE) #define ADC2_TR2 ADC_TR2(ADC2_BASE) #define ADC3_TR2 ADC_TR2(ADC3_BASE) @@ -109,7 +109,7 @@ /* Watchdog Threshold Register 3 (ADCx_TR3, x=1..4) TR3 */ -#define ADC_TR3(adc_base) MMIO32(adc_base + 0x28) +#define ADC_TR3(adc_base) MMIO32((adc_base) + 0x28) #define ADC1_TR3 ADC_TR3(ADC1_BASE) #define ADC2_TR3 ADC_TR3(ADC2_BASE) #define ADC3_TR3 ADC_TR3(ADC3_BASE) @@ -117,7 +117,7 @@ /* Regular Sequence Register 1 (ADCx_SQR1, x=1..4) SQR1 */ -#define ADC_SQR1(adc_base) MMIO32(adc_base + 0x30) +#define ADC_SQR1(adc_base) MMIO32((adc_base) + 0x30) #define ADC1_SQR1 ADC_SQR1(ADC1_BASE) #define ADC2_SQR1 ADC_SQR1(ADC2_BASE) #define ADC3_SQR1 ADC_SQR1(ADC3_BASE) @@ -125,7 +125,7 @@ /* Regular Sequence Register 2 (ADCx_SQR2, x=1..4) SQR2 */ -#define ADC_SQR2(adc_base) MMIO32(adc_base + 0x34) +#define ADC_SQR2(adc_base) MMIO32((adc_base) + 0x34) #define ADC1_SQR2 ADC_SQR2(ADC1_BASE) #define ADC2_SQR2 ADC_SQR2(ADC2_BASE) #define ADC3_SQR2 ADC_SQR2(ADC3_BASE) @@ -133,7 +133,7 @@ /* Regular Sequence Register 3 (ADCx_SQR3, x=1..4) SQR3 */ -#define ADC_SQR3(adc_base) MMIO32(adc_base + 0x38) +#define ADC_SQR3(adc_base) MMIO32((adc_base) + 0x38) #define ADC1_SQR3 ADC_SQR3(ADC1_BASE) #define ADC2_SQR3 ADC_SQR3(ADC2_BASE) #define ADC3_SQR3 ADC_SQR3(ADC3_BASE) @@ -141,7 +141,7 @@ /* Regular Sequence Register 4 (ADCx_SQR3, x=1..4) SQR4 */ -#define ADC_SQR4(adc_base) MMIO32(adc_base + 0x3C) +#define ADC_SQR4(adc_base) MMIO32((adc_base) + 0x3C) #define ADC1_SQR4 ADC_SQR4(ADC1_BASE) #define ADC2_SQR4 ADC_SQR4(ADC2_BASE) #define ADC3_SQR4 ADC_SQR4(ADC3_BASE) @@ -149,7 +149,7 @@ /* regular Data Register (ADCx_DR, x=1..4) DR */ -#define ADC_DR(adc_base) MMIO32(adc_base + 0x40) +#define ADC_DR(adc_base) MMIO32((adc_base) + 0x40) #define ADC1_DR ADC_DR(ADC1_BASE) #define ADC2_DR ADC_DR(ADC2_BASE) #define ADC3_DR ADC_DR(ADC3_BASE) @@ -157,7 +157,7 @@ /* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ -#define ADC_JSQR(adc_base) MMIO32(adc_base + 0x30) +#define ADC_JSQR(adc_base) MMIO32((adc_base) + 0x30) #define ADC1_JSQR ADC_JSQR(ADC1_BASE) #define ADC2_JSQR ADC_JSQR(ADC2_BASE) #define ADC3_JSQR ADC_JSQR(ADC3_BASE) @@ -165,25 +165,25 @@ /* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ -#define ADC_OFR1(adc_base) MMIO32(adc_base + 0x60) +#define ADC_OFR1(adc_base) MMIO32((adc_base) + 0x60) #define ADC1_OFR1 ADC_OFR1(ADC1_BASE) #define ADC2_OFR1 ADC_OFR1(ADC2_BASE) #define ADC3_OFR1 ADC_OFR1(ADC3_BASE) #define ADC4_OFR1 ADC_OFR1(ADC4_BASE) -#define ADC_OFR2(adc_base) MMIO32(adc_base + 0x64) +#define ADC_OFR2(adc_base) MMIO32((adc_base) + 0x64) #define ADC1_OFR2 ADC_OFR2(ADC1_BASE) #define ADC2_OFR2 ADC_OFR2(ADC2_BASE) #define ADC3_OFR2 ADC_OFR2(ADC3_BASE) #define ADC4_OFR2 ADC_OFR2(ADC4_BASE) -#define ADC_OFR3(adc_base) MMIO32(adc_base + 0x68) +#define ADC_OFR3(adc_base) MMIO32((adc_base) + 0x68) #define ADC1_OFR3 ADC_OFR3(ADC1_BASE) #define ADC2_OFR3 ADC_OFR3(ADC2_BASE) #define ADC3_OFR3 ADC_OFR3(ADC3_BASE) #define ADC4_OFR3 ADC_OFR3(ADC4_BASE) -#define ADC_OFR4(adc_base) MMIO32(adc_base + 0x6C) +#define ADC_OFR4(adc_base) MMIO32((adc_base) + 0x6C) #define ADC1_OFR4 ADC_OFR4(ADC1_BASE) #define ADC2_OFR4 ADC_OFR4(ADC2_BASE) #define ADC3_OFR4 ADC_OFR4(ADC3_BASE) @@ -191,25 +191,25 @@ /* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ -#define ADC_JDR1(adc_base) MMIO32(adc_base + 0x80) +#define ADC_JDR1(adc_base) MMIO32((adc_base) + 0x80) #define ADC1_JDR1 ADC_JDR1(ADC1_BASE) #define ADC2_JDR1 ADC_JDR1(ADC2_BASE) #define ADC3_JDR1 ADC_JDR1(ADC3_BASE) #define ADC4_JDR1 ADC_JDR1(ADC4_BASE) -#define ADC_JDR2(adc_base) MMIO32(adc_base + 0x84) +#define ADC_JDR2(adc_base) MMIO32((adc_base) + 0x84) #define ADC1_JDR2 ADC_JDR2(ADC1_BASE) #define ADC2_JDR2 ADC_JDR2(ADC2_BASE) #define ADC3_JDR2 ADC_JDR2(ADC3_BASE) #define ADC4_JDR2 ADC_JDR2(ADC4_BASE) -#define ADC_JDR3(adc_base) MMIO32(adc_base + 0x88) +#define ADC_JDR3(adc_base) MMIO32((adc_base) + 0x88) #define ADC1_JDR3 ADC_JDR3(ADC1_BASE) #define ADC2_JDR3 ADC_JDR3(ADC2_BASE) #define ADC3_JDR3 ADC_JDR3(ADC3_BASE) #define ADC4_JDR3 ADC_JDR3(ADC4_BASE) -#define ADC_JDR4(adc_base) MMIO32(adc_base + 0x8C) +#define ADC_JDR4(adc_base) MMIO32((adc_base) + 0x8C) #define ADC1_JDR4 ADC_JDR4(ADC1_BASE) #define ADC2_JDR4 ADC_JDR4(ADC2_BASE) #define ADC3_JDR4 ADC_JDR4(ADC3_BASE) @@ -217,7 +217,7 @@ /* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ -#define ADC_AWD2CR(adc_base) MMIO32(adc_base + 0xA0) +#define ADC_AWD2CR(adc_base) MMIO32((adc_base) + 0xA0) #define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) #define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) #define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) @@ -225,7 +225,7 @@ /* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ -#define ADC_AWD3CR(adc_base) MMIO32(adc_base + 0xA4) +#define ADC_AWD3CR(adc_base) MMIO32((adc_base) + 0xA4) #define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) #define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) #define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) @@ -233,7 +233,7 @@ /* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ -#define ADC_DIFSEL(adc_base) MMIO32(adc_base + 0xB0) +#define ADC_DIFSEL(adc_base) MMIO32((adc_base) + 0xB0) #define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) #define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) #define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) @@ -241,7 +241,7 @@ /* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ -#define ADC_CALFACT(adc_base) MMIO32(adc_base + 0xB4) +#define ADC_CALFACT(adc_base) MMIO32((adc_base) + 0xB4) #define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) #define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) #define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) diff --git a/include/libopencm3/stm32/f3/usart.h b/include/libopencm3/stm32/f3/usart.h index 86195634..e429ddc8 100644 --- a/include/libopencm3/stm32/f3/usart.h +++ b/include/libopencm3/stm32/f3/usart.h @@ -36,7 +36,7 @@ /* --- USART registers ----------------------------------------------------- */ /* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) @@ -44,7 +44,7 @@ #define UART5_CR1 USART_CR1(UART5_BASE) /* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) @@ -52,7 +52,7 @@ #define UART5_CR2 USART_CR2(UART5_BASE) /* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) @@ -60,7 +60,7 @@ #define UART5_CR3 USART_CR3(UART5_BASE) /* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x0C) +#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0C) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) @@ -68,7 +68,7 @@ #define UART5_BRR USART_BRR(UART5_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) @@ -76,7 +76,7 @@ #define UART5_GTPR USART_GTPR(UART5_BASE) /* Receiver timeout register (USART_RTOR) */ -#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14) #define USART1_RTOR USART_RTOR(USART1_BASE) #define USART2_RTOR USART_RTOR(USART2_BASE) #define USART3_RTOR USART_RTOR(USART3_BASE) @@ -84,7 +84,7 @@ #define UART5_RTOR USART_RTOR(UART5_BASE) /* Request register (USART_RQR) */ -#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18) #define USART1_RQR USART_RQR(USART1_BASE) #define USART2_RQR USART_RQR(USART2_BASE) #define USART3_RQR USART_RQR(USART3_BASE) @@ -92,7 +92,7 @@ #define UART5_RQR USART_RQR(UART5_BASE) /* Interrupt & status register (USART_ISR) */ -#define USART_ISR(usart_base) MMIO32(usart_base + 0x1C) +#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1C) #define USART1_ISR USART_ISR(USART1_BASE) #define USART2_ISR USART_ISR(USART2_BASE) #define USART3_ISR USART_ISR(USART3_BASE) @@ -100,7 +100,7 @@ #define UART5_ISR USART_ISR(UART5_BASE) /* Interrupt flag clear register (USART_ICR) */ -#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20) #define USART1_ICR USART_ICR(USART1_BASE) #define USART2_ICR USART_ICR(USART2_BASE) #define USART3_ICR USART_ICR(USART3_BASE) @@ -108,7 +108,7 @@ #define UART5_ICR USART_ICR(UART5_BASE) /* Receive data register (USART_RDR) */ -#define USART_RDR(usart_base) MMIO32(usart_base + 0x24) +#define USART_RDR(usart_base) MMIO32((usart_base) + 0x24) #define USART1_RDR USART_RDR(USART1_BASE) #define USART2_RDR USART_RDR(USART2_BASE) #define USART3_RDR USART_RDR(USART3_BASE) @@ -116,7 +116,7 @@ #define UART5_RDR USART_RDR(UART5_BASE) /* Transmit data register (USART_TDR) */ -#define USART_TDR(usart_base) MMIO32(usart_base + 0x28) +#define USART_TDR(usart_base) MMIO32((usart_base) + 0x28) #define USART1_TDR USART_TDR(USART1_BASE) #define USART2_TDR USART_TDR(USART2_BASE) #define USART3_TDR USART_TDR(USART3_BASE) diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h index 56188f40..07addb52 100644 --- a/include/libopencm3/stm32/f4/adc.h +++ b/include/libopencm3/stm32/f4/adc.h @@ -44,37 +44,37 @@ LGPL License Terms @ref lgpl_license /* --- Convenience macros -------------------------------------------------- */ /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x14) -#define ADC_JOFR2(block) MMIO32(block + 0x18) -#define ADC_JOFR3(block) MMIO32(block + 0x1c) -#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC_JOFR1(block) MMIO32((block) + 0x14) +#define ADC_JOFR2(block) MMIO32((block) + 0x18) +#define ADC_JOFR3(block) MMIO32((block) + 0x1c) +#define ADC_JOFR4(block) MMIO32((block) + 0x20) /* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC_HTR(block) MMIO32((block) + 0x24) /* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC_LTR(block) MMIO32((block) + 0x28) /* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC_SQR1(block) MMIO32((block) + 0x2c) /* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC_SQR2(block) MMIO32((block) + 0x30) /* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC_SQR3(block) MMIO32((block) + 0x34) /* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC_JSQR(block) MMIO32((block) + 0x38) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x3c) -#define ADC_JDR2(block) MMIO32(block + 0x40) -#define ADC_JDR3(block) MMIO32(block + 0x44) -#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC_JDR1(block) MMIO32((block) + 0x3c) +#define ADC_JDR2(block) MMIO32((block) + 0x40) +#define ADC_JDR3(block) MMIO32((block) + 0x44) +#define ADC_JDR4(block) MMIO32((block) + 0x48) /* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC_DR(block) MMIO32((block) + 0x4c) /* ADC common (shared) registers */ #define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) diff --git a/include/libopencm3/stm32/f4/fmc.h b/include/libopencm3/stm32/f4/fmc.h index 9367273c..8aa8c633 100644 --- a/include/libopencm3/stm32/f4/fmc.h +++ b/include/libopencm3/stm32/f4/fmc.h @@ -34,13 +34,13 @@ error "This file should not be included directly, it is included with fsmc.h" /* --- FMC registers ------------------------------------------------------ */ /* SDRAM Control Registers 1 .. 2 */ -#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * x) +#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x)) #define FMC_SDCR1 FMC_SDCR(0) #define FMC_SDCR2 FMC_SDCR(1) /* SDRAM Timing Registers 1 .. 2 */ -#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * x) +#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x)) #define FMC_SDTR1 FMC_SDTR(0) #define FMC_SDTR2 FMC_SDTR(1) diff --git a/include/libopencm3/stm32/f4/ltdc.h b/include/libopencm3/stm32/f4/ltdc.h index 6f5b3afe..adf54d01 100644 --- a/include/libopencm3/stm32/f4/ltdc.h +++ b/include/libopencm3/stm32/f4/ltdc.h @@ -45,51 +45,51 @@ #define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) /* x == LTDC_LAYER_x */ -#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * (x - 1))) +#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) #define LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) #define LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) -#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * (x - 1))) +#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) #define LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) #define LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) -#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * (x - 1))) +#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) #define LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) #define LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) -#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * (x - 1))) +#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) #define LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) #define LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) -#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * (x - 1))) +#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) #define LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) #define LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) -#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * (x - 1))) +#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) #define LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) #define LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) -#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * (x - 1))) +#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) #define LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) #define LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) -#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * (x - 1))) +#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) #define LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) #define LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) -#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * (x - 1))) +#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) #define LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) #define LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) -#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * (x - 1))) +#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) #define LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) #define LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) -#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * (x - 1))) +#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) #define LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) #define LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) -#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * (x - 1))) +#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) #define LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) #define LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h index 818251cb..2d8ed6a7 100644 --- a/include/libopencm3/stm32/fsmc.h +++ b/include/libopencm3/stm32/fsmc.h @@ -37,46 +37,46 @@ /* --- FSMC registers ------------------------------------------------------ */ /* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * (x)) #define FSMC_BCR1 FSMC_BCR(0) #define FSMC_BCR2 FSMC_BCR(1) #define FSMC_BCR3 FSMC_BCR(2) #define FSMC_BCR4 FSMC_BCR(3) /* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * (x)) #define FSMC_BTR1 FSMC_BTR(0) #define FSMC_BTR2 FSMC_BTR(1) #define FSMC_BTR3 FSMC_BTR(2) #define FSMC_BTR4 FSMC_BTR(3) /* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * (x)) #define FSMC_BWTR1 FSMC_BWTR(0) #define FSMC_BWTR2 FSMC_BWTR(1) #define FSMC_BWTR3 FSMC_BWTR(2) #define FSMC_BWTR4 FSMC_BWTR(3) /* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * (x)) #define FSMC_PCR2 FSMC_PCR(1) #define FSMC_PCR3 FSMC_PCR(2) #define FSMC_PCR4 FSMC_PCR(3) /* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * (x)) #define FSMC_SR2 FSMC_SR(1) #define FSMC_SR3 FSMC_SR(2) #define FSMC_SR4 FSMC_SR(3) /* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * (x)) #define FSMC_PMEM2 FSMC_PMEM(1) #define FSMC_PMEM3 FSMC_PMEM(2) #define FSMC_PMEM4 FSMC_PMEM(3) /* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * (x)) #define FSMC_PATT2 FSMC_PATT(1) #define FSMC_PATT3 FSMC_PATT(2) #define FSMC_PATT4 FSMC_PATT(3) @@ -85,7 +85,7 @@ #define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) /* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * (x)) #define FSMC_ECCR2 FSMC_ECCR(1) #define FSMC_ECCR3 FSMC_ECCR(2) diff --git a/include/libopencm3/stm32/l0/gpio.h b/include/libopencm3/stm32/l0/gpio.h index 4292ec81..a1b48990 100644 --- a/include/libopencm3/stm32/l0/gpio.h +++ b/include/libopencm3/stm32/l0/gpio.h @@ -41,7 +41,7 @@ /* Register definitions */ /*****************************************************************************/ -#define GPIO_BRR(port) MMIO32(port + 0x28) +#define GPIO_BRR(port) MMIO32((port) + 0x28) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) diff --git a/include/libopencm3/stm32/l1/adc.h b/include/libopencm3/stm32/l1/adc.h index cd56d15a..a5f4909c 100644 --- a/include/libopencm3/stm32/l1/adc.h +++ b/include/libopencm3/stm32/l1/adc.h @@ -40,52 +40,52 @@ LGPL License Terms @ref lgpl_license #define ADC_MAX_CHANNELS 32 /* ADC sample time register 3 (ADC_SMPR3) */ -#define ADC_SMPR3(block) MMIO32(block + 0x14) +#define ADC_SMPR3(block) MMIO32((block) + 0x14) #define ADC1_SMPR3 ADC_SMPR3(ADC1) /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x18) -#define ADC_JOFR2(block) MMIO32(block + 0x1c) -#define ADC_JOFR3(block) MMIO32(block + 0x20) -#define ADC_JOFR4(block) MMIO32(block + 0x24) +#define ADC_JOFR1(block) MMIO32((block) + 0x18) +#define ADC_JOFR2(block) MMIO32((block) + 0x1c) +#define ADC_JOFR3(block) MMIO32((block) + 0x20) +#define ADC_JOFR4(block) MMIO32((block) + 0x24) /* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x28) +#define ADC_HTR(block) MMIO32((block) + 0x28) /* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x2c) +#define ADC_LTR(block) MMIO32((block) + 0x2c) /* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x30) +#define ADC_SQR1(block) MMIO32((block) + 0x30) /* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x34) +#define ADC_SQR2(block) MMIO32((block) + 0x34) /* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x38) +#define ADC_SQR3(block) MMIO32((block) + 0x38) /* ADC regular sequence register 4 (ADC_SQR4) */ -#define ADC_SQR4(block) MMIO32(block + 0x3c) +#define ADC_SQR4(block) MMIO32((block) + 0x3c) #define ADC1_SQR4 ADC_SQR4(ADC1) /* ADC regular sequence register 5 (ADC_SQR5) */ -#define ADC_SQR5(block) MMIO32(block + 0x40) +#define ADC_SQR5(block) MMIO32((block) + 0x40) #define ADC1_SQR5 ADC_SQR5(ADC1) /* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x44) +#define ADC_JSQR(block) MMIO32((block) + 0x44) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x48) -#define ADC_JDR2(block) MMIO32(block + 0x4c) -#define ADC_JDR3(block) MMIO32(block + 0x50) -#define ADC_JDR4(block) MMIO32(block + 0x54) +#define ADC_JDR1(block) MMIO32((block) + 0x48) +#define ADC_JDR2(block) MMIO32((block) + 0x4c) +#define ADC_JDR3(block) MMIO32((block) + 0x50) +#define ADC_JDR4(block) MMIO32((block) + 0x54) /* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x58) +#define ADC_DR(block) MMIO32((block) + 0x58) /* ADC sample time register 0 (ADC_SMPR0) (high/med+ only) */ -#define ADC_SMPR0(block) MMIO32(block + 0x5c) +#define ADC_SMPR0(block) MMIO32((block) + 0x5c) #define ADC1_SMPR0 ADC_SMPR0(ADC1) #define ADC_CSR MMIO32(ADC1 + 0x300) diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h index f2c607ce..c2970e2a 100644 --- a/include/libopencm3/stm32/l1/gpio.h +++ b/include/libopencm3/stm32/l1/gpio.h @@ -57,7 +57,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ /* Port mode register (GPIOx_MODER) */ -#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIO_MODER(port) MMIO32((port) + 0x00) #define GPIOA_MODER GPIO_MODER(GPIOA) #define GPIOB_MODER GPIO_MODER(GPIOB) #define GPIOC_MODER GPIO_MODER(GPIOC) @@ -66,7 +66,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_MODER GPIO_MODER(GPIOH) /* Port output type register (GPIOx_OTYPER) */ -#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIO_OTYPER(port) MMIO32((port) + 0x04) #define GPIOA_OTYPER GPIO_OTYPER(GPIOA) #define GPIOB_OTYPER GPIO_OTYPER(GPIOB) #define GPIOC_OTYPER GPIO_OTYPER(GPIOC) @@ -75,7 +75,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_OTYPER GPIO_OTYPER(GPIOH) /* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08) #define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) #define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) #define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) @@ -84,7 +84,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIO_PUPDR(port) MMIO32((port) + 0x0c) #define GPIOA_PUPDR GPIO_PUPDR(GPIOA) #define GPIOB_PUPDR GPIO_PUPDR(GPIOB) #define GPIOC_PUPDR GPIO_PUPDR(GPIOC) @@ -93,7 +93,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_PUPDR GPIO_PUPDR(GPIOH) /* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIO_IDR(port) MMIO32((port) + 0x10) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) @@ -102,7 +102,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_IDR GPIO_IDR(GPIOH) /* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIO_ODR(port) MMIO32((port) + 0x14) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) @@ -111,7 +111,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_ODR GPIO_ODR(GPIOH) /* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIO_BSRR(port) MMIO32((port) + 0x18) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) @@ -120,7 +120,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_BSRR GPIO_BSRR(GPIOH) /* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x1C) +#define GPIO_LCKR(port) MMIO32((port) + 0x1C) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) @@ -129,7 +129,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_LCKR GPIO_LCKR(GPIOH) /* Alternate function low register (GPIOx_AFRL) */ -#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIO_AFRL(port) MMIO32((port) + 0x20) #define GPIOA_AFRL GPIO_AFRL(GPIOA) #define GPIOB_AFRL GPIO_AFRL(GPIOB) #define GPIOC_AFRL GPIO_AFRL(GPIOC) @@ -138,7 +138,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_AFRL GPIO_AFRL(GPIOH) /* Alternate function high register (GPIOx_AFRH) */ -#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIO_AFRH(port) MMIO32((port) + 0x24) #define GPIOA_AFRH GPIO_AFRH(GPIOA) #define GPIOB_AFRH GPIO_AFRH(GPIOB) #define GPIOC_AFRH GPIO_AFRH(GPIOC) @@ -148,7 +148,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIOx_MODER values-------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE(n, mode) ((mode) << (2 * (n))) #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode @ingroup gpio_defines @@ -171,7 +171,7 @@ LGPL License Terms @ref lgpl_license /**@}*/ /* Output speed values */ -#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED(n, speed) ((speed) << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @@ -184,7 +184,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIOx_PUPDR values ------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD(n, pupd) ((pupd) << (2 * (n))) #define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_pup GPIO Output Pin Pullup @ingroup gpio_defines @@ -217,7 +217,7 @@ LGPL License Terms @ref lgpl_license /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See datasheet table 5, page 35 for the definitions */ -#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR(n, af) ((af) << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) /** @defgroup gpio_af_num Alternate Function Pin Selection @ingroup gpio_defines diff --git a/include/libopencm3/stm32/l1/timer.h b/include/libopencm3/stm32/l1/timer.h index fbe1504d..f2e3cd6d 100644 --- a/include/libopencm3/stm32/l1/timer.h +++ b/include/libopencm3/stm32/l1/timer.h @@ -43,7 +43,7 @@ LGPL License Terms @ref lgpl_license */ /* Timer 2/3 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM3_OR TIM_OR(TIM3) diff --git a/include/libopencm3/vf6xx/ccm.h b/include/libopencm3/vf6xx/ccm.h index 5793beeb..b0a2569a 100644 --- a/include/libopencm3/vf6xx/ccm.h +++ b/include/libopencm3/vf6xx/ccm.h @@ -56,12 +56,12 @@ #define CCM_CIMR MMIO32(CCM_BASE + 0x34) #define CCM_CCOSR MMIO32(CCM_BASE + 0x38) #define CCM_CGPR MMIO32(CCM_BASE + 0x3C) -#define CCM_CCGR(offset) MMIO32(CCM_BASE + 0x40 + offset) -#define CCM_CMEOR(ovrr) MMIO32(CCM_BASE + 0x70 + (4 * ovrr)) +#define CCM_CCGR(offset) MMIO32(CCM_BASE + 0x40 + (offset)) +#define CCM_CMEOR(ovrr) MMIO32(CCM_BASE + 0x70 + (4 * (ovrr))) #define CCM_CPPDSR MMIO32(CCM_BASE + 0x88) #define CCM_CCOWR MMIO32(CCM_BASE + 0x8C) -#define CCM_CCPGR(pcgr) MMIO32(CCM_BASE + 0x90 + (4 * pcgr)) +#define CCM_CCPGR(pcgr) MMIO32(CCM_BASE + 0x90 + (4 * (pcgr))) /* --- CCM values -....----------------------------------------------------- */ diff --git a/include/libopencm3/vf6xx/gpio.h b/include/libopencm3/vf6xx/gpio.h index c575b3dc..899e4a73 100644 --- a/include/libopencm3/vf6xx/gpio.h +++ b/include/libopencm3/vf6xx/gpio.h @@ -52,15 +52,15 @@ #define GPIO3 (GPIO_BASE + 0x0C0) #define GPIO4 (GPIO_BASE + 0x100) -#define GPIO_OFFSET(gpio) (0x1 << (gpio % 32)) +#define GPIO_OFFSET(gpio) (0x1 << ((gpio) % 32)) /* --- GPIO registers ------------------------------------------------------ */ -#define GPIO_PDOR(gpio_base) MMIO32(gpio_base + 0x00) -#define GPIO_PSOR(gpio_base) MMIO32(gpio_base + 0x04) -#define GPIO_PCOR(gpio_base) MMIO32(gpio_base + 0x08) -#define GPIO_PTOR(gpio_base) MMIO32(gpio_base + 0x0C) -#define GPIO_PDIR(gpio_base) MMIO32(gpio_base + 0x10) +#define GPIO_PDOR(gpio_base) MMIO32((gpio_base) + 0x00) +#define GPIO_PSOR(gpio_base) MMIO32((gpio_base) + 0x04) +#define GPIO_PCOR(gpio_base) MMIO32((gpio_base) + 0x08) +#define GPIO_PTOR(gpio_base) MMIO32((gpio_base) + 0x0C) +#define GPIO_PDIR(gpio_base) MMIO32((gpio_base) + 0x10) /* --- Function prototypes ------------------------------------------------- */ diff --git a/include/libopencm3/vf6xx/iomuxc.h b/include/libopencm3/vf6xx/iomuxc.h index 7daf17db..8786b114 100644 --- a/include/libopencm3/vf6xx/iomuxc.h +++ b/include/libopencm3/vf6xx/iomuxc.h @@ -45,7 +45,7 @@ @ingroup VF6xx_iomuxc_defines @{*/ -#define IOMUXC(pad) MMIO32(IOMUXC_BASE + (0x4 * pad)) +#define IOMUXC(pad) MMIO32(IOMUXC_BASE + (0x4 * (pad))) #define IOMUXC_PAD(mode, speed, dse, pus, flags) \ (IOMUXC_##mode) << IOMUXC_MUX_MODE_SHIFT | \ diff --git a/include/libopencm3/vf6xx/uart.h b/include/libopencm3/vf6xx/uart.h index 07caa1d0..369918c9 100644 --- a/include/libopencm3/vf6xx/uart.h +++ b/include/libopencm3/vf6xx/uart.h @@ -54,20 +54,20 @@ /* --- UART registers ------------------------------------------------------ */ -#define UART_BDH(uart_base) MMIO8(uart_base + 0x00) -#define UART_BDL(uart_base) MMIO8(uart_base + 0x01) -#define UART_C1(uart_base) MMIO8(uart_base + 0x02) -#define UART_C2(uart_base) MMIO8(uart_base + 0x03) -#define UART_S1(uart_base) MMIO8(uart_base + 0x04) -#define UART_S2(uart_base) MMIO8(uart_base + 0x05) -#define UART_C3(uart_base) MMIO8(uart_base + 0x06) -#define UART_D(uart_base) MMIO8(uart_base + 0x07) -#define UART_MA1(uart_base) MMIO8(uart_base + 0x08) -#define UART_MA2(uart_base) MMIO8(uart_base + 0x09) -#define UART_C4(uart_base) MMIO8(uart_base + 0x0A) -#define UART_C5(uart_base) MMIO8(uart_base + 0x0B) -#define UART_ED(uart_base) MMIO8(uart_base + 0x0C) -#define UART_MODEM(uart_base) MMIO8(uart_base + 0x0D) +#define UART_BDH(uart_base) MMIO8((uart_base) + 0x00) +#define UART_BDL(uart_base) MMIO8((uart_base) + 0x01) +#define UART_C1(uart_base) MMIO8((uart_base) + 0x02) +#define UART_C2(uart_base) MMIO8((uart_base) + 0x03) +#define UART_S1(uart_base) MMIO8((uart_base) + 0x04) +#define UART_S2(uart_base) MMIO8((uart_base) + 0x05) +#define UART_C3(uart_base) MMIO8((uart_base) + 0x06) +#define UART_D(uart_base) MMIO8((uart_base) + 0x07) +#define UART_MA1(uart_base) MMIO8((uart_base) + 0x08) +#define UART_MA2(uart_base) MMIO8((uart_base) + 0x09) +#define UART_C4(uart_base) MMIO8((uart_base) + 0x0A) +#define UART_C5(uart_base) MMIO8((uart_base) + 0x0B) +#define UART_ED(uart_base) MMIO8((uart_base) + 0x0C) +#define UART_MODEM(uart_base) MMIO8((uart_base) + 0x0D) /* Incomplete */ /* --- CCM values -....----------------------------------------------------- */ |