20 files changed, 980 insertions, 1150 deletions

diff --git a/include/libopencm3/stm32/common/i2c_common_f24.h b/include/libopencm3/stm32/common/i2c_common_f24.h
deleted file mode 100644
index a056114c..00000000
--- a/include/libopencm3/stm32/common/i2c_common_f24.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @addtogroup i2c_defines
-
-@author @htmlonly © @endhtmlonly 2012
-Ken Sarkies <ksarkies@internode.on.net>
-
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
-The order of header inclusion is important. i2c.h includes the device
-specific memorymap.h header before including this header file.*/
-
-/** @cond */
-#ifdef LIBOPENCM3_I2C_H
-/** @endcond */
-#ifndef LIBOPENCM3_I2C_COMMON_F24_H
-#define LIBOPENCM3_I2C_COMMON_F24_H
-
-#include <libopencm3/stm32/common/i2c_common_all.h>
-
-/**@{*/
-
-#define I2C3				I2C3_BASE
-
-/**@}*/
-
-#endif
-/** @cond */
-#else
-#warning "i2c_common_f24.h should not be included explicitly, only via i2c.h"
-#endif
-/** @endcond */
-
diff --git a/include/libopencm3/stm32/common/i2c_common_all.h b/include/libopencm3/stm32/common/i2c_common_v1.h
index 059ef10f..bded08b5 100644
--- a/include/libopencm3/stm32/common/i2c_common_all.h
+++ b/include/libopencm3/stm32/common/i2c_common_v1.h
@@ -26,13 +26,13 @@
 The order of header inclusion is important. i2c.h includes the device
 specific memorymap.h header before including this header file.*/
 
+/**@{*/
+
 /** @cond */
-#if defined(LIBOPENCM3_I2C_H)
+#ifdef LIBOPENCM3_I2C_H
 /** @endcond */
-#ifndef LIBOPENCM3_I2C_COMMON_ALL_H
-#define LIBOPENCM3_I2C_COMMON_ALL_H
-
-/**@{*/
+#ifndef LIBOPENCM3_I2C_COMMON_V1_H
+#define LIBOPENCM3_I2C_COMMON_V1_H
 
 /* --- Convenience macros -------------------------------------------------- */
 
@@ -397,7 +397,7 @@ END_DECLS
 #endif
 /** @cond */
 #else
-#warning "i2c_common_all.h should not be included explicitly, only via i2c.h"
+#warning "i2c_common_v1.h should not be included explicitly, only via i2c.h"
 #endif
 /** @endcond */
 /**@}*/
diff --git a/include/libopencm3/stm32/common/i2c_common_v2.h b/include/libopencm3/stm32/common/i2c_common_v2.h
new file mode 100644
index 00000000..7f99cb05
--- /dev/null
+++ b/include/libopencm3/stm32/common/i2c_common_v2.h
@@ -0,0 +1,446 @@
+/** @addtogroup i2c_defines
+ *
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H
+The order of header inclusion is important. i2c.h includes the device
+specific memorymap.h header before including this header file.*/
+
+/**@{*/
+
+/** @cond */
+#ifdef LIBOPENCM3_I2C_H
+/** @endcond */
+#ifndef LIBOPENCM3_I2C_COMMON_V2_H
+#define LIBOPENCM3_I2C_COMMON_V2_H
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/* I2C register base addresses (for convenience) */
+/*****************************************************************************/
+/** @defgroup i2c_reg_base I2C register base address
+ * @ingroup i2c_defines
+ * @{*/
+#define I2C1				I2C1_BASE
+#define I2C2				I2C2_BASE
+/**@}*/
+
+/* --- I2C registers ------------------------------------------------------- */
+
+/* Control register 1 (I2Cx_CR1) */
+#define I2C_CR1(i2c_base)		MMIO32((i2c_base) + 0x00)
+#define I2C1_CR1			I2C_CR1(I2C1)
+#define I2C2_CR1			I2C_CR1(I2C2)
+
+/* Control register 2 (I2Cx_CR2) */
+#define I2C_CR2(i2c_base)		MMIO32((i2c_base) + 0x04)
+#define I2C1_CR2			I2C_CR2(I2C1)
+#define I2C2_CR2			I2C_CR2(I2C2)
+
+/* Own address register 1 (I2Cx_OAR1) */
+#define I2C_OAR1(i2c_base)		MMIO32((i2c_base) + 0x08)
+#define I2C1_OAR1			I2C_OAR1(I2C1)
+#define I2C2_OAR1			I2C_OAR1(I2C2)
+
+/* Own address register 2 (I2Cx_OAR2) */
+#define I2C_OAR2(i2c_base)		MMIO32((i2c_base) + 0x0c)
+#define I2C1_OAR2			I2C_OAR2(I2C1)
+#define I2C2_OAR2			I2C_OAR2(I2C2)
+
+/* Timing register (I2Cx_TIMINGR) */
+#define I2C_TIMINGR(i2c_base)		MMIO32((i2c_base) + 0x10)
+#define I2C1_TIMINGR			I2C_TIMINGR(I2C1)
+#define I2C2_TIMINGR			I2C_TIMINGR(I2C2)
+
+/* Timeout register (I2Cx_TIMEOUTR) */
+#define I2C_TIMEOUTR(i2c_base)		MMIO32((i2c_base) + 0x14)
+#define I2C1_TIMEOUTR			I2C_TIMEOUTR(I2C1)
+#define I2C2_TIMEOUTR			I2C_TIMEOUTR(I2C2)
+
+/* Interrupt and Status register (I2Cx_ISR) */
+#define I2C_ISR(i2c_base)		MMIO32((i2c_base) + 0x18)
+#define I2C1_ISR			I2C_ISR(I2C1)
+#define I2C2_ISR			I2C_ISR(I2C2)
+
+/* Interrupt clear register (I2Cx_ICR) */
+#define I2C_ICR(i2c_base)		MMIO32((i2c_base) + 0x1C)
+#define I2C1_ICR			I2C_ICR(I2C1)
+#define I2C2_ICR			I2C_ICR(I2C2)
+
+/* PEC register (I2Cx_PECR) */
+#define I2C_PECR(i2c_base)		MMIO32((i2c_base) + 0x20)
+#define I2C1_PECR			I2C_PECR(I2C1)
+#define I2C2_PECR			I2C_PECR(I2C2)
+
+/* Receive data register (I2Cx_RXDR) */
+#define I2C_RXDR(i2c_base)		MMIO32((i2c_base) + 0x24)
+#define I2C1_RXDR			I2C_RXDR(I2C1)
+#define I2C2_RXDR			I2C_RXDR(I2C2)
+
+/* Transmit data register (I2Cx_TXDR) */
+#define I2C_TXDR(i2c_base)		MMIO32((i2c_base) + 0x28)
+#define I2C1_TXDR			I2C_TXDR(I2C1)
+#define I2C2_TXDR			I2C_TXDR(I2C2)
+
+/* --- I2Cx_CR1 values ----------------------------------------------------- */
+
+/* PECEN: PEC enable */
+#define I2C_CR1_PECEN			(1 << 23)
+
+/* ALERTEN: SMBus alert enable */
+#define I2C_CR1_ALERTEN			(1 << 22)
+
+/* SMBDEN: SMBus Device Default address enable */
+#define I2C_CR1_SMBDEN			(1 << 21)
+
+/* SMBHEN: SMBus Host address enable */
+#define I2C_CR1_SMBHEN			(1 << 20)
+
+/* GCEN: General call enable */
+#define I2C_CR1_GCEN			(1 << 19)
+
+/* WUPEN: Wakeup from STOP enable */
+#define I2C_CR1_WUPEN			(1 << 18)
+
+/* NOSTRETCH: Clock stretching disable */
+#define I2C_CR1_NOSTRETCH		(1 << 17)
+
+/* SBC: Slave byte control */
+#define I2C_CR1_SBC			(1 << 16)
+
+/* RXDMAEN: DMA reception requests enable */
+#define I2C_CR1_RXDMAEN			(1 << 15)
+
+/* TXDMAEN: DMA transmission requests enable */
+#define I2C_CR1_TXDMAEN			(1 << 14)
+
+/* ANFOFF: Analog noise filter OFF */
+#define I2C_CR1_ANFOFF			(1 << 12)
+
+/* DNF[3:0]: Digital noise filter */
+#define I2C_CR1_DNF_DISABLED		(0x0 << 8)
+#define I2C_CR1_DNF_UP_1_TI2CCLK	(0x1 << 8)
+#define I2C_CR1_DNF_UP_2_TI2CCLK	(0x2 << 8)
+#define I2C_CR1_DNF_UP_3_TI2CCLK	(0x3 << 8)
+#define I2C_CR1_DNF_UP_4_TI2CCLK	(0x4 << 8)
+#define I2C_CR1_DNF_UP_5_TI2CCLK	(0x5 << 8)
+#define I2C_CR1_DNF_UP_6_TI2CCLK	(0x6 << 8)
+#define I2C_CR1_DNF_UP_7_TI2CCLK	(0x7 << 8)
+#define I2C_CR1_DNF_UP_8_TI2CCLK	(0x8 << 8)
+#define I2C_CR1_DNF_UP_9_TI2CCLK	(0x9 << 8)
+#define I2C_CR1_DNF_UP_10_TI2CCLK	(0xA << 8)
+#define I2C_CR1_DNF_UP_11_TI2CCLK	(0xB << 8)
+#define I2C_CR1_DNF_UP_12_TI2CCLK	(0xC << 8)
+#define I2C_CR1_DNF_UP_13_TI2CCLK	(0xD << 8)
+#define I2C_CR1_DNF_UP_14_TI2CCLK	(0xE << 8)
+#define I2C_CR1_DNF_UP_15_TI2CCLK	(0xF << 8)
+#define I2C_CR1_DNF_MASK                (0xF << 8)
+
+/* ERRIE: Error interrupts enable */
+#define I2C_CR1_ERRIE			(1 << 7)
+
+/* TCIE: Transfer Complete interrupt enable */
+#define I2C_CR1_TCIE			(1 << 6)
+
+/* STOPIE: STOP detection Interrupt enable */
+#define I2C_CR1_STOPIE			(1 << 5)
+
+/* NACKIE: Not acknowledge received Interrupt enable */
+#define I2C_CR1_NACKIE			(1 << 4)
+
+/* ADDRIE: Address match Interrupt enable (slave only) */
+#define I2C_CR1_DDRIE			(1 << 3)
+
+/* RXIE: RX Interrupt enable */
+#define I2C_CR1_RXIE			(1 << 2)
+
+/* TXIE: TX Interrupt enable */
+#define I2C_CR1_TXIE			(1 << 1)
+
+/* PE: Peripheral enable */
+#define I2C_CR1_PE			(1 << 0)
+
+/* --- I2Cx_CR2 values ----------------------------------------------------- */
+
+/* PECBYTE: Packet error checking byte */
+#define I2C_CR2_PECBYTE			(1 << 26)
+
+/* AUTOEND: Automatic end mode (master mode) */
+#define I2C_CR2_AUTOEND			(1 << 25)
+
+/* RELOAD: NBYTES reload mode */
+#define I2C_CR2_RELOAD			(1 << 24)
+
+/* NBYTES[7:0]: Number of bytes (23,16) */
+#define I2C_CR2_NBYTES_SHIFT            16
+#define I2C_CR2_NBYTES_MASK             (0xFF << I2C_CR2_NBYTES_SHIFT)
+
+/* NACK: NACK generation (slave mode) */
+#define I2C_CR2_NACK			(1 << 15)
+
+/* STOP: Stop generation (master mode) */
+#define I2C_CR2_STOP			(1 << 14)
+
+/* START: Start generation */
+#define I2C_CR2_START			(1 << 13)
+
+/* HEAD10R: 10-bit address header only read direction (master receiver mode) */
+#define I2C_CR2_HEAD10R			(1 << 12)
+
+/* ADD10: 10-bit addressing mode (master mode) */
+#define I2C_CR2_ADD10			(1 << 11)
+
+/* RD_WRN: Transfer direction (master mode) */
+#define I2C_CR2_RD_WRN			(1 << 10)
+
+#define I2C_CR2_SADD_7BIT_SHIFT         1
+#define I2C_CR2_SADD_10BIT_SHIFT        0
+#define I2C_CR2_SADD_7BIT_MASK          (0x7F << I2C_CR2_SADD_7BIT_SHIFT)
+#define I2C_CR2_SADD_10BIT_MASK         0x3FF
+
+/* --- I2Cx_OAR1 values ---------------------------------------------------- */
+
+/* OA1EN: Own Address 1 enable */
+#define I2C_OAR1_OA1EN_DISABLE		(0x0 << 15)
+#define I2C_OAR1_OA1EN_ENABLE		(0x1 << 15)
+
+/* OA1MODE Own Address 1 10-bit mode */
+#define I2C_OAR1_OA1MODE		(1 << 10)
+#define I2C_OAR1_OA1MODE_7BIT		0
+#define I2C_OAR1_OA1MODE_10BIT		1
+
+/* OA1[9:8]: Interface address */
+
+/* OA1[7:1]: Interface address */
+
+/* OA1[0]: Interface address */
+#define I2C_OAR1_OA1			(1 << 10)
+#define I2C_OAR1_OA1_7BIT		0
+#define I2C_OAR1_OA1_10BIT		1
+
+/* --- I2Cx_OAR2 values ---------------------------------------------------- */
+
+/* OA2EN: Own Address 2 enable */
+#define I2C_OAR2_OA2EN			(1 << 15)
+
+/* OA2MSK[2:0]: Own Address 2 masks */
+#define I2C_OAR2_OA2MSK_NO_MASK		(0x0 << 8)
+#define I2C_OAR2_OA2MSK_OA2_7_OA2_2	(0x1 << 8)
+#define I2C_OAR2_OA2MSK_OA2_7_OA2_3	(0x2 << 8)
+#define I2C_OAR2_OA2MSK_OA2_7_OA2_4	(0x3 << 8)
+#define I2C_OAR2_OA2MSK_OA2_7_OA2_5	(0x4 << 8)
+#define I2C_OAR2_OA2MSK_OA2_7_OA2_6	(0x5 << 8)
+#define I2C_OAR2_OA2MSK_OA2_7		(0x6 << 8)
+#define I2C_OAR2_OA2MSK_NO_CMP		(0x7 << 8)
+
+/* OA2[7:1]: Interface address */
+
+/* --- I2Cx_TIMINGR values ------------------------------------------------- */
+
+/* PRESC[3:0]: Timing prescaler (31,28) */
+#define I2C_TIMINGR_PRESC_SHIFT 28
+#define I2C_TIMINGR_PRESC_MASK (0xF << 28)
+
+/* SCLDEL[3:0]: Data setup time (23,20) */
+#define I2C_TIMINGR_SCLDEL_SHIFT 20
+#define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT)
+
+/* SDADEL[3:0]: Data hold time (19,16) */
+#define I2C_TIMINGR_SDADEL_SHIFT 16
+#define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT)
+
+/* SCLH[7:0]: SCL high period (master mode) (15,8) */
+#define I2C_TIMINGR_SCLH_SHIFT 8
+#define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT)
+
+/* SCLL[7:0]: SCL low period (master mode) (7,0) */
+#define I2C_TIMINGR_SCLL_SHIFT 0
+#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)
+
+/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */
+
+/* TEXTEN: Extended clock timeout enable */
+#define I2C_TIEMOUTR_TEXTEN		(1 << 31)
+
+/* XXX: Not clear yet. */
+/* TIMEOUTB[11:0]: Bus timeout B */
+
+/* TIMOUTEN: Clock timeout enable */
+#define I2C_TIEMOUTR_TIMOUTEN		(1 << 15)
+
+/* TIDLE: Idle clock timeout detection */
+#define I2C_TIEMOUTR_TIDLE_SCL_LOW	(0x0 << 12)
+#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH	(0x1 << 12)
+
+/* XXX: Not clear yet. */
+/* TIMEOUTA[11:0]: Bus Timeout A */
+
+/* --- I2Cx_ISR values ----------------------------------------------------- */
+
+/* Bits 31:24 Reserved, must be kept at reset value */
+
+/* XXX: Not clear yet. */
+/* ADDCODE[6:0]: Address match code (Slave mode) */
+
+/* DIR: Transfer direction (Slave mode) */
+#define I2C_ISR_DIR_READ		(0x1 << 16)
+#define I2C_ISR_DIR_WRITE		(0x0 << 16)
+
+/* BUSY: Bus busy */
+#define I2C_ISR_BUSY			(1 << 15)
+
+/* ALERT: SMBus alert */
+#define I2C_ISR_ALERT			(1 << 13)
+
+/* TIMEOUT: Timeout or tLOW detection flag */
+#define I2C_ISR_TIMEOUT			(1 << 12)
+
+/* PECERR: PEC Error in reception */
+#define I2C_ISR_PECERR			(1 << 11)
+
+/* OVR: Overrun/Underrun (slave mode) */
+#define I2C_ISR_OVR			(1 << 10)
+
+/* ARLO: Arbitration lost */
+#define I2C_ISR_ARLO			(1 << 9)
+
+/* BERR: Bus error */
+#define I2C_ISR_BERR			(1 << 8)
+
+/* TCR: Transfer Complete Reload */
+#define I2C_ISR_TCR			(1 << 7)
+
+/* TC: Transfer Complete (master mode) */
+#define I2C_ISR_TC			(1 << 6)
+
+/* STOPF: Stop detection flag */
+#define I2C_ISR_STOPF			(1 << 5)
+
+/* NACKF: Not Acknowledge received flag */
+#define I2C_ISR_NACKF			(1 << 4)
+
+/* ADDR: Address matched (slave mode) */
+#define I2C_ISR_ADDR			(1 << 3)
+
+/* RXNE: Receive data register not empty (receivers) */
+#define I2C_ISR_RXNE			(1 << 2)
+
+/* TXIS: Transmit interrupt status (transmitters) */
+#define I2C_ISR_TXIS			(1 << 1)
+
+/* TXE: Transmit data register empty (transmitters) */
+#define I2C_ISR_TXE			(1 << 0)
+
+/* --- I2Cx_ICR values ----------------------------------------------------- */
+
+/* ALERTCF: Alert flag clear */
+#define I2C_ICR_ALERTCF			(1 << 13)
+
+/* TIMOUTCF: Timeout detection flag clear */
+#define I2C_ICR_TIMOUTCF		(1 << 12)
+
+/* PECCF: PEC Error flag clear */
+#define I2C_ICR_PECCF			(1 << 11)
+
+/* OVRCF: Overrun/Underrun flag clear */
+#define I2C_ICR_OVRCF			(1 << 10)
+
+/* ARLOCF: Arbitration Lost flag clear */
+#define I2C_ICR_ARLOCF			(1 << 9)
+
+/* BERRCF: Bus error flag clear */
+#define I2C_ICR_BERRCF			(1 << 8)
+
+/* STOPCF: Stop detection flag clear */
+#define I2C_ICR_STOPCF			(1 << 5)
+
+/* NACKCF: Not Acknowledge flag clear */
+#define I2C_ICR_NACKCF			(1 << 4)
+
+/* ADDRCF: Address Matched flag clear */
+#define I2C_ICR_ADDRCF			(1 << 3)
+
+/* --- I2Cx_PECR values ---------------------------------------------------- */
+
+/* PEC[7:0] Packet error checking register  */
+
+/* --- I2C function prototypes---------------------------------------------- */
+
+BEGIN_DECLS
+
+void i2c_reset(uint32_t i2c);
+void i2c_peripheral_enable(uint32_t i2c);
+void i2c_peripheral_disable(uint32_t i2c);
+void i2c_send_start(uint32_t i2c);
+void i2c_send_stop(uint32_t i2c);
+void i2c_clear_stop(uint32_t i2c);
+void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
+void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
+void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
+void i2c_send_data(uint32_t i2c, uint8_t data);
+uint8_t i2c_get_data(uint32_t i2c);
+
+void i2c_enable_analog_filter(uint32_t i2c);
+void i2c_disable_analog_filter(uint32_t i2c);
+void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting);
+void i2c_set_prescaler(uint32_t i2c, uint8_t presc);
+void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time);
+void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time);
+void i2c_set_scl_high_period(uint32_t i2c, uint8_t period);
+void i2c_set_scl_low_period(uint32_t i2c, uint8_t period);
+void i2c_enable_stretching(uint32_t i2c);
+void i2c_disable_stretching(uint32_t i2c);
+void i2c_100khz_i2cclk8mhz(uint32_t i2c);
+void i2c_set_7bit_addr_mode(uint32_t i2c);
+void i2c_set_10bit_addr_mode(uint32_t i2c);
+void i2c_set_7bit_address(uint32_t i2c, uint8_t addr);
+void i2c_set_10bit_address(uint32_t i2c, uint16_t addr);
+void i2c_set_write_transfer_dir(uint32_t i2c);
+void i2c_set_read_transfer_dir(uint32_t i2c);
+void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes);
+uint8_t i2c_is_start(uint32_t i2c);
+void i2c_enable_autoend(uint32_t i2c);
+void i2c_disable_autoend(uint32_t i2c);
+uint8_t i2c_nack(uint32_t i2c);
+uint8_t i2c_busy(uint32_t i2c);
+uint8_t i2c_transmit_int_status(uint32_t i2c);
+uint8_t i2c_transfer_complete(uint32_t i2c);
+uint8_t i2c_received_data(uint32_t i2c);
+void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
+void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
+void i2c_enable_rxdma(uint32_t i2c);
+void i2c_disable_rxdma(uint32_t i2c);
+void i2c_enable_txdma(uint32_t i2c);
+void i2c_disable_txdma(uint32_t i2c);
+void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
+	       uint8_t size, uint8_t *data);
+void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
+	      uint8_t size, uint8_t *data);
+
+END_DECLS
+
+#endif
+/** @cond */
+#else
+#warning "i2c_common_v2.h should not be included explicitly, only via i2c.h"
+#endif
+/** @endcond */
+/**@}*/
+
diff --git a/include/libopencm3/stm32/f0/i2c.h b/include/libopencm3/stm32/f0/i2c.h
index ea7d98d3..d105a2fc 100644
--- a/include/libopencm3/stm32/f0/i2c.h
+++ b/include/libopencm3/stm32/f0/i2c.h
@@ -32,225 +32,7 @@
 #ifndef LIBOPENCM3_I2C_H
 #define LIBOPENCM3_I2C_H
 
-/*****************************************************************************/
-/* Module definitions                                                        */
-/*****************************************************************************/
-
-#define I2C1				I2C1_BASE
-#define I2C2				I2C2_BASE
-
-/*****************************************************************************/
-/* Register definitions                                                      */
-/*****************************************************************************/
-
-#define I2C_CR1(i2c_base)		MMIO32((i2c_base) + 0x00)
-#define I2C1_CR1			I2C_CR1(I2C1)
-#define I2C2_CR1			I2C_CR1(I2C2)
-
-#define I2C_CR2(i2c_base)		MMIO32((i2c_base) + 0x04)
-#define I2C1_CR2			I2C_CR2(I2C1)
-#define I2C2_CR2			I2C_CR2(I2C2)
-
-#define I2C_OAR1(i2c_base)		MMIO32((i2c_base) + 0x08)
-#define I2C1_OAR1			I2C_OAR1(I2C1)
-#define I2C2_OAR1			I2C_OAR1(I2C2)
-
-#define I2C_OAR2(i2c_base)		MMIO32((i2c_base) + 0x0c)
-#define I2C1_OAR2			I2C_OAR2(I2C1)
-#define I2C2_OAR2			I2C_OAR2(I2C2)
-
-#define I2C_TIMINGR(i2c_base)		MMIO32((i2c_base) + 0x10)
-#define I2C1_TIMINGR			I2C_TIMINGR(I2C1)
-#define I2C2_TIMINGR			I2C_TIMINGR(I2C2)
-
-#define I2C_TIMEOUTR(i2c_base)		MMIO32((i2c_base) + 0x14)
-#define I2C1_TIMEOUTR			I2C_TIMEOUTR(I2C1)
-#define I2C2_TIMEOUTR			I2C_TIMEOUTR(I2C2)
-
-#define I2C_ISR(i2c_base)		MMIO32((i2c_base) + 0x18)
-#define I2C1_ISR			I2C_ISR(I2C1)
-#define I2C2_ISR			I2C_ISR(I2C2)
-
-#define I2C_ICR(i2c_base)		MMIO32((i2c_base) + 0x1C)
-#define I2C1_ICR			I2C_ICR(I2C1)
-#define I2C2_ICR			I2C_ICR(I2C2)
-
-#define I2C_PECR(i2c_base)		MMIO8((i2c_base) + 0x20)
-#define I2C1_PECR			I2C_PECR(I2C1)
-#define I2C2_PECR			I2C_PECR(I2C2)
-
-#define I2C_RXDR(i2c_base)		MMIO8((i2c_base) + 0x24)
-#define I2C1_RXDR			I2C_RXDR(I2C1)
-#define I2C2_RXDR			I2C_RXDR(I2C2)
-
-#define I2C_TXDR(i2c_base)		MMIO8((i2c_base) + 0x28)
-#define I2C1_TXDR			I2C_TXDR(I2C1)
-#define I2C2_TXDR			I2C_TXDR(I2C2)
-
-/*****************************************************************************/
-/* Register values                                                           */
-/*****************************************************************************/
-
-/* I2C_CR1 values ---------------------------------------------------------- */
-
-#define I2C_CR1_PECEN			(1 << 23)
-#define I2C_CR1_ALERTEN			(1 << 22)
-#define I2C_CR1_SMBDEN			(1 << 21)
-#define I2C_CR1_SMBHEN			(1 << 20)
-#define I2C_CR1_GCEN			(1 << 19)
-#define I2C_CR1_WUPEN			(1 << 18)
-#define I2C_CR1_NOSTRETCH		(1 << 17)
-#define I2C_CR1_SBC			(1 << 16)
-#define I2C_CR1_RXDMAEN			(1 << 15)
-#define I2C_CR1_TXDMAEN			(1 << 14)
-#define I2C_CR1_ANFOFF			(1 << 12)
-
-#define I2C_CR1_DNF_SHIFT		8
-#define I2C_CR1_DNF			(0x0F << I2C_CR1_DNF_SHIFT)
-#define I2C_CR1_DNF_VAL(x)		((x) << I2C_CR1_DNF_SHIFT)
-
-#define I2C_CR1_ERRIE			(1 << 7)
-#define I2C_CR1_TCIE			(1 << 6)
-#define I2C_CR1_STOPIE			(1 << 5)
-#define I2C_CR1_NACKIE			(1 << 4)
-#define I2C_CR1_ADDRIE			(1 << 3)
-#define I2C_CR1_RXIE			(1 << 2)
-#define I2C_CR1_TXIE			(1 << 1)
-#define I2C_CR1_PE			(1 << 0)
-
-/* I2C_CR2 values ---------------------------------------------------------- */
-
-#define I2C_CR2_PECBYTE			(1 << 26)
-#define I2C_CR2_AUTOEND			(1 << 25)
-#define I2C_CR2_RELOAD			(1 << 24)
-
-#define I2C_CR2_NBYTES_SHIFT		16
-#define I2C_CR2_NBYTES			(0xFF << I2C_CR2_NBYTES_SHIFT)
-#define I2C_CR2_NBYTES_VAL(x)		((x) << I2C_CR2_NBYTES_SHIFT)
-
-#define I2C_CR2_NACK			(1 << 15)
-#define I2C_CR2_STOP			(1 << 14)
-#define I2C_CR2_START			(1 << 13)
-#define I2C_CR2_HEAD10R			(1 << 12)
-#define I2C_CR2_ADD10			(1 << 11)
-#define I2C_CR2_RD_WRN			(1 << 10)
-
-#define I2C_CR2_SADD_SHIFT		0
-#define I2C_CR2_SADD			(0x3FF << I2C_CR2_SADD_SHIFT)
-#define I2C_CR2_SADD_VAL(x)		((x) << I2C_CR2_SADD_SHIFT)
-
-/* I2C_OAR1 values --------------------------------------------------------- */
-
-#define I2C_OAR1_OA1EN			(1 << 15)
-#define I2C_OAR1_OA1MODE		(1 << 10)
-
-#define I2C_OAR1_OA1_SHIFT		0
-#define I2C_OAR1_OA1			(0x3FF << I2C_OAR1_OA1_SHIFT)
-#define I2C_OAR1_OA1_VAL(x)		((x) << I2C_OAR1_OA1_SHIFT)
-
-/* I2C_OAR2 values --------------------------------------------------------- */
-
-#define I2C_OAR2_OA1EN			(1 << 15)
-
-#define I2C_OAR2_OA2MSK_SHIFT		8
-#define I2C_OAR2_OA2MSK			(7 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_NOMASK		(0 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_1_BIT		(1 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_2_BIT		(2 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_3_BIT		(3 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_4_BIT		(4 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_5_BIT		(5 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_6_BIT		(6 << I2C_OAR2_OA2MSK_SHIFT)
-#define I2C_OAR2_OA2MSK_ALL		(7 << I2C_OAR2_OA2MSK_SHIFT)
-
-#define I2C_OAR2_OA2_SHIFT		1
-#define I2C_OAR2_OA2			(0x7F << I2C_OAR2_OA2_SHIFT)
-#define I2C_OAR2_OA2_VAL(x)		((x) << I2C_OAR2_OA2_SHIFT)
-
-/* I2C_TIMINGR values ------------------------------------------------------ */
-
-#define I2C_TIMINGR_PRESC_SHIFT		28
-#define I2C_TIMINGR_PRESC		(0x0F << I2C_TIMINGR_PRESC_SHIFT)
-#define I2C_TIMINGR_PRESC_VAL(x)	((x) << I2C_TIMINGR_PRESC_SHIFT)
-
-#define I2C_TIMINGR_SCLDEL_SHIFT	20
-#define I2C_TIMINGR_SCLDEL		(0x0F << I2C_TIMINGR_SCLDEL_SHIFT)
-#define I2C_TIMINGR_SCLDEL_VAL(x)	((x) << I2C_TIMINGR_SCLDEL_SHIFT)
-
-#define I2C_TIMINGR_SDADEL_SHIFT	16
-#define I2C_TIMINGR_SDADEL		(0x0F << I2C_TIMINGR_SDADEL_SHIFT)
-#define I2C_TIMINGR_SDADEL_VAL(x)	((x) << I2C_TIMINGR_SDADEL_SHIFT)
-
-#define I2C_TIMINGR_SCLH_SHIFT		8
-#define I2C_TIMINGR_SCLH		(0xFF << I2C_TIMINGR_SCLH_SHIFT)
-#define I2C_TIMINGR_SCLH_VAL(x)		((x) << I2C_TIMINGR_SCLH_SHIFT)
-
-#define I2C_TIMINGR_SCLL_SHIFT		0
-#define I2C_TIMINGR_SCLL		(0xFF << I2C_TIMINGR_SCLL_SHIFT)
-#define I2C_TIMINGR_SCLL_VAL(x)		((x) << I2C_TIMINGR_SCLL_SHIFT)
-
-/* I2C_TIMEOUTR values ----------------------------------------------------- */
-
-#define I2C_TIMEOUTR_TETXEN		(1 << 31)
-
-#define I2C_TIMEOUTR_TIMEOUTB_SHIFT	16
-#define I2C_TIMEOUTR_TIMEOUTB		(0xFFF << I2C_TIMEOUTR_TIMEOUTB_SHIFT)
-#define I2C_TIMEOUTR_TIMEOUTB_VAL(x)	((x) << I2C_TIMEOUTR_TIMEOUTB_SHIFT)
-
-#define I2C_TIMEOUTR_TIMOUTEN		(1 << 15)
-#define I2C_TIMEOUTR_TIDLE		(1 << 12)
-
-#define I2C_TIMEOUTR_TIMEOUTA_SHIFT	0
-#define I2C_TIMEOUTR_TIMEOUTA		(0xFFF << I2C_TIMEOUTR_TIMEOUTA_SHIFT)
-#define I2C_TIMEOUTR_TIMEOUTA_VAL(x)	((x) << I2C_TIMEOUTR_TIMEOUTA_SHIFT)
-
-/* I2C_ISR values ---------------------------------------------------------- */
-
-#define I2C_ISR_ADDCODE_SHIFT		17
-#define I2C_ISR_ADDCODE			(0x7F << I2C_ISR_ADDCODE_SHIFT)
-#define I2C_ISR_ADDCODE_VAL(x)		((x) << I2C_ISR_ADDCODE_SHIFT)
-#define I2C_ISR_ADDCODE_VALG(reg)	(((reg) & I2C_ISR_ADDCODE) >> \
-						I2C_ISR_ADDCODE_SHIFT)
-
-#define I2C_ISR_DIR			(1 << 16)
-#define I2C_ISR_BUSY			(1 << 15)
-#define I2C_ISR_ALERT			(1 << 13)
-#define I2C_ISR_TIMEOUT			(1 << 12)
-#define I2C_ISR_PECERR			(1 << 11)
-#define I2C_ISR_OVR			(1 << 10)
-#define I2C_ISR_ARLO			(1 << 9)
-#define I2C_ISR_BERR			(1 << 8)
-#define I2C_ISR_TCR			(1 << 7)
-#define I2C_ISR_TC			(1 << 6)
-#define I2C_ISR_STOPF			(1 << 5)
-#define I2C_ISR_NACKF			(1 << 4)
-#define I2C_ISR_ADDR			(1 << 3)
-#define I2C_ISR_RXNE			(1 << 2)
-#define I2C_ISR_TXIS			(1 << 1)
-#define I2C_ISR_TXE			(1 << 0)
-
-/* I2C_ICR values ---------------------------------------------------------- */
-
-#define I2C_ICR_ALERTCF			(1 << 13)
-#define I2C_ICR_TIMEOUTCF		(1 << 12)
-#define I2C_ICR_PECCF			(1 << 11)
-#define I2C_ICR_OVRCF			(1 << 10)
-#define I2C_ICR_ARLOCF			(1 << 9)
-#define I2C_ICR_BERRCF			(1 << 8)
-#define I2C_ICR_STOPCF			(1 << 5)
-#define I2C_ICR_NACKCF			(1 << 4)
-#define I2C_ICR_ADDRCF			(1 << 3)
-
-/*****************************************************************************/
-/* API definitions                                                           */
-/*****************************************************************************/
-
-/*****************************************************************************/
-/* API Functions                                                             */
-/*****************************************************************************/
-
-BEGIN_DECLS
-
-END_DECLS
+#include <libopencm3/stm32/common/i2c_common_v2.h>
 
 #endif
+
diff --git a/include/libopencm3/stm32/f1/i2c.h b/include/libopencm3/stm32/f1/i2c.h
index 19c26a35..f7e25f79 100644
--- a/include/libopencm3/stm32/f1/i2c.h
+++ b/include/libopencm3/stm32/f1/i2c.h
@@ -31,7 +31,7 @@ LGPL License Terms @ref lgpl_license
 #ifndef LIBOPENCM3_I2C_H
 #define LIBOPENCM3_I2C_H
 
-#include <libopencm3/stm32/common/i2c_common_all.h>
+#include <libopencm3/stm32/common/i2c_common_v1.h>
 
 #endif
 
diff --git a/include/libopencm3/stm32/f2/i2c.h b/include/libopencm3/stm32/f2/i2c.h
index c1be84c5..9c8afc94 100644
--- a/include/libopencm3/stm32/f2/i2c.h
+++ b/include/libopencm3/stm32/f2/i2c.h
@@ -31,7 +31,13 @@ LGPL License Terms @ref lgpl_license
 #ifndef LIBOPENCM3_I2C_H
 #define LIBOPENCM3_I2C_H
 
-#include <libopencm3/stm32/common/i2c_common_f24.h>
+#include <libopencm3/stm32/common/i2c_common_v1.h>
+
+/**@{*/
+
+#define I2C3				I2C3_BASE
+
+/**@}*/
 
 #endif
 
diff --git a/include/libopencm3/stm32/f3/i2c.h b/include/libopencm3/stm32/f3/i2c.h
index 6554d680..ee16a86e 100644
--- a/include/libopencm3/stm32/f3/i2c.h
+++ b/include/libopencm3/stm32/f3/i2c.h
@@ -31,413 +31,7 @@
 #ifndef LIBOPENCM3_I2C_H
 #define LIBOPENCM3_I2C_H
 
-/**@{*/
-
-/* --- Convenience macros -------------------------------------------------- */
-
-/* I2C register base addresses (for convenience) */
-/*****************************************************************************/
-/** @defgroup i2c_reg_base I2C register base address
- * @ingroup i2c_defines
- * @{*/
-#define I2C1				I2C1_BASE
-#define I2C2				I2C2_BASE
-/**@}*/
-
-/* --- I2C registers ------------------------------------------------------- */
-
-/* Control register 1 (I2Cx_CR1) */
-#define I2C_CR1(i2c_base)		MMIO32((i2c_base) + 0x00)
-#define I2C1_CR1			I2C_CR1(I2C1)
-#define I2C2_CR1			I2C_CR1(I2C2)
-
-/* Control register 2 (I2Cx_CR2) */
-#define I2C_CR2(i2c_base)		MMIO32((i2c_base) + 0x04)
-#define I2C1_CR2			I2C_CR2(I2C1)
-#define I2C2_CR2			I2C_CR2(I2C2)
-
-/* Own address register 1 (I2Cx_OAR1) */
-#define I2C_OAR1(i2c_base)		MMIO32((i2c_base) + 0x08)
-#define I2C1_OAR1			I2C_OAR1(I2C1)
-#define I2C2_OAR1			I2C_OAR1(I2C2)
-
-/* Own address register 2 (I2Cx_OAR2) */
-#define I2C_OAR2(i2c_base)		MMIO32((i2c_base) + 0x0c)
-#define I2C1_OAR2			I2C_OAR2(I2C1)
-#define I2C2_OAR2			I2C_OAR2(I2C2)
-
-/* Timing register (I2Cx_TIMINGR) */
-#define I2C_TIMINGR(i2c_base)		MMIO32((i2c_base) + 0x10)
-#define I2C1_TIMINGR			I2C_TIMINGR(I2C1)
-#define I2C2_TIMINGR			I2C_TIMINGR(I2C2)
-
-/* Timeout register (I2Cx_TIMEOUTR) */
-#define I2C_TIMEOUTR(i2c_base)		MMIO32((i2c_base) + 0x14)
-#define I2C1_TIMEOUTR			I2C_TIMEOUTR(I2C1)
-#define I2C2_TIMEOUTR			I2C_TIMEOUTR(I2C2)
-
-/* Interrupt and Status register (I2Cx_ISR) */
-#define I2C_ISR(i2c_base)		MMIO32((i2c_base) + 0x18)
-#define I2C1_ISR			I2C_ISR(I2C1)
-#define I2C2_ISR			I2C_ISR(I2C2)
-
-/* Interrupt clear register (I2Cx_ICR) */
-#define I2C_ICR(i2c_base)		MMIO32((i2c_base) + 0x1C)
-#define I2C1_ICR			I2C_ICR(I2C1)
-#define I2C2_ICR			I2C_ICR(I2C2)
-
-/* PEC register (I2Cx_PECR) */
-#define I2C_PECR(i2c_base)		MMIO32((i2c_base) + 0x20)
-#define I2C1_PECR			I2C_PECR(I2C1)
-#define I2C2_PECR			I2C_PECR(I2C2)
-
-/* Receive data register (I2Cx_RXDR) */
-#define I2C_RXDR(i2c_base)		MMIO32((i2c_base) + 0x24)
-#define I2C1_RXDR			I2C_RXDR(I2C1)
-#define I2C2_RXDR			I2C_RXDR(I2C2)
-
-/* Transmit data register (I2Cx_TXDR) */
-#define I2C_TXDR(i2c_base)		MMIO32((i2c_base) + 0x28)
-#define I2C1_TXDR			I2C_TXDR(I2C1)
-#define I2C2_TXDR			I2C_TXDR(I2C2)
-
-/* --- I2Cx_CR1 values ----------------------------------------------------- */
-
-/* PECEN: PEC enable */
-#define I2C_CR1_PECEN			(1 << 23)
-
-/* ALERTEN: SMBus alert enable */
-#define I2C_CR1_ALERTEN			(1 << 22)
-
-/* SMBDEN: SMBus Device Default address enable */
-#define I2C_CR1_SMBDEN			(1 << 21)
-
-/* SMBHEN: SMBus Host address enable */
-#define I2C_CR1_SMBHEN			(1 << 20)
-
-/* GCEN: General call enable */
-#define I2C_CR1_GCEN			(1 << 19)
-
-/* WUPEN: Wakeup from STOP enable */
-#define I2C_CR1_WUPEN			(1 << 18)
-
-/* NOSTRETCH: Clock stretching disable */
-#define I2C_CR1_NOSTRETCH		(1 << 17)
-
-/* SBC: Slave byte control */
-#define I2C_CR1_SBC			(1 << 16)
-
-/* RXDMAEN: DMA reception requests enable */
-#define I2C_CR1_RXDMAEN			(1 << 15)
-
-/* TXDMAEN: DMA transmission requests enable */
-#define I2C_CR1_TXDMAEN			(1 << 14)
-
-/* ANFOFF: Analog noise filter OFF */
-#define I2C_CR1_ANFOFF			(1 << 12)
-
-/* DNF[3:0]: Digital noise filter */
-#define I2C_CR1_DNF_DISABLED		(0x0 << 8)
-#define I2C_CR1_DNF_UP_1_TI2CCLK	(0x1 << 8)
-#define I2C_CR1_DNF_UP_2_TI2CCLK	(0x2 << 8)
-#define I2C_CR1_DNF_UP_3_TI2CCLK	(0x3 << 8)
-#define I2C_CR1_DNF_UP_4_TI2CCLK	(0x4 << 8)
-#define I2C_CR1_DNF_UP_5_TI2CCLK	(0x5 << 8)
-#define I2C_CR1_DNF_UP_6_TI2CCLK	(0x6 << 8)
-#define I2C_CR1_DNF_UP_7_TI2CCLK	(0x7 << 8)
-#define I2C_CR1_DNF_UP_8_TI2CCLK	(0x8 << 8)
-#define I2C_CR1_DNF_UP_9_TI2CCLK	(0x9 << 8)
-#define I2C_CR1_DNF_UP_10_TI2CCLK	(0xA << 8)
-#define I2C_CR1_DNF_UP_11_TI2CCLK	(0xB << 8)
-#define I2C_CR1_DNF_UP_12_TI2CCLK	(0xC << 8)
-#define I2C_CR1_DNF_UP_13_TI2CCLK	(0xD << 8)
-#define I2C_CR1_DNF_UP_14_TI2CCLK	(0xE << 8)
-#define I2C_CR1_DNF_UP_15_TI2CCLK	(0xF << 8)
-#define I2C_CR1_DNF_MASK                (0xF << 8)
-
-/* ERRIE: Error interrupts enable */
-#define I2C_CR1_ERRIE			(1 << 7)
-
-/* TCIE: Transfer Complete interrupt enable */
-#define I2C_CR1_TCIE			(1 << 6)
-
-/* STOPIE: STOP detection Interrupt enable */
-#define I2C_CR1_STOPIE			(1 << 5)
-
-/* NACKIE: Not acknowledge received Interrupt enable */
-#define I2C_CR1_NACKIE			(1 << 4)
-
-/* ADDRIE: Address match Interrupt enable (slave only) */
-#define I2C_CR1_DDRIE			(1 << 3)
-
-/* RXIE: RX Interrupt enable */
-#define I2C_CR1_RXIE			(1 << 2)
-
-/* TXIE: TX Interrupt enable */
-#define I2C_CR1_TXIE			(1 << 1)
-
-/* PE: Peripheral enable */
-#define I2C_CR1_PE			(1 << 0)
-
-/* --- I2Cx_CR2 values ----------------------------------------------------- */
-
-/* PECBYTE: Packet error checking byte */
-#define I2C_CR2_PECBYTE			(1 << 26)
-
-/* AUTOEND: Automatic end mode (master mode) */
-#define I2C_CR2_AUTOEND			(1 << 25)
-
-/* RELOAD: NBYTES reload mode */
-#define I2C_CR2_RELOAD			(1 << 24)
-
-/* NBYTES[7:0]: Number of bytes (23,16) */
-#define I2C_CR2_NBYTES_SHIFT            16
-#define I2C_CR2_NBYTES_MASK             (0xFF << I2C_CR2_NBYTES_SHIFT)
-
-/* NACK: NACK generation (slave mode) */
-#define I2C_CR2_NACK			(1 << 15)
-
-/* STOP: Stop generation (master mode) */
-#define I2C_CR2_STOP			(1 << 14)
-
-/* START: Start generation */
-#define I2C_CR2_START			(1 << 13)
-
-/* HEAD10R: 10-bit address header only read direction (master receiver mode) */
-#define I2C_CR2_HEAD10R			(1 << 12)
-
-/* ADD10: 10-bit addressing mode (master mode) */
-#define I2C_CR2_ADD10			(1 << 11)
-
-/* RD_WRN: Transfer direction (master mode) */
-#define I2C_CR2_RD_WRN			(1 << 10)
-
-#define I2C_CR2_SADD_7BIT_SHIFT         1
-#define I2C_CR2_SADD_10BIT_SHIFT        0
-#define I2C_CR2_SADD_7BIT_MASK          (0x7F << I2C_CR2_SADD_7BIT_SHIFT)
-#define I2C_CR2_SADD_10BIT_MASK         0x3FF
-
-/* --- I2Cx_OAR1 values ---------------------------------------------------- */
-
-/* OA1EN: Own Address 1 enable */
-#define I2C_OAR1_OA1EN_DISABLE		(0x0 << 15)
-#define I2C_OAR1_OA1EN_ENABLE		(0x1 << 15)
-
-/* OA1MODE Own Address 1 10-bit mode */
-#define I2C_OAR1_OA1MODE		(1 << 10)
-#define I2C_OAR1_OA1MODE_7BIT		0
-#define I2C_OAR1_OA1MODE_10BIT		1
-
-/* OA1[9:8]: Interface address */
-
-/* OA1[7:1]: Interface address */
-
-/* OA1[0]: Interface address */
-#define I2C_OAR1_OA1			(1 << 10)
-#define I2C_OAR1_OA1_7BIT		0
-#define I2C_OAR1_OA1_10BIT		1
-
-/* --- I2Cx_OAR2 values ---------------------------------------------------- */
-
-/* OA2EN: Own Address 2 enable */
-#define I2C_OAR2_OA2EN			(1 << 15)
-
-/* OA2MSK[2:0]: Own Address 2 masks */
-#define I2C_OAR2_OA2MSK_NO_MASK		(0x0 << 8)
-#define I2C_OAR2_OA2MSK_OA2_7_OA2_2	(0x1 << 8)
-#define I2C_OAR2_OA2MSK_OA2_7_OA2_3	(0x2 << 8)
-#define I2C_OAR2_OA2MSK_OA2_7_OA2_4	(0x3 << 8)
-#define I2C_OAR2_OA2MSK_OA2_7_OA2_5	(0x4 << 8)
-#define I2C_OAR2_OA2MSK_OA2_7_OA2_6	(0x5 << 8)
-#define I2C_OAR2_OA2MSK_OA2_7		(0x6 << 8)
-#define I2C_OAR2_OA2MSK_NO_CMP		(0x7 << 8)
-
-/* OA2[7:1]: Interface address */
-
-/* --- I2Cx_TIMINGR values ------------------------------------------------- */
-
-/* PRESC[3:0]: Timing prescaler (31,28) */
-#define I2C_TIMINGR_PRESC_SHIFT 28
-#define I2C_TIMINGR_PRESC_MASK (0xF << 28)
-
-/* SCLDEL[3:0]: Data setup time (23,20) */
-#define I2C_TIMINGR_SCLDEL_SHIFT 20
-#define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT)
-
-/* SDADEL[3:0]: Data hold time (19,16) */
-#define I2C_TIMINGR_SDADEL_SHIFT 16
-#define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT)
-
-/* SCLH[7:0]: SCL high period (master mode) (15,8) */
-#define I2C_TIMINGR_SCLH_SHIFT 8
-#define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT)
-
-/* SCLL[7:0]: SCL low period (master mode) (7,0) */
-#define I2C_TIMINGR_SCLL_SHIFT 0
-#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)
-
-/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */
-
-/* TEXTEN: Extended clock timeout enable */
-#define I2C_TIEMOUTR_TEXTEN		(1 << 31)
-
-/* XXX: Not clear yet. */
-/* TIMEOUTB[11:0]: Bus timeout B */
-
-/* TIMOUTEN: Clock timeout enable */
-#define I2C_TIEMOUTR_TIMOUTEN		(1 << 15)
-
-/* TIDLE: Idle clock timeout detection */
-#define I2C_TIEMOUTR_TIDLE_SCL_LOW	(0x0 << 12)
-#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH	(0x1 << 12)
-
-/* XXX: Not clear yet. */
-/* TIMEOUTA[11:0]: Bus Timeout A */
-
-/* --- I2Cx_ISR values ----------------------------------------------------- */
-
-/* Bits 31:24 Reserved, must be kept at reset value */
-
-/* XXX: Not clear yet. */
-/* ADDCODE[6:0]: Address match code (Slave mode) */
-
-/* DIR: Transfer direction (Slave mode) */
-#define I2C_ISR_DIR_READ		(0x1 << 16)
-#define I2C_ISR_DIR_WRITE		(0x0 << 16)
-
-/* BUSY: Bus busy */
-#define I2C_ISR_BUSY			(1 << 15)
-
-/* ALERT: SMBus alert */
-#define I2C_ISR_ALERT			(1 << 13)
-
-/* TIMEOUT: Timeout or tLOW detection flag */
-#define I2C_ISR_TIMEOUT			(1 << 12)
-
-/* PECERR: PEC Error in reception */
-#define I2C_ISR_PECERR			(1 << 11)
-
-/* OVR: Overrun/Underrun (slave mode) */
-#define I2C_ISR_OVR			(1 << 10)
-
-/* ARLO: Arbitration lost */
-#define I2C_ISR_ARLO			(1 << 9)
-
-/* BERR: Bus error */
-#define I2C_ISR_BERR			(1 << 8)
-
-/* TCR: Transfer Complete Reload */
-#define I2C_ISR_TCR			(1 << 7)
-
-/* TC: Transfer Complete (master mode) */
-#define I2C_ISR_TC			(1 << 6)
-
-/* STOPF: Stop detection flag */
-#define I2C_ISR_STOPF			(1 << 5)
-
-/* NACKF: Not Acknowledge received flag */
-#define I2C_ISR_NACKF			(1 << 4)
-
-/* ADDR: Address matched (slave mode) */
-#define I2C_ISR_ADDR			(1 << 3)
-
-/* RXNE: Receive data register not empty (receivers) */
-#define I2C_ISR_RXNE			(1 << 2)
-
-/* TXIS: Transmit interrupt status (transmitters) */
-#define I2C_ISR_TXIS			(1 << 1)
-
-/* TXE: Transmit data register empty (transmitters) */
-#define I2C_ISR_TXE			(1 << 0)
-
-/* --- I2Cx_ICR values ----------------------------------------------------- */
-
-/* ALERTCF: Alert flag clear */
-#define I2C_ICR_ALERTCF			(1 << 13)
-
-/* TIMOUTCF: Timeout detection flag clear */
-#define I2C_ICR_TIMOUTCF		(1 << 12)
-
-/* PECCF: PEC Error flag clear */
-#define I2C_ICR_PECCF			(1 << 11)
-
-/* OVRCF: Overrun/Underrun flag clear */
-#define I2C_ICR_OVRCF			(1 << 10)
-
-/* ARLOCF: Arbitration Lost flag clear */
-#define I2C_ICR_ARLOCF			(1 << 9)
-
-/* BERRCF: Bus error flag clear */
-#define I2C_ICR_BERRCF			(1 << 8)
-
-/* STOPCF: Stop detection flag clear */
-#define I2C_ICR_STOPCF			(1 << 5)
-
-/* NACKCF: Not Acknowledge flag clear */
-#define I2C_ICR_NACKCF			(1 << 4)
-
-/* ADDRCF: Address Matched flag clear */
-#define I2C_ICR_ADDRCF			(1 << 3)
-
-/* --- I2Cx_PECR values ---------------------------------------------------- */
-
-/* PEC[7:0] Packet error checking register  */
-
-/* --- I2C function prototypes---------------------------------------------- */
-
-BEGIN_DECLS
-
-void i2c_reset(uint32_t i2c);
-void i2c_peripheral_enable(uint32_t i2c);
-void i2c_peripheral_disable(uint32_t i2c);
-void i2c_send_start(uint32_t i2c);
-void i2c_send_stop(uint32_t i2c);
-void i2c_clear_stop(uint32_t i2c);
-void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave);
-void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave);
-void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq);
-void i2c_send_data(uint32_t i2c, uint8_t data);
-uint8_t i2c_get_data(uint32_t i2c);
-
-void i2c_enable_analog_filter(uint32_t i2c);
-void i2c_disable_analog_filter(uint32_t i2c);
-void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting);
-void i2c_set_prescaler(uint32_t i2c, uint8_t presc);
-void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time);
-void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time);
-void i2c_set_scl_high_period(uint32_t i2c, uint8_t period);
-void i2c_set_scl_low_period(uint32_t i2c, uint8_t period);
-void i2c_enable_stretching(uint32_t i2c);
-void i2c_disable_stretching(uint32_t i2c);
-void i2c_100khz_i2cclk8mhz(uint32_t i2c);
-void i2c_set_7bit_addr_mode(uint32_t i2c);
-void i2c_set_10bit_addr_mode(uint32_t i2c);
-void i2c_set_7bit_address(uint32_t i2c, uint8_t addr);
-void i2c_set_10bit_address(uint32_t i2c, uint16_t addr);
-void i2c_set_write_transfer_dir(uint32_t i2c);
-void i2c_set_read_transfer_dir(uint32_t i2c);
-void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes);
-uint8_t i2c_is_start(uint32_t i2c);
-void i2c_enable_autoend(uint32_t i2c);
-void i2c_disable_autoend(uint32_t i2c);
-uint8_t i2c_nack(uint32_t i2c);
-uint8_t i2c_busy(uint32_t i2c);
-uint8_t i2c_transmit_int_status(uint32_t i2c);
-uint8_t i2c_transfer_complete(uint32_t i2c);
-uint8_t i2c_received_data(uint32_t i2c);
-void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt);
-void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt);
-void i2c_enable_rxdma(uint32_t i2c);
-void i2c_disable_rxdma(uint32_t i2c);
-void i2c_enable_txdma(uint32_t i2c);
-void i2c_disable_txdma(uint32_t i2c);
-void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
-	       uint8_t size, uint8_t *data);
-void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
-	      uint8_t size, uint8_t *data);
-
-END_DECLS
-
-/**@}*/
+#include <libopencm3/stm32/common/i2c_common_v2.h>
 
 #endif
+
diff --git a/include/libopencm3/stm32/f4/i2c.h b/include/libopencm3/stm32/f4/i2c.h
index 02b6a99d..890d412f 100644
--- a/include/libopencm3/stm32/f4/i2c.h
+++ b/include/libopencm3/stm32/f4/i2c.h
@@ -31,7 +31,13 @@ LGPL License Terms @ref lgpl_license
 #ifndef LIBOPENCM3_I2C_H
 #define LIBOPENCM3_I2C_H
 
-#include <libopencm3/stm32/common/i2c_common_f24.h>
+#include <libopencm3/stm32/common/i2c_common_v1.h>
+
+/**@{*/
+
+#define I2C3				I2C3_BASE
+
+/**@}*/
 
 #endif
 
diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h
index 426af211..112ece2c 100644
--- a/include/libopencm3/stm32/i2c.h
+++ b/include/libopencm3/stm32/i2c.h
@@ -30,8 +30,14 @@
 #       include <libopencm3/stm32/f3/i2c.h>
 #elif defined(STM32F4)
 #       include <libopencm3/stm32/f4/i2c.h>
+#elif defined(STM32F7)
+#       include <libopencm3/stm32/f7/i2c.h>
+#elif defined(STM32L0)
+#       include <libopencm3/stm32/l0/i2c.h>
 #elif defined(STM32L1)
 #       include <libopencm3/stm32/l1/i2c.h>
+#elif defined(STM32L4)
+#       include <libopencm3/stm32/l4/i2c.h>
 #else
 #       error "stm32 family not defined."
 #endif
diff --git a/include/libopencm3/stm32/l1/i2c.h b/include/libopencm3/stm32/l1/i2c.h
index c2ed3f33..04ac1c75 100644
--- a/include/libopencm3/stm32/l1/i2c.h
+++ b/include/libopencm3/stm32/l1/i2c.h
@@ -31,7 +31,7 @@ LGPL License Terms @ref lgpl_license
 #ifndef LIBOPENCM3_I2C_H
 #define LIBOPENCM3_I2C_H
 
-#include <libopencm3/stm32/common/i2c_common_all.h>
+#include <libopencm3/stm32/common/i2c_common_v1.h>
 
 #endif
 
diff --git a/lib/stm32/common/i2c_common_all.c b/lib/stm32/common/i2c_common_v1.c
index 1af665fa..d8e53d1b 100644
--- a/lib/stm32/common/i2c_common_all.c
+++ b/lib/stm32/common/i2c_common_v1.c
@@ -65,6 +65,11 @@ void i2c_reset(uint32_t i2c)
 		rcc_periph_reset_pulse(RST_I2C3);
 		break;
 #endif
+#if defined(I2C4_BASE)
+	case I2C4:
+		rcc_periph_reset_pulse(RST_I2C4);
+		break;
+#endif
 	default:
 		break;
 	}
diff --git a/lib/stm32/common/i2c_common_v2.c b/lib/stm32/common/i2c_common_v2.c
new file mode 100644
index 00000000..01180cae
--- /dev/null
+++ b/lib/stm32/common/i2c_common_v2.c
@@ -0,0 +1,489 @@
+/** @addtogroup i2c_file
+ *
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/i2c.h>
+#include <libopencm3/stm32/rcc.h>
+
+/**@{*/
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Reset.
+ *
+ * The I2C peripheral and all its associated configuration registers are placed
+ * in the reset condition. The reset is effected via the RCC peripheral reset
+ * system.
+ *
+ * @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
+ */
+
+void i2c_reset(uint32_t i2c)
+{
+	switch (i2c) {
+	case I2C1:
+		rcc_periph_reset_pulse(RST_I2C1);
+		break;
+#if defined(I2C2_BASE)
+	case I2C2:
+		rcc_periph_reset_pulse(RST_I2C2);
+		break;
+#endif
+#if defined(I2C3_BASE)
+	case I2C3:
+		rcc_periph_reset_pulse(RST_I2C3);
+		break;
+#endif
+#if defined(I2C4_BASE)
+	case I2C4:
+		rcc_periph_reset_pulse(RST_I2C4);
+		break;
+#endif
+	default:
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Peripheral Enable.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+
+void i2c_peripheral_enable(uint32_t i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_PE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Peripheral Disable.
+ *
+ * This must not be reset while in Master mode until a communication has
+ * finished. In Slave mode, the peripheral is disabled only after communication
+ * has ended.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+
+void i2c_peripheral_disable(uint32_t i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_PE;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Send Start Condition.
+ *
+ * If in Master mode this will cause a restart condition to occur at the end of
+ * the current transmission. If in Slave mode, this will initiate a start
+ * condition when the current bus activity is completed.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+
+void i2c_send_start(uint32_t i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_START;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Send Stop Condition.
+ *
+ * After the current byte transfer this will initiate a stop condition if in
+ * Master mode, or simply release the bus if in Slave mode.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+
+void i2c_send_stop(uint32_t i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_STOP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Clear Stop Flag.
+ *
+ * Clear the "Send Stop" flag in the I2C config register
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+void i2c_clear_stop(uint32_t i2c)
+{
+	I2C_ICR(i2c) |= I2C_ICR_STOPCF;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
+ *
+ * This sets an address for Slave mode operation, in 7 bit form.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ * @param[in] slave Unsigned int8. Slave address 0...127.
+ */
+
+void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
+{
+	I2C_OAR1(i2c) = (uint16_t)(slave << 1);
+	I2C_OAR1(i2c) &= ~I2C_OAR1_OA1MODE;
+	I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
+ *
+ * This sets an address for Slave mode operation, in 10 bit form.
+ *
+ * @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ * @param[in] slave Unsigned int16. Slave address 0...1023.
+ */
+
+void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
+{
+	I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_OA1MODE | slave);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Send Data.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ * @param[in] data Unsigned int8. Byte to send.
+ */
+
+void i2c_send_data(uint32_t i2c, uint8_t data)
+{
+	I2C_TXDR(i2c) = data;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Get Data.
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+uint8_t i2c_get_data(uint32_t i2c)
+{
+	return I2C_RXDR(i2c) & 0xff;
+}
+
+void i2c_enable_analog_filter(uint32_t i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF;
+}
+
+void i2c_disable_analog_filter(uint32_t i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_ANFOFF;
+}
+
+void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting)
+{
+	I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting;
+}
+
+/* t_presc= (presc+1)*t_i2cclk */
+void i2c_set_prescaler(uint32_t i2c, uint8_t presc)
+{
+	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) |
+			   (presc << I2C_TIMINGR_PRESC_SHIFT);
+}
+
+void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time)
+{
+	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) |
+			   (s_time << I2C_TIMINGR_SCLDEL_SHIFT);
+}
+
+void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time)
+{
+	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) |
+			   (h_time << I2C_TIMINGR_SDADEL_SHIFT);
+}
+
+void i2c_set_scl_high_period(uint32_t i2c, uint8_t period)
+{
+	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) |
+			   (period << I2C_TIMINGR_SCLH_SHIFT);
+}
+
+void i2c_set_scl_low_period(uint32_t i2c, uint8_t period)
+{
+	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) |
+			   (period << I2C_TIMINGR_SCLL_SHIFT);
+}
+
+void i2c_enable_stretching(uint32_t i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH;
+}
+
+void i2c_disable_stretching(uint32_t i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH;
+}
+
+void i2c_100khz_i2cclk8mhz(uint32_t i2c)
+{
+	i2c_set_prescaler(i2c, 1);
+	i2c_set_scl_low_period(i2c, 0x13);
+	i2c_set_scl_high_period(i2c, 0xF);
+	i2c_set_data_hold_time(i2c, 0x2);
+	i2c_set_data_setup_time(i2c, 0x4);
+}
+
+void i2c_set_7bit_addr_mode(uint32_t i2c)
+{
+	I2C_CR2(i2c) &= ~I2C_CR2_ADD10;
+}
+
+void i2c_set_10bit_addr_mode(uint32_t i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_ADD10;
+}
+
+void i2c_set_7bit_address(uint32_t i2c, uint8_t addr)
+{
+	I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) |
+		       ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT);
+}
+
+void i2c_set_10bit_address(uint32_t i2c, uint16_t addr)
+{
+	I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) |
+		       ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT);
+}
+
+void i2c_set_write_transfer_dir(uint32_t i2c)
+{
+	I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN;
+}
+
+void i2c_set_read_transfer_dir(uint32_t i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_RD_WRN;
+}
+
+void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes)
+{
+	I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) |
+		       (n_bytes << I2C_CR2_NBYTES_SHIFT);
+}
+
+uint8_t i2c_is_start(uint32_t i2c)
+{
+	if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) {
+		return 1;
+	}
+
+	return 0;
+}
+
+void i2c_enable_autoend(uint32_t i2c)
+{
+	I2C_CR2(i2c) |= I2C_CR2_AUTOEND;
+}
+
+void i2c_disable_autoend(uint32_t i2c)
+{
+	I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND;
+}
+
+uint8_t i2c_nack(uint32_t i2c)
+{
+	if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) {
+		return 1;
+	}
+
+	return 0;
+}
+
+uint8_t i2c_busy(uint32_t i2c)
+{
+	if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) {
+		return 1;
+	}
+
+	return 0;
+}
+
+uint8_t i2c_transmit_int_status(uint32_t i2c)
+{
+	if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) {
+		return 1;
+	}
+
+	return 0;
+}
+
+uint8_t i2c_transfer_complete(uint32_t i2c)
+{
+	if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) {
+		return 1;
+	}
+
+	return 0;
+}
+
+uint8_t i2c_received_data(uint32_t i2c)
+{
+	if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) {
+		return 1;
+	}
+
+	return 0;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Enable Interrupt
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ * @param[in] interrupt Unsigned int32. Interrupt to enable.
+ */
+void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
+{
+	I2C_CR1(i2c) |= interrupt;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Disable Interrupt
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ * @param[in] interrupt Unsigned int32. Interrupt to disable.
+ */
+void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
+{
+	I2C_CR1(i2c) &= ~interrupt;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Enable reception DMA
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+void i2c_enable_rxdma(uint32_t i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_RXDMAEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Disable reception DMA
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+void i2c_disable_rxdma(uint32_t i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Enable transmission DMA
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+void i2c_enable_txdma(uint32_t i2c)
+{
+	I2C_CR1(i2c) |= I2C_CR1_TXDMAEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief I2C Disable transmission DMA
+ *
+ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
+ */
+void i2c_disable_txdma(uint32_t i2c)
+{
+	I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;
+}
+
+void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
+	       uint8_t *data)
+{
+	int wait;
+	int i;
+	while (i2c_busy(i2c) == 1);
+	while (i2c_is_start(i2c) == 1);
+	/*Setting transfer properties*/
+	i2c_set_bytes_to_transfer(i2c, size + 1);
+	i2c_set_7bit_address(i2c, (i2c_addr & 0x7F));
+	i2c_set_write_transfer_dir(i2c);
+	i2c_enable_autoend(i2c);
+	/*start transfer*/
+	i2c_send_start(i2c);
+
+	wait = true;
+	while (wait) {
+		if (i2c_transmit_int_status(i2c)) {
+			wait = false;
+		}
+		while (i2c_nack(i2c));
+	}
+
+	i2c_send_data(i2c, reg);
+	for (i = 0; i < size; i++) {
+		wait = true;
+		while (wait) {
+			if (i2c_transmit_int_status(i2c)) {
+				wait = false;
+			}
+			while (i2c_nack(i2c));
+		}
+		i2c_send_data(i2c, data[i]);
+	}
+}
+
+void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
+	      uint8_t *data)
+{
+	int wait;
+	int i;
+	while (i2c_busy(i2c) == 1);
+	while (i2c_is_start(i2c) == 1);
+	/*Setting transfer properties*/
+	i2c_set_bytes_to_transfer(i2c, 1);
+	i2c_set_7bit_address(i2c, i2c_addr);
+	i2c_set_write_transfer_dir(i2c);
+	i2c_disable_autoend(i2c);
+	/*start transfer*/
+	i2c_send_start(i2c);
+
+	wait = true;
+	while (wait) {
+		if (i2c_transmit_int_status(i2c)) {
+			wait = false;
+		}
+		while (i2c_nack(i2c)); /* Some error */
+	}
+	i2c_send_data(i2c, reg);
+
+	while (i2c_is_start(i2c) == 1);
+	/*Setting transfer properties*/
+	i2c_set_bytes_to_transfer(i2c, size);
+	i2c_set_7bit_address(i2c, i2c_addr);
+	i2c_set_read_transfer_dir(i2c);
+	i2c_enable_autoend(i2c);
+	/*start transfer*/
+	i2c_send_start(i2c);
+
+	for (i = 0; i < size; i++) {
+		while (i2c_received_data(i2c) == 0);
+		data[i] = i2c_get_data(i2c);
+	}
+}
+
+/**@}*/
diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile
index 466554d1..e7406726 100644
--- a/lib/stm32/f0/Makefile
+++ b/lib/stm32/f0/Makefile
@@ -36,7 +36,7 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 ARFLAGS		= rcs
 
 OBJS		= flash.o rcc.o usart.o dma.o rtc.o comparator.o crc.o \
-                  dac.o i2c.o iwdg.o pwr.o gpio.o timer.o adc.o desig.o
+                  dac.o iwdg.o pwr.o gpio.o timer.o adc.o desig.o
 
 OBJS            += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \
                    pwr_common_all.o iwdg_common_all.o rtc_common_l1f024.o \
@@ -46,6 +46,7 @@ OBJS            += gpio_common_all.o gpio_common_f0234.o crc_common_all.o \
 OBJS		+= adc_common_v2.o
 OBJS		+= crs_common_all.o
 OBJS		+= usart_common_v2.o
+OBJS		+= i2c_common_v2.o
 
 OBJS		+= usb.o usb_control.o usb_standard.o
 OBJS		+= st_usbfs_core.o st_usbfs_v2.o
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index 04f2cecd..3022d358 100755
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -40,7 +40,7 @@ OBJS		= adc.o adc_common_v1.o can.o desig.o flash.o gpio.o \
 OBJS		+= mac.o mac_stm32fxx7.o phy.o phy_ksz8051mll.o
 
 OBJS            += crc_common_all.o dac_common_all.o dma_common_l1f013.o \
-                   gpio_common_all.o i2c_common_all.o iwdg_common_all.o \
+                   gpio_common_all.o i2c_common_v1.o iwdg_common_all.o \
                    pwr_common_all.o spi_common_all.o spi_common_l1f124.o \
                    timer_common_all.o usart_common_all.o usart_common_f124.o \
                    rcc_common_all.o exti_common_all.o \
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index 397e77a0..10d0c808 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -38,7 +38,7 @@ ARFLAGS		= rcs
 OBJS		= gpio.o rcc.o desig.o
 
 OBJS            += crc_common_all.o dac_common_all.o dma_common_f24.o \
-                   gpio_common_all.o gpio_common_f0234.o i2c_common_all.o \
+                   gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \
                    iwdg_common_all.o rtc_common_l1f024.o spi_common_all.o \
                    spi_common_l1f124.o timer_common_all.o timer_common_f0234.o \
 		   timer_common_f24.o usart_common_all.o usart_common_f124.o \
diff --git a/lib/stm32/f2/i2c.c b/lib/stm32/f2/i2c.c
index ea0c99da..e5f6a415 100644
--- a/lib/stm32/f2/i2c.c
+++ b/lib/stm32/f2/i2c.c
@@ -29,5 +29,4 @@
  */
 
 #include <libopencm3/stm32/i2c.h>
-#include <libopencm3/stm32/common/i2c_common_all.h>
 
diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile
index e30847d0..a87e35c5 100644
--- a/lib/stm32/f3/Makefile
+++ b/lib/stm32/f3/Makefile
@@ -36,7 +36,7 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 
 ARFLAGS		= rcs
 
-OBJS		= rcc.o adc.o can.o i2c.o usart.o dma.o flash.o desig.o
+OBJS		= rcc.o adc.o can.o usart.o dma.o flash.o desig.o
 
 OBJS            += gpio_common_all.o gpio_common_f0234.o \
 		   dac_common_all.o crc_common_all.o \
@@ -45,6 +45,7 @@ OBJS            += gpio_common_all.o gpio_common_f0234.o \
 		   flash.o exti_common_all.o rcc_common_all.o spi_common_f03.o
 OBJS		+= adc_common_v2.o adc_common_v2_multi.o
 OBJS		+= usart_common_v2.o usart_common_all.o
+OBJS		+= i2c_common_v2.o
 
 OBJS		+= usb.o usb_control.o usb_standard.o
 OBJS		+= st_usbfs_core.o st_usbfs_v1.o
diff --git a/lib/stm32/f3/i2c.c b/lib/stm32/f3/i2c.c
index b5d39cfc..cc92957b 100644
--- a/lib/stm32/f3/i2c.c
+++ b/lib/stm32/f3/i2c.c
@@ -29,458 +29,4 @@
  */
 
 #include <libopencm3/stm32/i2c.h>
-#include <libopencm3/stm32/rcc.h>
 
-/**@{*/
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Reset.
- *
- * The I2C peripheral and all its associated configuration registers are placed
- * in the reset condition. The reset is effected via the RCC peripheral reset
- * system.
- *
- * @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
- */
-
-void i2c_reset(uint32_t i2c)
-{
-	switch (i2c) {
-	case I2C1:
-		rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST);
-		rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST);
-		break;
-	case I2C2:
-		rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST);
-		rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_I2C2RST);
-		break;
-	}
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Peripheral Enable.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-
-void i2c_peripheral_enable(uint32_t i2c)
-{
-	I2C_CR1(i2c) |= I2C_CR1_PE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Peripheral Disable.
- *
- * This must not be reset while in Master mode until a communication has
- * finished. In Slave mode, the peripheral is disabled only after communication
- * has ended.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-
-void i2c_peripheral_disable(uint32_t i2c)
-{
-	I2C_CR1(i2c) &= ~I2C_CR1_PE;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Send Start Condition.
- *
- * If in Master mode this will cause a restart condition to occur at the end of
- * the current transmission. If in Slave mode, this will initiate a start
- * condition when the current bus activity is completed.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-
-void i2c_send_start(uint32_t i2c)
-{
-	I2C_CR2(i2c) |= I2C_CR2_START;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Send Stop Condition.
- *
- * After the current byte transfer this will initiate a stop condition if in
- * Master mode, or simply release the bus if in Slave mode.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-
-void i2c_send_stop(uint32_t i2c)
-{
-	I2C_CR2(i2c) |= I2C_CR2_STOP;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Clear Stop Flag.
- *
- * Clear the "Send Stop" flag in the I2C config register
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-void i2c_clear_stop(uint32_t i2c)
-{
-	I2C_ICR(i2c) |= I2C_ICR_STOPCF;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Set the 7 bit Slave Address for the Peripheral.
- *
- * This sets an address for Slave mode operation, in 7 bit form.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- * @param[in] slave Unsigned int8. Slave address 0...127.
- */
-
-void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
-{
-	I2C_OAR1(i2c) = (uint16_t)(slave << 1);
-	I2C_OAR1(i2c) &= ~I2C_OAR1_OA1MODE;
-	I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Set the 10 bit Slave Address for the Peripheral.
- *
- * This sets an address for Slave mode operation, in 10 bit form.
- *
- * @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- * @param[in] slave Unsigned int16. Slave address 0...1023.
- */
-
-void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
-{
-	I2C_OAR1(i2c) = (uint16_t)(I2C_OAR1_OA1MODE | slave);
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Send Data.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- * @param[in] data Unsigned int8. Byte to send.
- */
-
-void i2c_send_data(uint32_t i2c, uint8_t data)
-{
-	I2C_TXDR(i2c) = data;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Get Data.
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-uint8_t i2c_get_data(uint32_t i2c)
-{
-	return I2C_RXDR(i2c) & 0xff;
-}
-
-void i2c_enable_analog_filter(uint32_t i2c)
-{
-	I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF;
-}
-
-void i2c_disable_analog_filter(uint32_t i2c)
-{
-	I2C_CR1(i2c) |= I2C_CR1_ANFOFF;
-}
-
-void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting)
-{
-	I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting;
-}
-
-/* t_presc= (presc+1)*t_i2cclk */
-void i2c_set_prescaler(uint32_t i2c, uint8_t presc)
-{
-	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) |
-			   (presc << I2C_TIMINGR_PRESC_SHIFT);
-}
-
-void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time)
-{
-	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) |
-			   (s_time << I2C_TIMINGR_SCLDEL_SHIFT);
-}
-
-void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time)
-{
-	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) |
-			   (h_time << I2C_TIMINGR_SDADEL_SHIFT);
-}
-
-void i2c_set_scl_high_period(uint32_t i2c, uint8_t period)
-{
-	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) |
-			   (period << I2C_TIMINGR_SCLH_SHIFT);
-}
-
-void i2c_set_scl_low_period(uint32_t i2c, uint8_t period)
-{
-	I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) |
-			   (period << I2C_TIMINGR_SCLL_SHIFT);
-}
-
-void i2c_enable_stretching(uint32_t i2c)
-{
-	I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH;
-}
-
-void i2c_disable_stretching(uint32_t i2c)
-{
-	I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH;
-}
-
-void i2c_100khz_i2cclk8mhz(uint32_t i2c)
-{
-	i2c_set_prescaler(i2c, 1);
-	i2c_set_scl_low_period(i2c, 0x13);
-	i2c_set_scl_high_period(i2c, 0xF);
-	i2c_set_data_hold_time(i2c, 0x2);
-	i2c_set_data_setup_time(i2c, 0x4);
-}
-
-void i2c_set_7bit_addr_mode(uint32_t i2c)
-{
-	I2C_CR2(i2c) &= ~I2C_CR2_ADD10;
-}
-
-void i2c_set_10bit_addr_mode(uint32_t i2c)
-{
-	I2C_CR2(i2c) |= I2C_CR2_ADD10;
-}
-
-void i2c_set_7bit_address(uint32_t i2c, uint8_t addr)
-{
-	I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) |
-		       ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT);
-}
-
-void i2c_set_10bit_address(uint32_t i2c, uint16_t addr)
-{
-	I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) |
-		       ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT);
-}
-
-void i2c_set_write_transfer_dir(uint32_t i2c)
-{
-	I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN;
-}
-
-void i2c_set_read_transfer_dir(uint32_t i2c)
-{
-	I2C_CR2(i2c) |= I2C_CR2_RD_WRN;
-}
-
-void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes)
-{
-	I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) |
-		       (n_bytes << I2C_CR2_NBYTES_SHIFT);
-}
-
-uint8_t i2c_is_start(uint32_t i2c)
-{
-	if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) {
-		return 1;
-	}
-
-	return 0;
-}
-
-void i2c_enable_autoend(uint32_t i2c)
-{
-	I2C_CR2(i2c) |= I2C_CR2_AUTOEND;
-}
-
-void i2c_disable_autoend(uint32_t i2c)
-{
-	I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND;
-}
-
-uint8_t i2c_nack(uint32_t i2c)
-{
-	if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) {
-		return 1;
-	}
-
-	return 0;
-}
-
-uint8_t i2c_busy(uint32_t i2c)
-{
-	if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) {
-		return 1;
-	}
-
-	return 0;
-}
-
-uint8_t i2c_transmit_int_status(uint32_t i2c)
-{
-	if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) {
-		return 1;
-	}
-
-	return 0;
-}
-
-uint8_t i2c_transfer_complete(uint32_t i2c)
-{
-	if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) {
-		return 1;
-	}
-
-	return 0;
-}
-
-uint8_t i2c_received_data(uint32_t i2c)
-{
-	if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) {
-		return 1;
-	}
-
-	return 0;
-}
-
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Enable Interrupt
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- * @param[in] interrupt Unsigned int32. Interrupt to enable.
- */
-void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
-{
-	I2C_CR1(i2c) |= interrupt;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Disable Interrupt
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- * @param[in] interrupt Unsigned int32. Interrupt to disable.
- */
-void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
-{
-	I2C_CR1(i2c) &= ~interrupt;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Enable reception DMA
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-void i2c_enable_rxdma(uint32_t i2c)
-{
-	I2C_CR1(i2c) |= I2C_CR1_RXDMAEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Disable reception DMA
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-void i2c_disable_rxdma(uint32_t i2c)
-{
-	I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Enable transmission DMA
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-void i2c_enable_txdma(uint32_t i2c)
-{
-	I2C_CR1(i2c) |= I2C_CR1_TXDMAEN;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief I2C Disable transmission DMA
- *
- * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
- */
-void i2c_disable_txdma(uint32_t i2c)
-{
-	I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;
-}
-
-void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
-	       uint8_t *data)
-{
-	int wait;
-	int i;
-	while (i2c_busy(i2c) == 1);
-	while (i2c_is_start(i2c) == 1);
-	/*Setting transfer properties*/
-	i2c_set_bytes_to_transfer(i2c, size + 1);
-	i2c_set_7bit_address(i2c, (i2c_addr & 0x7F));
-	i2c_set_write_transfer_dir(i2c);
-	i2c_enable_autoend(i2c);
-	/*start transfer*/
-	i2c_send_start(i2c);
-
-	wait = true;
-	while (wait) {
-		if (i2c_transmit_int_status(i2c)) {
-			wait = false;
-		}
-		while (i2c_nack(i2c));
-	}
-
-	i2c_send_data(i2c, reg);
-	for (i = 0; i < size; i++) {
-		wait = true;
-		while (wait) {
-			if (i2c_transmit_int_status(i2c)) {
-				wait = false;
-			}
-			while (i2c_nack(i2c));
-		}
-		i2c_send_data(i2c, data[i]);
-	}
-}
-
-void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
-	      uint8_t *data)
-{
-	int wait;
-	int i;
-	while (i2c_busy(i2c) == 1);
-	while (i2c_is_start(i2c) == 1);
-	/*Setting transfer properties*/
-	i2c_set_bytes_to_transfer(i2c, 1);
-	i2c_set_7bit_address(i2c, i2c_addr);
-	i2c_set_write_transfer_dir(i2c);
-	i2c_disable_autoend(i2c);
-	/*start transfer*/
-	i2c_send_start(i2c);
-
-	wait = true;
-	while (wait) {
-		if (i2c_transmit_int_status(i2c)) {
-			wait = false;
-		}
-		while (i2c_nack(i2c)); /* Some error */
-	}
-	i2c_send_data(i2c, reg);
-
-	while (i2c_is_start(i2c) == 1);
-	/*Setting transfer properties*/
-	i2c_set_bytes_to_transfer(i2c, size);
-	i2c_set_7bit_address(i2c, i2c_addr);
-	i2c_set_read_transfer_dir(i2c);
-	i2c_enable_autoend(i2c);
-	/*start transfer*/
-	i2c_send_start(i2c);
-
-	for (i = 0; i < size; i++) {
-		while (i2c_received_data(i2c) == 0);
-		data[i] = i2c_get_data(i2c);
-	}
-}
-
-/**@}*/
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index c1d9e1b8..6180c519 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -42,7 +42,7 @@ OBJS		= adc.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \
 		  rtc.o crypto.o
 
 OBJS            += crc_common_all.o dac_common_all.o dma_common_f24.o \
-                   gpio_common_all.o gpio_common_f0234.o i2c_common_all.o \
+                   gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \
                    iwdg_common_all.o pwr_common_all.o rtc_common_l1f024.o \
                    spi_common_all.o spi_common_l1f124.o timer_common_all.o \
                    timer_common_f0234.o timer_common_f24.o usart_common_all.o \
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index b645a1a1..ff0fd010 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -38,7 +38,7 @@ OBJS		= crc.o desig.o flash.o rcc.o usart.o dma.o lcd.o
 OBJS		+= crc_common_all.o dac_common_all.o
 OBJS		+= dma_common_l1f013.o
 OBJS		+= gpio_common_all.o gpio_common_f0234.o
-OBJS		+= i2c_common_all.o iwdg_common_all.o
+OBJS		+= i2c_common_v1.o iwdg_common_all.o
 OBJS		+= pwr_common_all.o pwr_common_l01.o rtc_common_l1f024.o
 OBJS		+= spi_common_all.o spi_common_l1f124.o timer_common_all.o
 OBJS		+= usart_common_all.o usart_common_f124.o