diff options
Diffstat (limited to 'include/libopencm3/stm32/l0/timer.h')
| -rw-r--r-- | include/libopencm3/stm32/l0/timer.h | 166 |
1 files changed, 0 insertions, 166 deletions
diff --git a/include/libopencm3/stm32/l0/timer.h b/include/libopencm3/stm32/l0/timer.h index 3d6323e2..98772811 100644 --- a/include/libopencm3/stm32/l0/timer.h +++ b/include/libopencm3/stm32/l0/timer.h @@ -96,174 +96,8 @@ LGPL License Terms @ref lgpl_license #define TIM22_OR_TI1_RMP_COMP2_OUT (1 << TIM22_OR_TI1_RMP_SHIFT) #define TIM22_OR_TI1_RMP_COMP1_OUT (2 << TIM22_OR_TI1_RMP_SHIFT) -/* --- LPTIM (low power timer) ------------------------------------------- */ - -#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) -#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) -#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) -#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) -#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) -#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) -#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) -#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) - -#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) -#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) -#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE) -#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) -#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE) -#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) -#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) -#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) - -/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register -@{*/ -#define LPTIM_ISR_CMPM (1 << 0) -#define LPTIM_ISR_ARRM (1 << 1) -#define LPTIM_ISR_EXTTRIG (1 << 2) -#define LPTIM_ISR_CMPOK (1 << 3) -#define LPTIM_ISR_ARROK (1 << 4) -#define LPTIM_ISR_UP (1 << 5) -#define LPTIM_ISR_DOWN (1 << 6) -/**@}*/ - -/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register -@{*/ -#define LPTIM_ICR_CMPMCF (1 << 0) -#define LPTIM_ICR_ARRMCF (1 << 1) -#define LPTIM_ICR_EXTTRIGCF (1 << 2) -#define LPTIM_ICR_CMPOKCF (1 << 3) -#define LPTIM_ICR_ARROKCF (1 << 4) -#define LPTIM_ICR_UPCF (1 << 5) -#define LPTIM_ICR_DOWNCF (1 << 6) -/**@}*/ - -/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register -@{*/ -#define LPTIM_IER_CMPMIE (1 << 0) -#define LPTIM_IER_ARRMIE (1 << 1) -#define LPTIM_IER_EXTTRIGIE (1 << 2) -#define LPTIM_IER_CMPOKIE (1 << 3) -#define LPTIM_IER_ARROKIE (1 << 4) -#define LPTIM_IER_UPIE (1 << 5) -#define LPTIM_IER_DOWNIE (1 << 6) -/**@}*/ - -/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register -@{*/ - -/** CKSEL: Select internal (0) or external clock source (1) **/ -#define LPTIM_CFGR_CKSEL (1 << 0) - -#define LPTIM_CFGR_CKPOL_SHIFT 1 -#define LPTIM_CFGR_CKPOL_MASK 0x03 -#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) -/** @defgroup lptim_cfgr_ckpol LPTIM_CFGR CKPOL Clock Polarity -@{*/ -#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_CKFLT_SHIFT 3 -#define LPTIM_CFGR_CKFLT_MASK 0x03 -#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) -/** @defgroup lptim_cfgr_ckflt LPTIM_CFGR CKFLT Configurable digital filter for external clock -@{*/ -#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_TRGFLT_SHIFT 6 -#define LPTIM_CFGR_TRGFLT_MASK 0x03 -#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) -/** @defgroup lptim_cfgr_trgflt LPTIM_CFGR TRGFLT Configurable digital filter for trigger -@{*/ -#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_PRESC_SHIFT 9 -#define LPTIM_CFGR_PRESC_MASK 0x07 -#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) -/** @defgroup lptim_cfgr_presc LPTIM_CFGR PRESC Clock prescaler -@{*/ -#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_TRIGSEL_SHIFT 13 -#define LPTIM_CFGR_TRIGSEL_MASK 0x07 -#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -/** @defgroup lptim_cfgr_trigsel LPTIM_CFGR TRIGSEL Trigger selector -@{*/ -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) -/* 5 is reserved */ -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -/**@}*/ - -#define LPTIM_CFGR_TRIGEN_SHIFT 17 -#define LPTIM_CFGR_TRIGSEL_MASK 0x07 -#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) -/** @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity -@{*/ -#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) -/**@}*/ - -/** TIMOUT: Timeout enable **/ -#define LPTIM_CFGR_TIMOUT (1 << 19) - -/** WAVE: Waveform shape **/ -#define LPTIM_CFGR_WAVE (1 << 20) - -/** WAVPOL: Waveform shape polarity **/ -#define LPTIM_CFGR_WAVPOL (1 << 21) - -/** PRELOAD: Register update mode **/ -#define LPTIM_CFGR_PRELOAD (1 << 22) - -/** COUNTMODE: Counter mode enable **/ -#define LPTIM_CFGR_COUNTMODE (1 << 23) - -/** ENC: Encoder mode enable **/ -#define LPTIM_CFGR_ENC (1 << 24) - /**@}*/ -/** @defgroup lptim_cr LPTIM_CR Control Register -@{*/ - -/** ENABLE: Counter enable **/ -#define LPTIM_CR_ENABLE (1 << 0) - -/** SNGSTRT: Start in Single Mode **/ -#define LPTIM_CR_SNGSTRT (1 << 1) - -/** CNGSTRT: Start in Continuous Mode **/ -#define LPTIM_CR_CNTSTRT (1 << 2) - -/**@}*/ - - #endif /**@}*/ |