diff options
Diffstat (limited to 'include/libopencm3/stm32/l0')
| -rw-r--r-- | include/libopencm3/stm32/l0/dma.h | 1 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/doc-stm32l0.h | 2 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/exti.h | 1 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/gpio.h | 3 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/lptimer.h | 46 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/rcc.h | 63 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/syscfg.h | 1 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/timer.h | 120 | ||||
| -rw-r--r-- | include/libopencm3/stm32/l0/usart.h | 4 |
9 files changed, 99 insertions, 142 deletions
diff --git a/include/libopencm3/stm32/l0/dma.h b/include/libopencm3/stm32/l0/dma.h index b39d0610..344f4d4b 100644 --- a/include/libopencm3/stm32/l0/dma.h +++ b/include/libopencm3/stm32/l0/dma.h @@ -32,6 +32,7 @@ #define LIBOPENCM3_DMA_H #include <libopencm3/stm32/common/dma_common_l1f013.h> +#include <libopencm3/stm32/common/dma_common_csel.h> #endif diff --git a/include/libopencm3/stm32/l0/doc-stm32l0.h b/include/libopencm3/stm32/l0/doc-stm32l0.h index 2d01ca01..0813bcd9 100644 --- a/include/libopencm3/stm32/l0/doc-stm32l0.h +++ b/include/libopencm3/stm32/l0/doc-stm32l0.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32L0 +/** @page libopencm3 STM32L0 @version 1.0.0 diff --git a/include/libopencm3/stm32/l0/exti.h b/include/libopencm3/stm32/l0/exti.h index b2af19b2..c1d90156 100644 --- a/include/libopencm3/stm32/l0/exti.h +++ b/include/libopencm3/stm32/l0/exti.h @@ -37,5 +37,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/l0/gpio.h b/include/libopencm3/stm32/l0/gpio.h index a1b48990..da2f420d 100644 --- a/include/libopencm3/stm32/l0/gpio.h +++ b/include/libopencm3/stm32/l0/gpio.h @@ -57,7 +57,8 @@ @{*/ #define GPIO_OSPEED_LOW 0x0 #define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x3 +#define GPIO_OSPEED_HIGH 0x2 +#define GPIO_OSPEED_VERYHIGH 0x3 /**@}*/ /*****************************************************************************/ diff --git a/include/libopencm3/stm32/l0/lptimer.h b/include/libopencm3/stm32/l0/lptimer.h new file mode 100644 index 00000000..e6d99d8c --- /dev/null +++ b/include/libopencm3/stm32/l0/lptimer.h @@ -0,0 +1,46 @@ +/** @defgroup lptimer_defines LPTIM Defines + * + * @ingroup STM32L0xx_defines + * + * @brief <b>libopencm3 Defined Constants and Types for the STM32L0xx Low Power Timer</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_LPTIMER_H +#define LIBOPENCM3_LPTIMER_H +/**@{*/ + +#include <libopencm3/stm32/common/lptimer_common_all.h> + +/** @defgroup lptim_reg_base Low Power Timer register base addresses +@{*/ +#define LPTIM1 LPTIM1_BASE +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index ace255b1..59194425 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -142,14 +142,17 @@ #define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO_MASK 0xf -/* PLL Output division selection */ +/** @defgroup rcc_cfgr_pdf PLLDIV PLL division factor + @{*/ #define RCC_CFGR_PLLDIV_DIV2 0x1 #define RCC_CFGR_PLLDIV_DIV3 0x2 #define RCC_CFGR_PLLDIV_DIV4 0x3 +/**@}*/ #define RCC_CFGR_PLLDIV_SHIFT 22 #define RCC_CFGR_PLLDIV_MASK 0x3 -/* PLLMUL: PLL multiplication factor */ +/** @defgroup rcc_cfgr_pmf PLLMUL PLL multiplication factor + @{*/ #define RCC_CFGR_PLLMUL_MUL3 0x0 #define RCC_CFGR_PLLMUL_MUL4 0x1 #define RCC_CFGR_PLLMUL_MUL6 0x2 @@ -159,6 +162,7 @@ #define RCC_CFGR_PLLMUL_MUL24 0x6 #define RCC_CFGR_PLLMUL_MUL32 0x7 #define RCC_CFGR_PLLMUL_MUL48 0x8 +/**@}*/ #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL_MASK 0xf @@ -171,24 +175,32 @@ #define RCC_CFGR_STOPWUCK_HSI16 (1<<15) /* PPRE2: APB high-speed prescaler (APB2) */ +/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors +@{*/ #define RCC_CFGR_PPRE2_NODIV 0x0 #define RCC_CFGR_PPRE2_DIV2 0x4 #define RCC_CFGR_PPRE2_DIV4 0x5 #define RCC_CFGR_PPRE2_DIV8 0x6 #define RCC_CFGR_PPRE2_DIV16 0x7 +/**@}*/ #define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE2_SHIFT 11 /* PPRE1: APB low-speed prescaler (APB1) */ +/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors +@{*/ #define RCC_CFGR_PPRE1_NODIV 0x0 #define RCC_CFGR_PPRE1_DIV2 0x4 #define RCC_CFGR_PPRE1_DIV4 0x5 #define RCC_CFGR_PPRE1_DIV8 0x6 #define RCC_CFGR_PPRE1_DIV16 0x7 +/**@}*/ #define RCC_CFGR_PPRE1_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 8 /* HPRE: AHB prescaler */ +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors +@{*/ #define RCC_CFGR_HPRE_NODIV 0x0 #define RCC_CFGR_HPRE_DIV2 0x8 #define RCC_CFGR_HPRE_DIV4 0x9 @@ -198,6 +210,7 @@ #define RCC_CFGR_HPRE_DIV128 0xd #define RCC_CFGR_HPRE_DIV256 0xe #define RCC_CFGR_HPRE_DIV512 0xf +/**@}*/ #define RCC_CFGR_HPRE_MASK 0xf #define RCC_CFGR_HPRE_SHIFT 4 @@ -262,17 +275,18 @@ #define RCC_IOPPRSTR_IOPBRST (1<<1) #define RCC_IOPPRSTR_IOPARST (1<<0) -/* --- RCC_AHBRSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values +@{*/ #define RCC_AHBRSTR_CRYPRST (1 << 24) #define RCC_AHBRSTR_RNGRST (1 << 20) #define RCC_AHBRSTR_TSCRST (1 << 16) #define RCC_AHBRSTR_CRCRST (1 << 12) #define RCC_AHBRSTR_MIFRST (1 << 8) #define RCC_AHBRSTR_DMARST (1 << 0) +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_DBGRST (1 << 22) #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) @@ -280,9 +294,10 @@ #define RCC_APB2RSTR_TIM22RST (1 << 5) #define RCC_APB2RSTR_TIM21RST (1 << 2) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_LPTIM1RST (1 << 31) #define RCC_APB1RSTR_I2C3RST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) @@ -302,6 +317,7 @@ #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ /* --- RCC_IOPENR - GPIO clock enable register */ @@ -312,11 +328,7 @@ #define RCC_IOPENR_IOPBEN (1<<1) #define RCC_IOPENR_IOPAEN (1<<0) -/* --- RCC_AHBENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values -@ingroup STM32L0xx_rcc_defines - +/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values @{*/ #define RCC_AHBENR_CRYPEN (1 << 24) #define RCC_AHBENR_RNGEN (1 << 20) @@ -324,13 +336,9 @@ #define RCC_AHBENR_CRCEN (1 << 12) #define RCC_AHBENR_MIFEN (1 << 8) #define RCC_AHBENR_DMAEN (1 << 0) -/*@}*/ - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@ingroup STM32L0xx_rcc_defines +/**@}*/ +/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values @{*/ #define RCC_APB2ENR_DBGEN (1 << 22) #define RCC_APB2ENR_USART1EN (1 << 14) @@ -340,13 +348,9 @@ #define RCC_APB2ENR_TIM22EN (1 << 5) #define RCC_APB2ENR_TIM21EN (1 << 2) #define RCC_APB2ENR_SYSCFGEN (1 << 0) -/*@}*/ - -/* --- RCC_APB1ENR values -------------------------------------------------- */ +/**@}*/ /** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@ingroup STM32L0xx_rcc_defines - @{*/ #define RCC_APB1ENR_LPTIM1EN (1 << 31) #define RCC_APB1ENR_DACEN (1 << 29) @@ -366,7 +370,7 @@ #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) -/*@}*/ +/**@}*/ /* --- RCC_IOPSMENR - GPIO Clock enable in sleep mode */ @@ -693,6 +697,15 @@ void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); +void rcc_set_msi_range(uint32_t msi_range); + +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel); + +void rcc_set_lptim1_sel(uint32_t lptim1_sel); +void rcc_set_lpuart1_sel(uint32_t lpupart1_sel); +void rcc_set_usart1_sel(uint32_t usart1_sel); +void rcc_set_usart2_sel(uint32_t usart2_sel); + END_DECLS /**@}*/ diff --git a/include/libopencm3/stm32/l0/syscfg.h b/include/libopencm3/stm32/l0/syscfg.h index 1ae0a947..767ddf44 100644 --- a/include/libopencm3/stm32/l0/syscfg.h +++ b/include/libopencm3/stm32/l0/syscfg.h @@ -111,6 +111,7 @@ /* SYSCFG_EXTICR Values -- --------------------------------------------------*/ +#define SYSCFG_EXTICR_FIELDSIZE 4 #define SYSCFG_EXTICR_GPIOA 0 #define SYSCFG_EXTICR_GPIOB 1 #define SYSCFG_EXTICR_GPIOC 2 diff --git a/include/libopencm3/stm32/l0/timer.h b/include/libopencm3/stm32/l0/timer.h index c2ed35a8..98772811 100644 --- a/include/libopencm3/stm32/l0/timer.h +++ b/include/libopencm3/stm32/l0/timer.h @@ -37,7 +37,9 @@ LGPL License Terms @ref lgpl_license #include <libopencm3/stm32/common/timer_common_all.h> -/* Timer 2/21/22 option register (TIMx_OR) */ +/**@{*/ + +/** Timer 2/21/22 option register (TIMx_OR) */ #define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) @@ -94,118 +96,8 @@ LGPL License Terms @ref lgpl_license #define TIM22_OR_TI1_RMP_COMP2_OUT (1 << TIM22_OR_TI1_RMP_SHIFT) #define TIM22_OR_TI1_RMP_COMP1_OUT (2 << TIM22_OR_TI1_RMP_SHIFT) -/* --- LPTIM (low power timer) ------------------------------------------- */ - -#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) -#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) -#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) -#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) -#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) -#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) -#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) -#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) - -#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) -#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) -#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE) -#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) -#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE) -#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) -#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) -#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) - -#define LPTIM_ISR_CMPM (1 << 0) -#define LPTIM_ISR_ARRM (1 << 1) -#define LPTIM_ISR_EXTTRIG (1 << 2) -#define LPTIM_ISR_CMPOK (1 << 3) -#define LPTIM_ISR_ARROK (1 << 4) -#define LPTIM_ISR_UP (1 << 5) -#define LPTIM_ISR_DOWN (1 << 6) - -#define LPTIM_ICR_CMPMCF (1 << 0) -#define LPTIM_ICR_ARRMCF (1 << 1) -#define LPTIM_ICR_EXTTRIGCF (1 << 2) -#define LPTIM_ICR_CMPOKCF (1 << 3) -#define LPTIM_ICR_ARROKCF (1 << 4) -#define LPTIM_ICR_UPCF (1 << 5) -#define LPTIM_ICR_DOWNCF (1 << 6) - -#define LPTIM_IER_CMPMIE (1 << 0) -#define LPTIM_IER_ARRMIE (1 << 1) -#define LPTIM_IER_EXTTRIGIE (1 << 2) -#define LPTIM_IER_CMPOKIE (1 << 3) -#define LPTIM_IER_ARROKIE (1 << 4) -#define LPTIM_IER_UPIE (1 << 5) -#define LPTIM_IER_DOWNIE (1 << 6) - -#define LPTIM_CFGR_CKSEL (1 << 0) - -#define LPTIM_CFGR_CKPOL_SHIFT 1 -#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) - -#define LPTIM_CFGR_CKFLT_SHIFT 3 -#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) - -#define LPTIM_CFGR_TRGFLT_SHIFT 6 -#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) - -#define LPTIM_CFGR_PRESC_SHIFT 9 -#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) - -#define LPTIM_CFGR_TRIGSEL_SHIFT 13 -#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) -/* 5 is reserved */ -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) - -#define LPTIM_CFGR_TRIGEN_SHIFT 17 -#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) - -#define LPTIM_CFGR_TIMOUT (1 << 19) - -#define LPTIM_CFGR_WAVE (1 << 20) - -#define LPTIM_CFGR_WAVPOL (1 << 21) - -#define LPTIM_CFGR_PRELOAD (1 << 22) - -#define LPTIM_CFGR_COUNTMODE (1 << 23) - -#define LPTIM_CFGR_ENC (1 << 24) - -#define LPTIM_CR_ENABLE (1 << 0) - -#define LPTIM_CR_SNGSTRT (1 << 1) - -#define LPTIM_CR_CNTSTRT (1 << 2) +/**@}*/ #endif + +/**@}*/ diff --git a/include/libopencm3/stm32/l0/usart.h b/include/libopencm3/stm32/l0/usart.h index d3777707..6ab49067 100644 --- a/include/libopencm3/stm32/l0/usart.h +++ b/include/libopencm3/stm32/l0/usart.h @@ -30,8 +30,9 @@ #include <libopencm3/stm32/common/usart_common_all.h> #include <libopencm3/stm32/common/usart_common_v2.h> +/**@{*/ + /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ @@ -46,4 +47,5 @@ BEGIN_DECLS END_DECLS +/**@}*/ #endif |