diff options
Diffstat (limited to 'cm3cpp/timer.cpp')
| -rw-r--r-- | cm3cpp/timer.cpp | 636 |
1 files changed, 273 insertions, 363 deletions
diff --git a/cm3cpp/timer.cpp b/cm3cpp/timer.cpp index e2711e9..b494dd2 100644 --- a/cm3cpp/timer.cpp +++ b/cm3cpp/timer.cpp @@ -29,31 +29,38 @@ namespace cm3cpp { namespace tim { +/** Helper for make explicit opencm3 defined constants conversions */ +template<typename T> +constexpr uint32_t to_u32(T t) +{ + return static_cast<uint32_t>(t); +} + // 1,2,3,4,5,6,7,8,9,10,11,12,13,14 auto Timer::enable_counter() -> Result { - TIM_CR1(_timer) |= TIM_CR1_CEN; + TIM_CR1(_timer) |= to_u32(TIM_CR1_CEN); return OK; } // 1,2,3,4,5,6,7,8,9,10,11,12,13,14 auto Timer::disable_counter() -> Result { - TIM_CR1(_timer) &= ~TIM_CR1_CEN; + TIM_CR1(_timer) &= ~to_u32(TIM_CR1_CEN); return OK; } // 1,2,3,4,5,6,7,8,9,10,11,12,13,14 auto Timer::enable_update_event_generation() -> Result { - TIM_CR1(_timer) &= ~TIM_CR1_UDIS; + TIM_CR1(_timer) &= ~to_u32(TIM_CR1_UDIS); return OK; } // 1,2,3,4,5,6,7,8,9,10,11,12,13,14 auto Timer::disable_update_event_generation() -> Result { - TIM_CR1(_timer) |= TIM_CR1_UDIS; + TIM_CR1(_timer) |= to_u32(TIM_CR1_UDIS); return OK; } @@ -62,7 +69,7 @@ auto Timer::set_update_event_source(UevSource source) -> Result { switch (source) { case COUNTER_OVERFLOW_AND_UG: - TIM_CR1(_timer) &= ~TIM_CR1_URS; + TIM_CR1(_timer) &= ~to_u32(TIM_CR1_URS); break; case COUNTER_OVERFLOW: TIM_CR1(_timer) |= TIM_CR1_URS; @@ -80,7 +87,7 @@ auto Timer::set_counter_mode(CounterMode mode) -> Result TIM_CR1(_timer) |= TIM_CR1_OPM; break; case CONTINUOUS: - TIM_CR1(_timer) &= ~TIM_CR1_OPM; + TIM_CR1(_timer) &= ~to_u32(TIM_CR1_OPM); break; } @@ -97,7 +104,7 @@ auto Timer::set_counter_direction(CounterDirection dir) -> Result switch (dir) { case UP: - TIM_CR1(_timer) &= ~TIM_CR1_DIR_DOWN; + TIM_CR1(_timer) &= ~to_u32(TIM_CR1_DIR_DOWN); break; case DOWN: TIM_CR1(_timer) |= TIM_CR1_DIR_DOWN; @@ -116,32 +123,29 @@ auto Timer::set_alignment(Alignment alignment) -> Result } bool counter_enable = TIM_CR1(_timer) & TIM_CR1_CEN; + const auto cms_clear_mask = TIM_CR1(_timer) & ~to_u32(TIM_CR1_CMS_MASK); switch (alignment) { case EDGE: - TIM_CR1(_timer) = - (TIM_CR1(_timer) & ~TIM_CR1_CMS_MASK) | TIM_CR1_CMS_EDGE; + TIM_CR1(_timer) = cms_clear_mask | TIM_CR1_CMS_EDGE; return OK; case CENTER_DOWN: if (counter_enable) { return USAGE_ERROR; } - TIM_CR1(_timer) = - (TIM_CR1(_timer) & ~TIM_CR1_CMS_MASK) | TIM_CR1_CMS_CENTER_1; + TIM_CR1(_timer) = cms_clear_mask | TIM_CR1_CMS_CENTER_1; return OK; case CENTER_UP: if (counter_enable) { return USAGE_ERROR; } - TIM_CR1(_timer) = - (TIM_CR1(_timer) & ~TIM_CR1_CMS_MASK) | TIM_CR1_CMS_CENTER_2; + TIM_CR1(_timer) = cms_clear_mask | TIM_CR1_CMS_CENTER_2; return OK; case CENTER_UP_DOWN: if (counter_enable) { return USAGE_ERROR; } - TIM_CR1(_timer) = - (TIM_CR1(_timer) & ~TIM_CR1_CMS_MASK) | TIM_CR1_CMS_CENTER_3; + TIM_CR1(_timer) = cms_clear_mask | TIM_CR1_CMS_CENTER_3; return OK; } @@ -158,7 +162,7 @@ auto Timer::enable_autoreload_preload() -> Result // 1,2,3,4,5,6,7,8,9,10,11,12,13,14 auto Timer::disable_autoreload_preload() -> Result { - TIM_CR1(_timer) &= ~TIM_CR1_ARPE; + TIM_CR1(_timer) &= ~to_u32(TIM_CR1_ARPE); return OK; } @@ -169,18 +173,18 @@ auto Timer::set_clock_division(ClockDivision div) -> Result return USAGE_ERROR; } + const auto ckd_ck_int_clear_mask = + TIM_CR1(_timer) & ~to_u32(TIM_CR1_CKD_CK_INT_MASK); + switch (div) { case TIMER_CLOCK_MUL_1: - TIM_CR1(_timer) = - (TIM_CR1(_timer) & ~TIM_CR1_CKD_CK_INT_MASK) | TIM_CR1_CKD_CK_INT; + TIM_CR1(_timer) = ckd_ck_int_clear_mask | TIM_CR1_CKD_CK_INT; break; case TIMER_CLOCK_MUL_2: - TIM_CR1(_timer) = (TIM_CR1(_timer) & ~TIM_CR1_CKD_CK_INT_MASK) | - TIM_CR1_CKD_CK_INT_MUL_2; + TIM_CR1(_timer) = ckd_ck_int_clear_mask | TIM_CR1_CKD_CK_INT_MUL_2; break; case TIMER_CLOCK_MUL_4: - TIM_CR1(_timer) = (TIM_CR1(_timer) & ~TIM_CR1_CKD_CK_INT_MASK) | - TIM_CR1_CKD_CK_INT_MUL_4; + TIM_CR1(_timer) = ckd_ck_int_clear_mask | TIM_CR1_CKD_CK_INT_MUL_4; break; } @@ -190,38 +194,32 @@ auto Timer::set_clock_division(ClockDivision div) -> Result // 9,12 auto Timer::set_master_mode(MasterMode mode) -> Result { + const auto mms_clear_mask = TIM_CR2(_timer) & ~to_u32(TIM_CR2_MMS_MASK); + switch (mode) { case MASTER_RESET: - TIM_CR2(_timer) = - (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | TIM_CR2_MMS_RESET; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_RESET; break; case ENABLE: - TIM_CR2(_timer) = - (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | TIM_CR2_MMS_ENABLE; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_ENABLE; break; case UPDATE: - TIM_CR2(_timer) = - (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | TIM_CR2_MMS_UPDATE; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_UPDATE; break; case COMPARE_PULSE: - TIM_CR2(_timer) = - (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | TIM_CR2_MMS_COMPARE_PULSE; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_COMPARE_PULSE; break; case COMPARE_OC1REF: - TIM_CR2(_timer) = (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | - TIM_CR2_MMS_COMPARE_OC1REF; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_COMPARE_OC1REF; break; case COMPARE_OC2REF: - TIM_CR2(_timer) = (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | - TIM_CR2_MMS_COMPARE_OC2REF; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_COMPARE_OC2REF; break; case COMPARE_OC3REF: - TIM_CR2(_timer) = (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | - TIM_CR2_MMS_COMPARE_OC3REF; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_COMPARE_OC3REF; break; case COMPARE_OC4REF: - TIM_CR2(_timer) = (TIM_CR2(_timer) & ~TIM_CR2_MMS_MASK) | - TIM_CR2_MMS_COMPARE_OC4REF; + TIM_CR2(_timer) = mms_clear_mask | TIM_CR2_MMS_COMPARE_OC4REF; break; } @@ -231,29 +229,26 @@ auto Timer::set_master_mode(MasterMode mode) -> Result // 9,12 auto Timer::set_slave_mode(SlaveMode mode) -> Result { + const auto clear_sms_mask = TIM_SMCR(_timer) & ~to_u32(TIM_SMCR_SMS_MASK); + switch (mode) { case DISABLED: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_SMS_MASK) | TIM_SMCR_SMS_OFF; + TIM_SMCR(_timer) = clear_sms_mask | TIM_SMCR_SMS_OFF; break; case SLAVE_RESET: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_SMS_MASK) | TIM_SMCR_SMS_RM; + TIM_SMCR(_timer) = clear_sms_mask | TIM_SMCR_SMS_RM; break; case GATED: if (TIM_SMCR(_timer) & TIM_SMCR_TS_TI1F_ED) { return USAGE_ERROR; } - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_SMS_MASK) | TIM_SMCR_SMS_GM; + TIM_SMCR(_timer) = clear_sms_mask | TIM_SMCR_SMS_GM; break; case TRIGGER: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_SMS_MASK) | TIM_SMCR_SMS_TM; + TIM_SMCR(_timer) = clear_sms_mask | TIM_SMCR_SMS_TM; break; case EXTERNAL_CLOCK: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_SMS_MASK) | TIM_SMCR_SMS_ECM1; + TIM_SMCR(_timer) = clear_sms_mask | TIM_SMCR_SMS_ECM1; break; } @@ -263,34 +258,29 @@ auto Timer::set_slave_mode(SlaveMode mode) -> Result // 9,12 auto Timer::set_trigger(Trigger trigger) -> Result { + const auto clear_ts_mask = TIM_SMCR(_timer) & ~to_u32(TIM_SMCR_TS_MASK); + switch (trigger) { case INTERNAL_TRIGGER_0: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_ITR0; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_ITR0; break; case INTERNAL_TRIGGER_1: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_ITR1; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_ITR1; break; case INTERNAL_TRIGGER_2: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_ITR2; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_ITR2; break; case INTERNAL_TRIGGER_3: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_ITR3; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_ITR3; break; case EDGE_DETECTOR: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_TI1F_ED; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_TI1F_ED; break; case FILTERED_TIMER_INPUT_1: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_TI1FP1; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_TI1FP1; break; case FILTERED_TIMER_INPUT_2: - TIM_SMCR(_timer) = - (TIM_SMCR(_timer) & ~TIM_SMCR_TS_MASK) | TIM_SMCR_TS_TI2FP2; + TIM_SMCR(_timer) = clear_ts_mask | TIM_SMCR_TS_TI2FP2; break; } @@ -307,7 +297,7 @@ auto Timer::enable_master_slave_mode() -> Result // 9,12 auto Timer::disable_master_slave_mode() -> Result { - TIM_SMCR(_timer) &= ~TIM_SMCR_MSM; + TIM_SMCR(_timer) &= ~to_u32(TIM_SMCR_MSM); return OK; } @@ -321,7 +311,7 @@ auto Timer::enable_update_interrupt() -> Result // 9,12 auto Timer::disable_update_interrupt() -> Result { - TIM_DIER(_timer) &= ~TIM_DIER_UIE; + TIM_DIER(_timer) &= ~to_u32(TIM_DIER_UIE); return OK; } @@ -335,7 +325,7 @@ auto Timer::enable_capture_compare_1_interrupt() -> Result // 9,12 auto Timer::disable_capture_compare_1_interrupt() -> Result { - TIM_DIER(_timer) &= ~TIM_DIER_CC1IE; + TIM_DIER(_timer) &= ~to_u32(TIM_DIER_CC1IE); return OK; } @@ -349,7 +339,7 @@ auto Timer::enable_capture_compare_2_interrupt() -> Result // 9,12 auto Timer::disable_capture_compare_2_interrupt() -> Result { - TIM_DIER(_timer) &= ~TIM_DIER_CC2IE; + TIM_DIER(_timer) &= ~to_u32(TIM_DIER_CC2IE); return OK; } @@ -362,7 +352,7 @@ auto Timer::enable_capture_compare_3_interrupt() -> Result // 9,12 auto Timer::disable_capture_compare_3_interrupt() -> Result { - TIM_DIER(_timer) &= ~TIM_DIER_CC3IE; + TIM_DIER(_timer) &= ~to_u32(TIM_DIER_CC3IE); return OK; } @@ -376,7 +366,7 @@ auto Timer::enable_capture_compare_4_interrupt() -> Result // 9,12 auto Timer::disable_capture_compare_4_interrupt() -> Result { - TIM_DIER(_timer) &= ~TIM_DIER_CC4IE; + TIM_DIER(_timer) &= ~to_u32(TIM_DIER_CC4IE); return OK; } @@ -390,7 +380,7 @@ auto Timer::enable_trigger_interrupt() -> Result // 9,12 auto Timer::disable_trigger_interrupt() -> Result { - TIM_DIER(_timer) &= ~TIM_DIER_TIE; + TIM_DIER(_timer) &= ~to_u32(TIM_DIER_TIE); return OK; } @@ -440,34 +430,34 @@ auto Timer::clear_flag_status(Flag flag) -> Result { switch (flag) { case UPDATE_INTERRUPT: - TIM_SR(_timer) &= ~TIM_SR_UIF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_UIF); break; case CAPTURE_COMPARE_1_INTERRUPT: - TIM_SR(_timer) &= ~TIM_SR_CC1IF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC1IF); break; case CAPTURE_COMPARE_2_INTERRUPT: - TIM_SR(_timer) &= ~TIM_SR_CC2IF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC2IF); break; case CAPTURE_COMPARE_3_INTERRUPT: - TIM_SR(_timer) &= ~TIM_SR_CC3IF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC3IF); break; case CAPTURE_COMPARE_4_INTERRUPT: - TIM_SR(_timer) &= ~TIM_SR_CC4IF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC4IF); break; case TRIGGER_INTERRUPT: - TIM_SR(_timer) &= ~TIM_SR_TIF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_TIF); break; case CAPTURE_COMPARE_1_OVERCAPTURE: - TIM_SR(_timer) &= ~TIM_SR_CC1OF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC1OF); break; case CAPTURE_COMPARE_2_OVERCAPTURE: - TIM_SR(_timer) &= ~TIM_SR_CC2OF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC2OF); break; case CAPTURE_COMPARE_3_OVERCAPTURE: - TIM_SR(_timer) &= ~TIM_SR_CC3OF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC3OF); break; case CAPTURE_COMPARE_4_OVERCAPTURE: - TIM_SR(_timer) &= ~TIM_SR_CC4OF; + TIM_SR(_timer) &= ~to_u32(TIM_SR_CC4OF); break; } @@ -488,22 +478,21 @@ auto Timer::set_capture_compare_1_mode(CcMode mode) -> Result return USAGE_ERROR; } + const uint32_t cc1s_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_CC1S_MASK); + switch (mode) { case OUTPUT: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC1S_MASK) | TIM_CCMR1_CC1S_OUT; + TIM_CCMR1(_timer) = cc1s_clear_mask | TIM_CCMR1_CC1S_OUT; break; case INPUT_MAPPED_TI1: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC1S_MASK) | - TIM_CCMR1_CC1S_IN_TI1; + TIM_CCMR1(_timer) = cc1s_clear_mask | TIM_CCMR1_CC1S_IN_TI1; break; case INPUT_MAPPED_TI2: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC1S_MASK) | - TIM_CCMR1_CC1S_IN_TI2; + TIM_CCMR1(_timer) = cc1s_clear_mask | TIM_CCMR1_CC1S_IN_TI2; break; case INPUT_MAPPED_TRC: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC1S_MASK) | - TIM_CCMR1_CC1S_IN_TRC; + TIM_CCMR1(_timer) = cc1s_clear_mask | TIM_CCMR1_CC1S_IN_TRC; break; default: @@ -522,22 +511,21 @@ auto Timer::set_capture_compare_2_mode(CcMode mode) -> Result return USAGE_ERROR; } + const uint32_t cc2s_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_CC2S_MASK); + switch (mode) { case OUTPUT: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC2S_MASK) | TIM_CCMR1_CC2S_OUT; + TIM_CCMR1(_timer) = cc2s_clear_mask | TIM_CCMR1_CC2S_OUT; break; case INPUT_MAPPED_TI1: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC2S_MASK) | - TIM_CCMR1_CC2S_IN_TI1; + TIM_CCMR1(_timer) = cc2s_clear_mask | TIM_CCMR1_CC2S_IN_TI1; break; case INPUT_MAPPED_TI2: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC2S_MASK) | - TIM_CCMR1_CC2S_IN_TI2; + TIM_CCMR1(_timer) = cc2s_clear_mask | TIM_CCMR1_CC2S_IN_TI2; break; case INPUT_MAPPED_TRC: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_CC2S_MASK) | - TIM_CCMR1_CC2S_IN_TRC; + TIM_CCMR1(_timer) = cc2s_clear_mask | TIM_CCMR1_CC2S_IN_TRC; break; default: @@ -556,22 +544,21 @@ auto Timer::set_input_capture_1_prescaler(Prescaler prescaler) -> Result return USAGE_ERROR; } + const uint32_t ic1psc_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_IC1PSC_MASK); + switch (prescaler) { case NO_PRESCALER: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1PSC_MASK) | - TIM_CCMR1_IC1PSC_OFF; + TIM_CCMR1(_timer) = ic1psc_clear_mask | TIM_CCMR1_IC1PSC_OFF; break; case CAPTURE_EVERY_2_EVENTS: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1PSC_MASK) | TIM_CCMR1_IC1PSC_2; + TIM_CCMR1(_timer) = ic1psc_clear_mask | TIM_CCMR1_IC1PSC_2; break; case CAPTURE_EVERY_4_EVENTS: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1PSC_MASK) | TIM_CCMR1_IC1PSC_4; + TIM_CCMR1(_timer) = ic1psc_clear_mask | TIM_CCMR1_IC1PSC_4; break; case CAPTURE_EVERY_8_EVENTS: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1PSC_MASK) | TIM_CCMR1_IC1PSC_8; + TIM_CCMR1(_timer) = ic1psc_clear_mask | TIM_CCMR1_IC1PSC_8; break; } @@ -587,22 +574,21 @@ auto Timer::set_input_capture_2_prescaler(Prescaler prescaler) -> Result return USAGE_ERROR; } + const uint32_t ic2psc_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_IC2PSC_MASK); + switch (prescaler) { case NO_PRESCALER: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2PSC_MASK) | - TIM_CCMR1_IC2PSC_OFF; + TIM_CCMR1(_timer) = ic2psc_clear_mask | TIM_CCMR1_IC2PSC_OFF; break; case CAPTURE_EVERY_2_EVENTS: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2PSC_MASK) | TIM_CCMR1_IC2PSC_2; + TIM_CCMR1(_timer) = ic2psc_clear_mask | TIM_CCMR1_IC2PSC_2; break; case CAPTURE_EVERY_4_EVENTS: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2PSC_MASK) | TIM_CCMR1_IC2PSC_4; + TIM_CCMR1(_timer) = ic2psc_clear_mask | TIM_CCMR1_IC2PSC_4; break; case CAPTURE_EVERY_8_EVENTS: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2PSC_MASK) | TIM_CCMR1_IC2PSC_8; + TIM_CCMR1(_timer) = ic2psc_clear_mask | TIM_CCMR1_IC2PSC_8; break; } @@ -618,70 +604,57 @@ auto Timer::set_input_capture_1_filter(Filter filter) -> Result return USAGE_ERROR; } + const uint32_t ic1f_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_IC1F_MASK); + switch (filter) { case NO_FILTER: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | TIM_CCMR1_IC1F_OFF; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_OFF; break; case CK_INT_N_2: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_CK_INT_N_2; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_CK_INT_N_2; break; case CK_INT_N_4: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_CK_INT_N_4; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_CK_INT_N_4; break; case CK_INT_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_CK_INT_N_8; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_CK_INT_N_8; break; case DTF_DIV_2_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_2_N_6; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_2_N_6; break; case DTF_DIV_2_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_2_N_8; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_2_N_8; break; case TF_DIV_4_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_4_N_6; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_4_N_6; break; case DTF_DIV_4_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_4_N_8; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_4_N_8; break; case DTF_DIV_8_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_8_N_6; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_8_N_6; break; case DTF_DIV_8_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_8_N_8; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_8_N_8; break; case DTF_DIV_16_N_5: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_16_N_5; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_16_N_5; break; case DTF_DIV_16_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_16_N_6; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_16_N_6; break; case DTF_DIV_16_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_16_N_8; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_16_N_8; break; case DTF_DIV_32_N_5: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_32_N_5; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_32_N_5; break; case DTF_DIV_32_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_32_N_6; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_32_N_6; break; case DTF_DIV_32_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC1F_MASK) | - TIM_CCMR1_IC1F_DTF_DIV_32_N_8; + TIM_CCMR1(_timer) = ic1f_clear_mask | TIM_CCMR1_IC1F_DTF_DIV_32_N_8; break; } @@ -697,70 +670,57 @@ auto Timer::set_input_capture_2_filter(Filter filter) -> Result return USAGE_ERROR; } + const uint32_t ic2f_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_IC2F_MASK); + switch (filter) { case NO_FILTER: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | TIM_CCMR1_IC2F_OFF; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_OFF; break; case CK_INT_N_2: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_CK_INT_N_2; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_CK_INT_N_2; break; case CK_INT_N_4: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_CK_INT_N_4; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_CK_INT_N_4; break; case CK_INT_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_CK_INT_N_8; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_CK_INT_N_8; break; case DTF_DIV_2_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_2_N_6; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_2_N_6; break; case DTF_DIV_2_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_2_N_8; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_2_N_8; break; case TF_DIV_4_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_4_N_6; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_4_N_6; break; case DTF_DIV_4_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_4_N_8; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_4_N_8; break; case DTF_DIV_8_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_8_N_6; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_8_N_6; break; case DTF_DIV_8_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_8_N_8; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_8_N_8; break; case DTF_DIV_16_N_5: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_16_N_5; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_16_N_5; break; case DTF_DIV_16_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_16_N_6; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_16_N_6; break; case DTF_DIV_16_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_16_N_8; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_16_N_8; break; case DTF_DIV_32_N_5: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_32_N_5; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_32_N_5; break; case DTF_DIV_32_N_6: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_32_N_6; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_32_N_6; break; case DTF_DIV_32_N_8: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_IC2F_MASK) | - TIM_CCMR1_IC2F_DTF_DIV_32_N_8; + TIM_CCMR1(_timer) = ic2f_clear_mask | TIM_CCMR1_IC2F_DTF_DIV_32_N_8; break; } @@ -789,7 +749,7 @@ auto Timer::disable_fast_output_compare_1() -> Result return USAGE_ERROR; } - TIM_CCMR1(_timer) &= ~TIM_CCMR1_OC1FE; + TIM_CCMR1(_timer) &= ~to_u32(TIM_CCMR1_OC1FE); return OK; } @@ -815,7 +775,7 @@ auto Timer::disable_fast_output_compare_2() -> Result return USAGE_ERROR; } - TIM_CCMR1(_timer) &= ~TIM_CCMR1_OC2FE; + TIM_CCMR1(_timer) &= ~to_u32(TIM_CCMR1_OC2FE); return OK; } @@ -841,7 +801,7 @@ auto Timer::disable_output_compare_1_preload() -> Result return USAGE_ERROR; } - TIM_CCMR1(_timer) &= ~TIM_CCMR1_OC1PE; + TIM_CCMR1(_timer) &= ~to_u32(TIM_CCMR1_OC1PE); return OK; } @@ -868,7 +828,7 @@ auto Timer::disable_output_compare_2_preload() -> Result return USAGE_ERROR; } - TIM_CCMR1(_timer) &= ~TIM_CCMR1_OC2PE; + TIM_CCMR1(_timer) &= ~to_u32(TIM_CCMR1_OC2PE); return OK; } @@ -881,38 +841,33 @@ auto Timer::set_output_compare_1_mode(OcMode mode) -> Result return USAGE_ERROR; } + const uint32_t oc1m_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_OC1M_MASK); + switch (mode) { case FROZEN: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | - TIM_CCMR1_OC1M_FROZEN; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_FROZEN; break; case ACTIVE_LEVEL_ON_MATCH: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | - TIM_CCMR1_OC1M_ACTIVE; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_ACTIVE; break; case INACTIVE_LEVEL_ON_MATCH: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | - TIM_CCMR1_OC1M_INACTIVE; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_INACTIVE; break; case TOGGLE: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | - TIM_CCMR1_OC1M_TOGGLE; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_TOGGLE; break; case FORCE_INACTIVE_LEVEL: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | - TIM_CCMR1_OC1M_FORCE_LOW; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_FORCE_LOW; break; case FORCE_ACTIVE_LEVEL: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | - TIM_CCMR1_OC1M_FORCE_HIGH; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_FORCE_HIGH; break; case PWM_MODE_1: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | TIM_CCMR1_OC1M_PWM1; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_PWM1; break; case PWM_MODE_2: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC1M_MASK) | TIM_CCMR1_OC1M_PWM2; + TIM_CCMR1(_timer) = oc1m_clear_mask | TIM_CCMR1_OC1M_PWM2; break; } @@ -928,38 +883,33 @@ auto Timer::set_output_compare_2_mode(OcMode mode) -> Result return USAGE_ERROR; } + const uint32_t oc2m_clear_mask = + TIM_CCMR1(_timer) & ~to_u32(TIM_CCMR1_OC2M_MASK); + switch (mode) { case FROZEN: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | - TIM_CCMR1_OC2M_FROZEN; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_FROZEN; break; case ACTIVE_LEVEL_ON_MATCH: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | - TIM_CCMR1_OC2M_ACTIVE; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_ACTIVE; break; case INACTIVE_LEVEL_ON_MATCH: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | - TIM_CCMR1_OC2M_INACTIVE; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_INACTIVE; break; case TOGGLE: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | - TIM_CCMR1_OC2M_TOGGLE; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_TOGGLE; break; case FORCE_INACTIVE_LEVEL: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | - TIM_CCMR1_OC2M_FORCE_LOW; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_FORCE_LOW; break; case FORCE_ACTIVE_LEVEL: - TIM_CCMR1(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | - TIM_CCMR1_OC2M_FORCE_HIGH; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_FORCE_HIGH; break; case PWM_MODE_1: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | TIM_CCMR1_OC2M_PWM1; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_PWM1; break; case PWM_MODE_2: - TIM_CCMR1(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR1_OC2M_MASK) | TIM_CCMR1_OC2M_PWM2; + TIM_CCMR1(_timer) = oc2m_clear_mask | TIM_CCMR1_OC2M_PWM2; break; } @@ -975,22 +925,21 @@ auto Timer::set_capture_compare_3_mode(CcMode mode) -> Result return USAGE_ERROR; } + const uint32_t oc3s_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_CC3S_MASK); + switch (mode) { case OUTPUT: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC3S_MASK) | TIM_CCMR2_CC3S_OUT; + TIM_CCMR2(_timer) = oc3s_clear_mask | TIM_CCMR2_CC3S_OUT; break; case INPUT_MAPPED_TI3: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC3S_MASK) | - TIM_CCMR2_CC3S_IN_TI3; + TIM_CCMR2(_timer) = oc3s_clear_mask | TIM_CCMR2_CC3S_IN_TI3; break; case INPUT_MAPPED_TI4: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC3S_MASK) | - TIM_CCMR2_CC3S_IN_TI4; + TIM_CCMR2(_timer) = oc3s_clear_mask | TIM_CCMR2_CC3S_IN_TI4; break; case INPUT_MAPPED_TRC: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC3S_MASK) | - TIM_CCMR2_CC3S_IN_TRC; + TIM_CCMR2(_timer) = oc3s_clear_mask | TIM_CCMR2_CC3S_IN_TRC; break; case INPUT_MAPPED_TI1: @@ -1010,22 +959,21 @@ auto Timer::set_capture_compare_4_mode(CcMode mode) -> Result return USAGE_ERROR; } + const uint32_t oc4s_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_CC4S_MASK); + switch (mode) { case OUTPUT: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC4S_MASK) | TIM_CCMR2_CC4S_OUT; + TIM_CCMR2(_timer) = oc4s_clear_mask | TIM_CCMR2_CC4S_OUT; break; case INPUT_MAPPED_TI3: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC4S_MASK) | - TIM_CCMR2_CC4S_IN_TI3; + TIM_CCMR2(_timer) = oc4s_clear_mask | TIM_CCMR2_CC4S_IN_TI3; break; case INPUT_MAPPED_TI4: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC4S_MASK) | - TIM_CCMR2_CC4S_IN_TI4; + TIM_CCMR2(_timer) = oc4s_clear_mask | TIM_CCMR2_CC4S_IN_TI4; break; case INPUT_MAPPED_TRC: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_CC4S_MASK) | - TIM_CCMR2_CC4S_IN_TRC; + TIM_CCMR2(_timer) = oc4s_clear_mask | TIM_CCMR2_CC4S_IN_TRC; break; case INPUT_MAPPED_TI1: @@ -1045,22 +993,21 @@ auto Timer::set_input_capture_3_prescaler(Prescaler prescaler) -> Result return USAGE_ERROR; } + const uint32_t ic3psc_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_IC3PSC_MASK); + switch (prescaler) { case NO_PRESCALER: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC3PSC_MASK) | - TIM_CCMR2_IC3PSC_OFF; + TIM_CCMR2(_timer) = ic3psc_clear_mask | TIM_CCMR2_IC3PSC_OFF; break; case CAPTURE_EVERY_2_EVENTS: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC3PSC_MASK) | TIM_CCMR2_IC3PSC_2; + TIM_CCMR2(_timer) = ic3psc_clear_mask | TIM_CCMR2_IC3PSC_2; break; case CAPTURE_EVERY_4_EVENTS: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC3PSC_MASK) | TIM_CCMR2_IC3PSC_4; + TIM_CCMR2(_timer) = ic3psc_clear_mask | TIM_CCMR2_IC3PSC_4; break; case CAPTURE_EVERY_8_EVENTS: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC3PSC_MASK) | TIM_CCMR2_IC3PSC_8; + TIM_CCMR2(_timer) = ic3psc_clear_mask | TIM_CCMR2_IC3PSC_8; break; } @@ -1076,22 +1023,21 @@ auto Timer::set_input_capture_4_prescaler(Prescaler prescaler) -> Result return USAGE_ERROR; } + const uint32_t ic4psc_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_IC4PSC_MASK); + switch (prescaler) { case NO_PRESCALER: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC4PSC_MASK) | - TIM_CCMR2_IC4PSC_OFF; + TIM_CCMR2(_timer) = ic4psc_clear_mask | TIM_CCMR2_IC4PSC_OFF; break; case CAPTURE_EVERY_2_EVENTS: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC4PSC_MASK) | TIM_CCMR2_IC4PSC_2; + TIM_CCMR2(_timer) = ic4psc_clear_mask | TIM_CCMR2_IC4PSC_2; break; case CAPTURE_EVERY_4_EVENTS: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC4PSC_MASK) | TIM_CCMR2_IC4PSC_4; + TIM_CCMR2(_timer) = ic4psc_clear_mask | TIM_CCMR2_IC4PSC_4; break; case CAPTURE_EVERY_8_EVENTS: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_IC4PSC_MASK) | TIM_CCMR2_IC4PSC_8; + TIM_CCMR2(_timer) = ic4psc_clear_mask | TIM_CCMR2_IC4PSC_8; break; } @@ -1107,70 +1053,57 @@ auto Timer::set_input_capture_3_filter(Filter filter) -> Result return USAGE_ERROR; } + const uint32_t ic3f_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_IC3F_MASK); + switch (filter) { case NO_FILTER: - TIM_CCMR2(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | TIM_CCMR2_IC3F_OFF; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_OFF; break; case CK_INT_N_2: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_CK_INT_N_2; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_CK_INT_N_2; break; case CK_INT_N_4: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_CK_INT_N_4; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_CK_INT_N_4; break; case CK_INT_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_CK_INT_N_8; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_CK_INT_N_8; break; case DTF_DIV_2_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_2_N_6; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_2_N_6; break; case DTF_DIV_2_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_2_N_8; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_2_N_8; break; case TF_DIV_4_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_4_N_6; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_4_N_6; break; case DTF_DIV_4_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_4_N_8; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_4_N_8; break; case DTF_DIV_8_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_8_N_6; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_8_N_6; break; case DTF_DIV_8_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_8_N_8; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_8_N_8; break; case DTF_DIV_16_N_5: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_16_N_5; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_16_N_5; break; case DTF_DIV_16_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_16_N_6; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_16_N_6; break; case DTF_DIV_16_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_16_N_8; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_16_N_8; break; case DTF_DIV_32_N_5: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_32_N_5; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_32_N_5; break; case DTF_DIV_32_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_32_N_6; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_32_N_6; break; case DTF_DIV_32_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC3F_MASK) | - TIM_CCMR2_IC3F_DTF_DIV_32_N_8; + TIM_CCMR2(_timer) = ic3f_clear_mask | TIM_CCMR2_IC3F_DTF_DIV_32_N_8; break; } @@ -1186,70 +1119,57 @@ auto Timer::set_input_capture_4_filter(Filter filter) -> Result return USAGE_ERROR; } + const uint32_t ic4f_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_IC4F_MASK); + switch (filter) { case NO_FILTER: - TIM_CCMR2(_timer) = - (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | TIM_CCMR2_IC4F_OFF; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_OFF; break; case CK_INT_N_2: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_CK_INT_N_2; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_CK_INT_N_2; break; case CK_INT_N_4: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_CK_INT_N_4; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_CK_INT_N_4; break; case CK_INT_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_CK_INT_N_8; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_CK_INT_N_8; break; case DTF_DIV_2_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_2_N_6; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_2_N_6; break; case DTF_DIV_2_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_2_N_8; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_2_N_8; break; case TF_DIV_4_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_4_N_6; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_4_N_6; break; case DTF_DIV_4_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_4_N_8; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_4_N_8; break; case DTF_DIV_8_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_8_N_6; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_8_N_6; break; case DTF_DIV_8_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_8_N_8; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_8_N_8; break; case DTF_DIV_16_N_5: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_16_N_5; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_16_N_5; break; case DTF_DIV_16_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_16_N_6; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_16_N_6; break; case DTF_DIV_16_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_16_N_8; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_16_N_8; break; case DTF_DIV_32_N_5: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_32_N_5; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_32_N_5; break; case DTF_DIV_32_N_6: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_32_N_6; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_32_N_6; break; case DTF_DIV_32_N_8: - TIM_CCMR2(_timer) = (TIM_CCMR1(_timer) & ~TIM_CCMR2_IC4F_MASK) | - TIM_CCMR2_IC4F_DTF_DIV_32_N_8; + TIM_CCMR2(_timer) = ic4f_clear_mask | TIM_CCMR2_IC4F_DTF_DIV_32_N_8; break; } @@ -1277,7 +1197,7 @@ auto Timer::disable_fast_output_compare_3() -> Result return USAGE_ERROR; } - TIM_CCMR2(_timer) &= ~TIM_CCMR2_OC3FE; + TIM_CCMR2(_timer) &= ~to_u32(TIM_CCMR2_OC3FE); return OK; } @@ -1303,7 +1223,7 @@ auto Timer::disable_fast_output_compare_4() -> Result return USAGE_ERROR; } - TIM_CCMR2(_timer) &= ~TIM_CCMR2_OC4FE; + TIM_CCMR2(_timer) &= ~to_u32(TIM_CCMR2_OC4FE); return OK; } @@ -1329,7 +1249,7 @@ auto Timer::disable_output_compare_3_preload() -> Result return USAGE_ERROR; } - TIM_CCMR2(_timer) &= ~TIM_CCMR2_OC3PE; + TIM_CCMR2(_timer) &= ~to_u32(TIM_CCMR2_OC3PE); return OK; } @@ -1355,7 +1275,7 @@ auto Timer::disable_output_compare_4_preload() -> Result return USAGE_ERROR; } - TIM_CCMR2(_timer) &= ~TIM_CCMR2_OC4PE; + TIM_CCMR2(_timer) &= ~to_u32(TIM_CCMR2_OC4PE); return OK; } @@ -1368,38 +1288,33 @@ auto Timer::set_output_compare_3_mode(OcMode mode) -> Result return USAGE_ERROR; } + const uint32_t oc3m_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_OC3M_FROZEN); + switch (mode) { case FROZEN: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | - TIM_CCMR2_OC3M_FROZEN; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_FROZEN; break; case ACTIVE_LEVEL_ON_MATCH: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | - TIM_CCMR2_OC3M_ACTIVE; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_ACTIVE; break; case INACTIVE_LEVEL_ON_MATCH: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | - TIM_CCMR2_OC3M_INACTIVE; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_INACTIVE; break; case TOGGLE: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | - TIM_CCMR2_OC3M_TOGGLE; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_TOGGLE; break; case FORCE_INACTIVE_LEVEL: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | - TIM_CCMR2_OC3M_FORCE_LOW; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_FORCE_LOW; break; case FORCE_ACTIVE_LEVEL: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | - TIM_CCMR2_OC3M_FORCE_HIGH; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_FORCE_HIGH; break; case PWM_MODE_1: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | TIM_CCMR2_OC3M_PWM1; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_PWM1; break; case PWM_MODE_2: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC3M_MASK) | TIM_CCMR2_OC3M_PWM2; + TIM_CCMR2(_timer) = oc3m_clear_mask | TIM_CCMR2_OC3M_PWM2; break; } @@ -1415,38 +1330,33 @@ auto Timer::set_output_compare_4_mode(OcMode mode) -> Result return USAGE_ERROR; } + const uint32_t oc4m_clear_mask = + TIM_CCMR2(_timer) & ~to_u32(TIM_CCMR2_OC4M_MASK); + switch (mode) { case FROZEN: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | - TIM_CCMR2_OC4M_FROZEN; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_FROZEN; break; case ACTIVE_LEVEL_ON_MATCH: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | - TIM_CCMR2_OC4M_ACTIVE; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_ACTIVE; break; case INACTIVE_LEVEL_ON_MATCH: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | - TIM_CCMR2_OC4M_INACTIVE; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_INACTIVE; break; case TOGGLE: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | - TIM_CCMR2_OC4M_TOGGLE; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_TOGGLE; break; case FORCE_INACTIVE_LEVEL: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | - TIM_CCMR2_OC4M_FORCE_LOW; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_FORCE_LOW; break; case FORCE_ACTIVE_LEVEL: - TIM_CCMR2(_timer) = (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | - TIM_CCMR2_OC4M_FORCE_HIGH; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_FORCE_HIGH; break; case PWM_MODE_1: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | TIM_CCMR2_OC4M_PWM1; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_PWM1; break; case PWM_MODE_2: - TIM_CCMR2(_timer) = - (TIM_CCMR2(_timer) & ~TIM_CCMR2_OC4M_MASK) | TIM_CCMR2_OC4M_PWM2; + TIM_CCMR2(_timer) = oc4m_clear_mask | TIM_CCMR2_OC4M_PWM2; break; } @@ -1463,7 +1373,7 @@ auto Timer::enable_capture_compare_1() -> Result // 9,12 auto Timer::disable_capture_compare_1() -> Result { - TIM_CCER(_timer) &= ~TIM_CCER_CC1E; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC1E); return OK; } @@ -1475,7 +1385,7 @@ auto Timer::set_capture_compare_1_polarity(Polarity polarity) -> Result TIM_CCER(_timer) |= TIM_CCER_CC1P; break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~TIM_CCER_CC1P; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC1P); break; } @@ -1489,7 +1399,7 @@ auto Timer::set_capture_compare_1_com_polarity(Polarity polarity) -> Result TIM_CCER(_timer) |= TIM_CCER_CC1NP; break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~TIM_CCER_CC1NP; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC1NP); break; } @@ -1506,7 +1416,7 @@ auto Timer::enable_capture_compare_2() -> Result // 9,12 auto Timer::disable_capture_compare_2() -> Result { - TIM_CCER(_timer) &= ~TIM_CCER_CC2E; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC2E); return OK; } @@ -1518,7 +1428,7 @@ auto Timer::set_capture_compare_2_polarity(Polarity polarity) -> Result TIM_CCER(_timer) |= TIM_CCER_CC2P; break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~TIM_CCER_CC2P; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC2P); break; } @@ -1534,7 +1444,7 @@ auto Timer::enable_capture_compare_3() -> Result // 9,12 auto Timer::disable_capture_compare_3() -> Result { - TIM_CCER(_timer) &= ~TIM_CCER_CC3E; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC3E); return OK; } @@ -1546,7 +1456,7 @@ auto Timer::set_capture_compare_3_polarity(Polarity polarity) -> Result TIM_CCER(_timer) |= TIM_CCER_CC3P; break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~TIM_CCER_CC3P; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC3P); break; } @@ -1560,7 +1470,7 @@ auto Timer::set_capture_compare_3_com_polarity(Polarity polarity) -> Result TIM_CCER(_timer) |= TIM_CCER_CC3NP; break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~TIM_CCER_CC3NP; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC3NP); break; } @@ -1577,7 +1487,7 @@ auto Timer::enable_capture_compare_4() -> Result // 9,12 auto Timer::disable_capture_compare_4() -> Result { - TIM_CCER(_timer) &= ~TIM_CCER_CC4E; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC4E); return OK; } @@ -1589,7 +1499,7 @@ auto Timer::set_capture_compare_4_polarity(Polarity polarity) -> Result TIM_CCER(_timer) |= TIM_CCER_CC4P; break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~TIM_CCER_CC4P; + TIM_CCER(_timer) &= ~to_u32(TIM_CCER_CC4P); break; } @@ -1600,10 +1510,10 @@ auto Timer::set_capture_compare_4_com_polarity(Polarity polarity) -> Result { switch (polarity) { case LO_FALLING_EDGE: - TIM_CCER(_timer) |= (1 << 15); + TIM_CCER(_timer) |= to_u32(1 << 15); break; case HI_RISING_EDGE: - TIM_CCER(_timer) &= ~(1 << 15); + TIM_CCER(_timer) &= ~to_u32(1 << 15); break; } @@ -1613,7 +1523,7 @@ auto Timer::set_capture_compare_4_com_polarity(Polarity polarity) -> Result // 9,12 uint16_t Timer::get_counter_value() const { - return TIM_CNT(_timer); + return static_cast<uint16_t>(TIM_CNT(_timer)); } uint32_t Timer::get_counter_value32() const @@ -1630,7 +1540,7 @@ void Timer::set_counter_value(uint16_t value) // 9,12 uint16_t Timer::get_prescaler_value() const { - return TIM_PSC(_timer); + return static_cast<uint16_t>(TIM_PSC(_timer)); } // 9,12 @@ -1642,7 +1552,7 @@ void Timer::set_prescaler_value(uint32_t value) // 9,12 uint16_t Timer::get_autoreload_value() const { - return TIM_ARR(_timer); + return static_cast<uint16_t>(TIM_ARR(_timer)); } // 9,12 @@ -1654,7 +1564,7 @@ void Timer::set_autoreload_value(uint32_t value) // 9,12 uint16_t Timer::get_capture_compare_1_value() const { - return TIM_CCR1(_timer); + return static_cast<uint16_t>(TIM_CCR1(_timer)); } // 9,12 @@ -1666,7 +1576,7 @@ void Timer::set_capture_compare_1_value(uint32_t value) // 9,12 uint16_t Timer::get_capture_compare_2_value() const { - return TIM_CCR2(_timer); + return static_cast<uint16_t>(TIM_CCR2(_timer)); } // 9,12 @@ -1677,7 +1587,7 @@ void Timer::set_capture_compare_2_value(uint32_t value) uint16_t Timer::get_capture_compare_3_value() const { - return TIM_CCR3(_timer); + return static_cast<uint16_t>(TIM_CCR3(_timer)); } // 9,12 @@ -1689,7 +1599,7 @@ void Timer::set_capture_compare_3_value(uint32_t value) // 9,12 uint16_t Timer::get_capture_compare_4_value() const { - return TIM_CCR4(_timer); + return static_cast<uint16_t>(TIM_CCR4(_timer)); } // 9,12 @@ -1705,7 +1615,7 @@ void Timer::enable_etr_clock() void Timer::disable_etr_clock() { - TIM_SMCR(_timer) &= ~TIM_SMCR_ECE; // reset enable bit + TIM_SMCR(_timer) &= ~to_u32(TIM_SMCR_ECE); // reset enable bit } void Timer::set_etr_filter(ExtTriggerFilter filter) |