diff options
| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2022-03-31 13:03:06 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2022-05-22 08:58:30 +0300 |
| commit | dc21ed2aef4150fc2fcf58227a4ff24502015c03 (patch) | |
| tree | 31679737f6f1ab8dbd2807d96546f0f7669c8d33 /Documentation/devicetree/bindings/powerpc/fsl | |
| parent | 5dd9e27ea4a39f7edd4bf81e9e70208e7ac0b7c9 (diff) | |
powerpc/85xx: Remove FSL_85XX_CACHE_SRAM
CONFIG_FSL_85XX_CACHE_SRAM is an option that is not
user selectable and which is not selected by any driver
nor any defconfig.
Remove it and all associated code.
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/9949813a6b758903b7bee910f798ba2ca82ff8ee.1648720908.git.christophe.leroy@csgroup.eu
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc/fsl')
| -rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt b/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt deleted file mode 100644 index 781955f5217d..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/cache_sram.txt +++ /dev/null @@ -1,20 +0,0 @@ -* Freescale PQ3 and QorIQ based Cache SRAM - -Freescale's mpc85xx and some QorIQ platforms provide an -option of configuring a part of (or full) cache memory -as SRAM. This cache SRAM representation in the device -tree should be done as under:- - -Required properties: - -- compatible : should be "fsl,p2020-cache-sram" -- fsl,cache-sram-ctlr-handle : points to the L2 controller -- reg : offset and length of the cache-sram. - -Example: - -cache-sram@fff00000 { - fsl,cache-sram-ctlr-handle = <&L2>; - reg = <0 0xfff00000 0 0x10000>; - compatible = "fsl,p2020-cache-sram"; -}; |