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| author | Sean Christopherson <seanjc@google.com> | 2022-07-09 01:02:41 +0300 |
|---|---|---|
| committer | Sean Christopherson <seanjc@google.com> | 2022-07-09 01:02:41 +0300 |
| commit | 4a627b0b162b9495f3646caa6edb0e0f97d8f2de (patch) | |
| tree | fb1ba7d97b016d558fd2a19b592b5bfd53aae93e /arch/x86/kvm/x86.c | |
| parent | b9b71f43683ae9d76b0989249607bbe8c9eb6c5c (diff) | |
| parent | 54ad60ba9d2673293c72a7c1c4f092622a1f8789 (diff) | |
Merge branch 'kvm-5.20-msr-eperm'
Merge a bug fix and cleanups for {g,s}et_msr_mce() using a base that
predates commit 281b52780b57 ("KVM: x86: Add emulation for
MSR_IA32_MCx_CTL2 MSRs."), which was written with the intention that it
be applied _after_ the bug fix and cleanups. The bug fix in particular
needs to be sent to stable trees; give them a stable hash to use.
Diffstat (limited to 'arch/x86/kvm/x86.c')
| -rw-r--r-- | arch/x86/kvm/x86.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 567d13405445..fb37d11dec2d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -3258,9 +3258,9 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info) * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB * issue on AMD K8s, allow bit 10 to be clear when setting all * other bits in order to avoid an uncaught #GP in the guest. - * - * UNIXWARE clears bit 0 of MC1_CTL to ignore - * correctable, single-bit ECC data errors. + * + * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable, + * single-bit ECC data errors. */ if (is_mci_control_msr(msr) && data != 0 && (data | (1 << 10) | 1) != ~(u64)0) |