diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2018-04-14 01:51:06 +0300 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2018-04-14 01:51:06 +0300 |
commit | ca4e7c51201fc47b2668d58faaa3b46a99d1a233 (patch) | |
tree | 06e0ece281eff94ff78c11e78e036d5b61ebbe60 /drivers/clk/ti | |
parent | daf3ef6e965d1d51d6ec604a8fc9919b75d5ec3c (diff) | |
parent | b44c4ddf4a15c42a91a88aaa32b7d53cf43391cb (diff) |
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The large diff this time around is from the addition of a new clk
driver for the TI Davinci family of SoCs. So far those clks have been
supported with a custom implementation of the clk API in the arch port
instead of in the CCF. With this driver merged we're one step closer
to having a single clk API implementation.
The other large diff is from the Amlogic clk driver that underwent
some major surgery to use regmap. Beyond that, the biggest hitter is
Samsung which needed some reworks to properly handle clk provider
power domains and a bunch of PLL rate updates.
The core framework was fairly quiet this round, just getting some
cleanups and small fixes for some of the more esoteric features. And
the usual set of driver non-critical fixes, cleanups, and minor
additions are here as well.
Core:
- Rejig clk_ops::init() to be a little earlier for phase/accuracy ops
- debugfs ops macroized to shave some lines of boilerplate code
- Always calculate the phase instead of caching it in clk_get_phase()
- More __must_check on bulk clk APIs
New Drivers:
- TI's Davinci family of SoCs
- Intel's Stratix10 SoC
- stm32mp157 SoC
- Allwinner H6 CCU
- Silicon Labs SI544 clock generator chip
- Renesas R-Car M3-N and V3H SoCs
- i.MX6SLL SoCs
Removed Drivers:
- ST-Ericsson AB8540/9540
Updates:
- Mediatek MT2701 and MT7622 audsys support and MT2712 updates
- STM32F469 DSI and STM32F769 sdmmc2 support
- GPIO clks can sleep now
- Spreadtrum SC9860 RTC clks
- Nvidia Tegra MBIST workarounds and various minor fixes
- Rockchip phase handling fixes and a memory leak plugged
- Renesas drivers switch to readl/writel from clk_readl/clk_writel
- Renesas gained CPU (Z/Z2) and watchdog support
- Rockchip rk3328 display clks and rk3399 1.6GHz PLL support
- Qualcomm PM8921 PMIC XO buffers
- Amlogic migrates to regmap APIs
- TI Keystone clk latching support
- Allwinner H3 and H5 video clk fixes
- Broadcom BCM2835 PLLs needed another bit to enable
- i.MX6SX CKO mux fix and i.MX7D Video PLL divider fix
- i.MX6UL/ULL epdc_podf support
- Hi3798CV200 COMBPHY0 and USB2_OTG_UTMI and phase support for eMMC"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (233 commits)
clk: davinci: add a reset lookup table for psc0
clk: imx: add clock driver for imx6sll
dt-bindings: imx: update clock doc for imx6sll
clk: imx: add new gate/gate2 wrapper funtion
clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux
clk: cs2000: set pm_ops in hibernate-compatible way
clk: bcm2835: De-assert/assert PLL reset signal when appropriate
clk: imx7d: Move clks_init_on before any clock operations
clk: imx7d: Correct ahb clk parent select
clk: imx7d: Correct dram pll type
clk: imx7d: Add USB clock information
clk: socfpga: stratix10: add clock driver for Stratix10 platform
dt-bindings: documentation: add clock bindings information for Stratix10
clk: ti: fix flag space conflict with clkctrl clocks
clk: uniphier: add additional ethernet clock lines for Pro4
clk: uniphier: add SATA clock control support
clk: uniphier: add PCIe clock control support
clk: Add driver for the si544 clock generator chip
clk: davinci: Remove redundant dev_err calls
clk: uniphier: add ethernet clock control support for PXs3
...
Diffstat (limited to 'drivers/clk/ti')
-rw-r--r-- | drivers/clk/ti/clk.c | 38 | ||||
-rw-r--r-- | drivers/clk/ti/clock.h | 13 | ||||
-rw-r--r-- | drivers/clk/ti/divider.c | 26 | ||||
-rw-r--r-- | drivers/clk/ti/mux.c | 13 |
4 files changed, 77 insertions, 13 deletions
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c index f4d6802a8544..7d22e1af2247 100644 --- a/drivers/clk/ti/clk.c +++ b/drivers/clk/ti/clk.c @@ -55,6 +55,29 @@ static void clk_memmap_writel(u32 val, const struct clk_omap_reg *reg) writel_relaxed(val, io->mem + reg->offset); } +static void _clk_rmw(u32 val, u32 mask, void __iomem *ptr) +{ + u32 v; + + v = readl_relaxed(ptr); + v &= ~mask; + v |= val; + writel_relaxed(v, ptr); +} + +static void clk_memmap_rmw(u32 val, u32 mask, const struct clk_omap_reg *reg) +{ + struct clk_iomap *io = clk_memmaps[reg->index]; + + if (reg->ptr) { + _clk_rmw(val, mask, reg->ptr); + } else if (io->regmap) { + regmap_update_bits(io->regmap, reg->offset, mask, val); + } else { + _clk_rmw(val, mask, io->mem + reg->offset); + } +} + static u32 clk_memmap_readl(const struct clk_omap_reg *reg) { u32 val; @@ -89,6 +112,7 @@ int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) ti_clk_ll_ops = ops; ops->clk_readl = clk_memmap_readl; ops->clk_writel = clk_memmap_writel; + ops->clk_rmw = clk_memmap_rmw; return 0; } @@ -251,6 +275,20 @@ int ti_clk_get_reg_addr(struct device_node *node, int index, return 0; } +void ti_clk_latch(struct clk_omap_reg *reg, s8 shift) +{ + u32 latch; + + if (shift < 0) + return; + + latch = 1 << shift; + + ti_clk_ll_ops->clk_rmw(latch, latch, reg); + ti_clk_ll_ops->clk_rmw(0, latch, reg); + ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ +} + /** * omap2_clk_provider_init - init master clock provider * @parent: master node diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index d9b43bfc2532..b58278077226 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -22,6 +22,7 @@ struct clk_omap_divider { u8 shift; u8 width; u8 flags; + s8 latch; const struct clk_div_table *table; }; @@ -33,6 +34,7 @@ struct clk_omap_mux { u32 *table; u32 mask; u8 shift; + s8 latch; u8 flags; }; @@ -74,6 +76,11 @@ enum { #define CLKF_CORE (1 << 9) #define CLKF_J_TYPE (1 << 10) +/* CLKCTRL flags */ +#define CLKF_SW_SUP BIT(5) +#define CLKF_HW_SUP BIT(6) +#define CLKF_NO_IDLEST BIT(7) + #define CLK(dev, con, ck) \ { \ .lk = { \ @@ -183,10 +190,6 @@ extern const struct omap_clkctrl_data am438x_clkctrl_data[]; extern const struct omap_clkctrl_data dm814_clkctrl_data[]; extern const struct omap_clkctrl_data dm816_clkctrl_data[]; -#define CLKF_SW_SUP BIT(0) -#define CLKF_HW_SUP BIT(1) -#define CLKF_NO_IDLEST BIT(2) - typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, @@ -194,6 +197,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); void ti_clk_add_aliases(void); +void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); + struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup); int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 77f93f6d2806..aaa277dd6d99 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -263,6 +263,8 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, val |= value << divider->shift; ti_clk_ll_ops->clk_writel(val, ÷r->reg); + ti_clk_latch(÷r->reg, divider->latch); + return 0; } @@ -276,7 +278,8 @@ static struct clk *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, struct clk_omap_reg *reg, - u8 shift, u8 width, u8 clk_divider_flags, + u8 shift, u8 width, s8 latch, + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk_omap_divider *div; @@ -305,6 +308,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, memcpy(&div->reg, reg, sizeof(*reg)); div->shift = shift; div->width = width; + div->latch = latch; div->flags = clk_divider_flags; div->hw.init = &init; div->table = table; @@ -420,6 +424,7 @@ struct clk_hw *ti_clk_build_component_div(struct ti_clk_divider *setup) div->table = _get_div_table_from_setup(setup, &div->width); div->shift = setup->bit_shift; + div->latch = -EINVAL; return &div->hw; } @@ -452,7 +457,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup) clk = _register_divider(NULL, setup->name, div->parent, flags, ®, div->bit_shift, - width, div_flags, table); + width, -EINVAL, div_flags, table); if (IS_ERR(clk)) kfree(table); @@ -556,7 +561,7 @@ static int _get_divider_width(struct device_node *node, static int __init ti_clk_divider_populate(struct device_node *node, struct clk_omap_reg *reg, const struct clk_div_table **table, - u32 *flags, u8 *div_flags, u8 *width, u8 *shift) + u32 *flags, u8 *div_flags, u8 *width, u8 *shift, s8 *latch) { u32 val; int ret; @@ -570,6 +575,13 @@ static int __init ti_clk_divider_populate(struct device_node *node, else *shift = 0; + if (latch) { + if (!of_property_read_u32(node, "ti,latch-bit", &val)) + *latch = val; + else + *latch = -EINVAL; + } + *flags = 0; *div_flags = 0; @@ -606,17 +618,18 @@ static void __init of_ti_divider_clk_setup(struct device_node *node) u8 clk_divider_flags = 0; u8 width = 0; u8 shift = 0; + s8 latch = -EINVAL; const struct clk_div_table *table = NULL; u32 flags = 0; parent_name = of_clk_get_parent_name(node, 0); if (ti_clk_divider_populate(node, ®, &table, &flags, - &clk_divider_flags, &width, &shift)) + &clk_divider_flags, &width, &shift, &latch)) goto cleanup; clk = _register_divider(NULL, node->name, parent_name, flags, ®, - shift, width, clk_divider_flags, table); + shift, width, latch, clk_divider_flags, table); if (!IS_ERR(clk)) { of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -639,7 +652,8 @@ static void __init of_ti_composite_divider_clk_setup(struct device_node *node) return; if (ti_clk_divider_populate(node, &div->reg, &div->table, &val, - &div->flags, &div->width, &div->shift) < 0) + &div->flags, &div->width, &div->shift, + NULL) < 0) goto cleanup; if (!ti_clk_add_component(node, &div->hw, CLK_COMPONENT_TYPE_DIVIDER)) diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index d4705803f3d3..69a4308a5a98 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -86,6 +86,7 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) } val |= index << mux->shift; ti_clk_ll_ops->clk_writel(val, &mux->reg); + ti_clk_latch(&mux->reg, mux->latch); return 0; } @@ -100,7 +101,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, struct clk_omap_reg *reg, u8 shift, u32 mask, - u8 clk_mux_flags, u32 *table) + s8 latch, u8 clk_mux_flags, u32 *table) { struct clk_omap_mux *mux; struct clk *clk; @@ -121,6 +122,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, memcpy(&mux->reg, reg, sizeof(*reg)); mux->shift = shift; mux->mask = mask; + mux->latch = latch; mux->flags = clk_mux_flags; mux->table = table; mux->hw.init = &init; @@ -160,7 +162,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup) flags |= CLK_SET_RATE_PARENT; return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, - flags, ®, mux->bit_shift, mask, + flags, ®, mux->bit_shift, mask, -EINVAL, mux_flags, NULL); } @@ -179,6 +181,7 @@ static void of_mux_clk_setup(struct device_node *node) u8 clk_mux_flags = 0; u32 mask = 0; u32 shift = 0; + s32 latch = -EINVAL; u32 flags = CLK_SET_RATE_NO_REPARENT; num_parents = of_clk_get_parent_count(node); @@ -197,6 +200,8 @@ static void of_mux_clk_setup(struct device_node *node) of_property_read_u32(node, "ti,bit-shift", &shift); + of_property_read_u32(node, "ti,latch-bit", &latch); + if (of_property_read_bool(node, "ti,index-starts-at-one")) clk_mux_flags |= CLK_MUX_INDEX_ONE; @@ -211,7 +216,8 @@ static void of_mux_clk_setup(struct device_node *node) mask = (1 << fls(mask)) - 1; clk = _register_mux(NULL, node->name, parent_names, num_parents, - flags, ®, shift, mask, clk_mux_flags, NULL); + flags, ®, shift, mask, latch, clk_mux_flags, + NULL); if (!IS_ERR(clk)) of_clk_add_provider(node, of_clk_src_simple_get, clk); @@ -234,6 +240,7 @@ struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup) return ERR_PTR(-ENOMEM); mux->shift = setup->bit_shift; + mux->latch = -EINVAL; mux->reg.index = setup->module; mux->reg.offset = setup->reg; |