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authorDaniel Lezcano <daniel.lezcano@linaro.org>2021-12-09 15:57:57 +0300
committerDaniel Lezcano <daniel.lezcano@linaro.org>2021-12-09 15:57:57 +0300
commit8632987380765dee716d460640aa58d58d52998e (patch)
treef8f4a55fc95c1060f97d64ee4d6db5c9693bb794 /drivers/clocksource
parent410fbda49cc9b2165e80b87880f164d9644b460d (diff)
parentc4f5b30dda01f2f6979a9681142de454991182ee (diff)
Merge branch 'reset/of-get-optional-exclusive' of git://git.pengutronix.de/pza/linux into timers/drivers/next
"Add optional variant of of_reset_control_get_exclusive(). If the requested reset is not specified in the device tree, this function returns NULL instead of an error." This dependency is needed for the Generic Timer Module (a.k.a OSTM) support for RZ/G2L. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'drivers/clocksource')
-rw-r--r--drivers/clocksource/Kconfig3
-rw-r--r--drivers/clocksource/hyperv_timer.c3
-rw-r--r--drivers/clocksource/timer-ixp4xx.c48
-rw-r--r--drivers/clocksource/timer-riscv.c9
4 files changed, 47 insertions, 16 deletions
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e71ac54b7896..f65e31bab9ae 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -235,8 +235,9 @@ config CLKSRC_LPC32XX
Support for the LPC32XX clocksource.
config CLKSRC_PISTACHIO
- bool "Clocksource for Pistachio SoC" if COMPILE_TEST
+ bool "Clocksource for Pistachio SoC"
depends on HAS_IOMEM
+ depends on MIPS || COMPILE_TEST
select TIMER_OF
help
Enables the clocksource for the Pistachio SoC.
diff --git a/drivers/clocksource/hyperv_timer.c b/drivers/clocksource/hyperv_timer.c
index d6ece7bbce89..ff188ab68496 100644
--- a/drivers/clocksource/hyperv_timer.c
+++ b/drivers/clocksource/hyperv_timer.c
@@ -361,9 +361,6 @@ EXPORT_SYMBOL_GPL(hv_stimer_global_cleanup);
* Hyper-V and 32-bit x86. The TSC reference page version is preferred.
*/
-u64 (*hv_read_reference_counter)(void);
-EXPORT_SYMBOL_GPL(hv_read_reference_counter);
-
static union {
struct ms_hyperv_tsc_page page;
u8 reserved[PAGE_SIZE];
diff --git a/drivers/clocksource/timer-ixp4xx.c b/drivers/clocksource/timer-ixp4xx.c
index 9396745e1c17..cbb184953510 100644
--- a/drivers/clocksource/timer-ixp4xx.c
+++ b/drivers/clocksource/timer-ixp4xx.c
@@ -18,6 +18,7 @@
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/platform_device.h>
/* Goes away with OF conversion */
#include <linux/platform_data/timer-ixp4xx.h>
@@ -29,9 +30,6 @@
#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
-#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
-#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
-#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
/*
@@ -45,17 +43,10 @@
#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
-#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
-#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
-
-#define IXP4XX_WDT_KEY 0x0000482E
-#define IXP4XX_WDT_RESET_ENABLE 0x00000001
-#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
-#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
+/* Remaining registers are for the watchdog and defined in the watchdog driver */
struct ixp4xx_timer {
void __iomem *base;
- unsigned int tick_rate;
u32 latch;
struct clock_event_device clkevt;
#ifdef CONFIG_ARM
@@ -181,7 +172,6 @@ static __init int ixp4xx_timer_register(void __iomem *base,
if (!tmr)
return -ENOMEM;
tmr->base = base;
- tmr->tick_rate = timer_freq;
/*
* The timer register doesn't allow to specify the two least
@@ -239,6 +229,40 @@ static __init int ixp4xx_timer_register(void __iomem *base,
return 0;
}
+static struct platform_device ixp4xx_watchdog_device = {
+ .name = "ixp4xx-watchdog",
+ .id = -1,
+};
+
+/*
+ * This probe gets called after the timer is already up and running. The main
+ * function on this platform is to spawn the watchdog device as a child.
+ */
+static int ixp4xx_timer_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+ /* Pass the base address as platform data and nothing else */
+ ixp4xx_watchdog_device.dev.platform_data = local_ixp4xx_timer->base;
+ ixp4xx_watchdog_device.dev.parent = dev;
+ return platform_device_register(&ixp4xx_watchdog_device);
+}
+
+static const struct of_device_id ixp4xx_timer_dt_id[] = {
+ { .compatible = "intel,ixp4xx-timer", },
+ { /* sentinel */ },
+};
+
+static struct platform_driver ixp4xx_timer_driver = {
+ .probe = ixp4xx_timer_probe,
+ .driver = {
+ .name = "ixp4xx-timer",
+ .of_match_table = ixp4xx_timer_dt_id,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver(ixp4xx_timer_driver);
+
/**
* ixp4xx_timer_setup() - Timer setup function to be called from boardfiles
* @timerbase: physical base of timer block
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index c51c5ed15aa7..1767f8bf2013 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -13,10 +13,12 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/module.h>
#include <linux/sched_clock.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/interrupt.h>
#include <linux/of_irq.h>
+#include <clocksource/timer-riscv.h>
#include <asm/smp.h>
#include <asm/sbi.h>
#include <asm/timex.h>
@@ -79,6 +81,13 @@ static int riscv_timer_dying_cpu(unsigned int cpu)
return 0;
}
+void riscv_cs_get_mult_shift(u32 *mult, u32 *shift)
+{
+ *mult = riscv_clocksource.mult;
+ *shift = riscv_clocksource.shift;
+}
+EXPORT_SYMBOL_GPL(riscv_cs_get_mult_shift);
+
/* called directly from the low-level interrupt handler */
static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id)
{