diff options
| author | Luca Weiss <luca@z3ntu.xyz> | 2022-01-30 14:45:35 +0300 |
|---|---|---|
| committer | Viresh Kumar <viresh.kumar@linaro.org> | 2022-02-09 10:50:03 +0300 |
| commit | 4a8a77abf0e2b6468ba0281e33384cbec5fb476a (patch) | |
| tree | a0af4f1f37bea0c84e1a029f36f66b869d7575a8 /drivers/cpufreq | |
| parent | b48cd0d12f8e3b5fc928ac84734e563eda8e430f (diff) | |
cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse
The fuse consists of 64 bits, with this statement we're supposed to get
the upper 32 bits but it actually read out of bounds and got 0 instead
of the desired value which lead to the "PVS bin not set." codepath being
run resetting our pvs value.
Fixes: a8811ec764f9 ("cpufreq: qcom: Add support for krait based socs")
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'drivers/cpufreq')
| -rw-r--r-- | drivers/cpufreq/qcom-cpufreq-nvmem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index d1744b5d9619..6dfa86971a75 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -130,7 +130,7 @@ static void get_krait_bin_format_b(struct device *cpu_dev, } /* Check PVS_BLOW_STATUS */ - pte_efuse = *(((u32 *)buf) + 4); + pte_efuse = *(((u32 *)buf) + 1); pte_efuse &= BIT(21); if (pte_efuse) { dev_dbg(cpu_dev, "PVS bin: %d\n", *pvs); |