diff options
| author | Guo Mengqi <guomengqi3@huawei.com> | 2022-07-15 05:33:12 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-07-28 11:33:44 +0300 |
| commit | b9f1736e475dba0d6da48fdcb831248ab1597886 (patch) | |
| tree | 4d4084eff6b8671ea5a1be52b53fe35b81d8c11a /drivers/tty/serial | |
| parent | af77c56aa35325daa2bc2bed5c2ebf169be61b86 (diff) | |
serial: 8250_bcm2835aux: Add missing clk_disable_unprepare()
The error path when get clock frequency fails in bcm2835aux_serial
driver does not correctly disable the clock.
This flaw was found using a static analysis tool "Hulk Robot", which
reported the following warning when analyzing linux-next/master:
drivers/tty/serial/8250/8250_bcm2835aux.c:
warning: clk_disable_unprepare_missing.cocci
The cocci script checks for the existence of clk_disable_unprepare()
paired with clk_prepare_enable().
Add the missing clk_disable_unprepare() to the error path.
Fixes: fcc446c8aa63 ("serial: 8250_bcm2835aux: Add ACPI support")
Reported-by: Hulk Robot <hulkci@huawei.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Guo Mengqi <guomengqi3@huawei.com>
Link: https://lore.kernel.org/r/20220715023312.37808-1-guomengqi3@huawei.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/tty/serial')
| -rw-r--r-- | drivers/tty/serial/8250/8250_bcm2835aux.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c b/drivers/tty/serial/8250/8250_bcm2835aux.c index 047e14ccb165..15a2387a5b25 100644 --- a/drivers/tty/serial/8250/8250_bcm2835aux.c +++ b/drivers/tty/serial/8250/8250_bcm2835aux.c @@ -167,8 +167,10 @@ static int bcm2835aux_serial_probe(struct platform_device *pdev) uartclk = clk_get_rate(data->clk); if (!uartclk) { ret = device_property_read_u32(&pdev->dev, "clock-frequency", &uartclk); - if (ret) - return dev_err_probe(&pdev->dev, ret, "could not get clk rate\n"); + if (ret) { + dev_err_probe(&pdev->dev, ret, "could not get clk rate\n"); + goto dis_clk; + } } /* the HW-clock divider for bcm2835aux is 8, |