diff options
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos7.dtsi | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index c3efbc8add38..3e53ff2be455 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -177,10 +177,11 @@ clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>, <&clock_topc DOUT_SCLK_BUS1_PLL>, <&clock_topc DOUT_SCLK_CC_PLL>, - <&clock_topc DOUT_SCLK_MFC_PLL>; + <&clock_topc DOUT_SCLK_MFC_PLL>, + <&clock_topc DOUT_SCLK_AUD_PLL>; clock-names = "fin_pll", "dout_sclk_bus0_pll", "dout_sclk_bus1_pll", "dout_sclk_cc_pll", - "dout_sclk_mfc_pll"; + "dout_sclk_mfc_pll", "dout_sclk_aud_pll"; }; clock_top1: clock-controller@105e0000 { @@ -218,12 +219,32 @@ compatible = "samsung,exynos7-clock-peric1"; reg = <0x14c80000 0xd00>; #clock-cells = <1>; - clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>, + clocks = <&fin_pll>, + <&clock_top0 DOUT_ACLK_PERIC1>, <&clock_top0 CLK_SCLK_UART1>, <&clock_top0 CLK_SCLK_UART2>, - <&clock_top0 CLK_SCLK_UART3>; - clock-names = "fin_pll", "dout_aclk_peric1_66", - "sclk_uart1", "sclk_uart2", "sclk_uart3"; + <&clock_top0 CLK_SCLK_UART3>, + <&clock_top0 CLK_SCLK_SPI0>, + <&clock_top0 CLK_SCLK_SPI1>, + <&clock_top0 CLK_SCLK_SPI2>, + <&clock_top0 CLK_SCLK_SPI3>, + <&clock_top0 CLK_SCLK_SPI4>, + <&clock_top0 CLK_SCLK_I2S1>, + <&clock_top0 CLK_SCLK_PCM1>, + <&clock_top0 CLK_SCLK_SPDIF>; + clock-names = "fin_pll", + "dout_aclk_peric1_66", + "sclk_uart1", + "sclk_uart2", + "sclk_uart3", + "sclk_spi0", + "sclk_spi1", + "sclk_spi2", + "sclk_spi3", + "sclk_spi4", + "sclk_i2s1", + "sclk_pcm1", + "sclk_spdif"; }; clock_peris: clock-controller@10040000 { |