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path:
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/
drivers
/
clk
/
clk-versaclock5.c
Age
Commit message (
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Author
2019-05-30
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157
Thomas Gleixner
2019-01-09
clk: vc5: Abort clock configuration without upstream clock
Marek Vasut
2018-12-15
clk: vc5: Add suspend/resume support
Marek Vasut
2017-07-17
clk: vc5: Add support for IDT VersaClock 5P49V5925
Vladimir Barinov
2017-07-17
clk: vc5: Add support for IDT VersaClock 5P49V6901
Marek Vasut
2017-07-17
clk: vc5: Add support for the input frequency doubler
Marek Vasut
2017-07-17
clk: vc5: Split clock input mux and predivider
Marek Vasut
2017-07-17
clk: vc5: Configure the output buffer input mux on prepare
Marek Vasut
2017-07-17
clk: vc5: Do not warn about disabled output buffer input muxes
Marek Vasut
2017-07-17
clk: vc5: Fix trivial typo
Marek Vasut
2017-07-17
clk: vc5: Prevent division by zero on unconfigured outputs
Marek Vasut
2017-04-19
clk: vc5: Add support for IDT VersaClock 5P49V5935
Alexey Firago
2017-04-19
clk: vc5: Add structure to describe particular chip features
Alexey Firago
2017-01-21
clk: vc5: Add support for IDT VersaClock 5P49V5923 and 5P49V5933
Marek Vasut