Age | Commit message (Expand) | Author |
---|---|---|
2020-01-05 | clocksource: riscv: add notrace to riscv_sched_clock | Zong Li |
2019-11-14 | riscv: add support for MMIO access to the timer registers | Christoph Hellwig |
2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig |
2019-09-05 | riscv: don't use the rdtime(h) pseudo-instructions | Christoph Hellwig |
2019-08-07 | RISC-V: Remove per cpu clocksource | Atish Patra |
2019-03-23 | clocksource/drivers/riscv: Fix clocksource mask | Atish Patra |
2019-02-23 | clocksource/drivers/riscv: Add required checks during clock source init | Atish Patra |
2018-12-19 | clocksource/drivers/riscv: Change name riscv_timer to timer-riscv | Daniel Lezcano |