github.com/torvalds/linux.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author
2022-02-09	cxl/core/port: Add endpoint decoders	Ben Widawsky
2022-02-09	cxl/mem: Add the cxl_mem driver	Ben Widawsky
2022-02-09	cxl/core/port: Add switch port enumeration	Dan Williams
2022-02-09	cxl/core/port: Remove @host argument for dport + decoder enumeration	Dan Williams
2022-02-09	cxl/port: Add a driver for 'struct cxl_port' objects	Ben Widawsky
2022-02-09	cxl/core/hdm: Add CXL standard decoder enumeration to the core	Dan Williams
2022-02-09	cxl/core: Generalize dport enumeration in the core	Dan Williams
2022-02-09	cxl/pmem: Introduce a find_cxl_root() helper	Dan Williams
2022-02-09	cxl/port: Introduce cxl_port_to_pci_bus()	Dan Williams
2022-02-09	cxl/core/port: Use dedicated lock for decoder target list	Dan Williams
2022-02-09	cxl: Prove CXL locking	Dan Williams
2022-02-09	cxl/core: Track port depth	Ben Widawsky
2022-02-09	cxl/core/port: Clarify decoder creation	Ben Widawsky
2022-02-09	cxl/core: Convert decoder range to resource	Ben Widawsky
2022-02-09	cxl: Introduce module_cxl_driver	Ben Widawsky
2022-02-09	cxl/acpi: Map component registers for Root Ports	Ben Widawsky
2022-01-05	cxl/core: Remove cxld_const_init in cxl_decoder_alloc()	Nathan Chancellor
2021-11-15	cxl/pmem: Fix module reload vs workqueue state	Dan Williams
2021-11-08	Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...	Linus Torvalds
2021-10-29	cxl/pci: Add @base to cxl_register_map	Dan Williams
2021-09-25	cxl/core: Replace unions with struct_group()	Kees Cook
2021-09-22	cxl/core: Split decoder setup into alloc + add	Dan Williams
2021-09-22	tools/testing/cxl: Introduce a mock memory device + driver	Dan Williams
2021-09-22	cxl/bus: Populate the target list at decoder create	Dan Williams
2021-09-21	tools/testing/cxl: Introduce a mocked-up CXL port hierarchy	Dan Williams
2021-09-21	cxl/pmem: Add support for multiple nvdimm-bridge objects	Dan Williams
2021-08-06	cxl/pci: Simplify register setup	Ben Widawsky
2021-06-16	cxl/pmem: Register 'pmem' / cxl_nvdimm devices	Dan Williams
2021-06-16	cxl/pmem: Add initial infrastructure for pmem support	Dan Williams
2021-06-16	cxl/core: Add cxl-bus driver infrastructure	Dan Williams
2021-06-12	cxl/hdm: Fix decoder count calculation	Ben Widawsky
2021-06-10	cxl/acpi: Introduce cxl_decoder objects	Dan Williams
2021-06-10	cxl/acpi: Add downstream port data to cxl_port instances	Dan Williams
2021-06-10	cxl/acpi: Introduce the root of a cxl_port topology	Dan Williams
2021-06-06	cxl/pci: Add HDM decoder capabilities	Ben Widawsky
2021-06-06	cxl/pci: Map registers based on capabilities	Ira Weiny
2021-05-15	cxl/core: Refactor CXL register lookup for bridge reuse	Dan Williams
2021-05-15	cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices	Dan Williams
2021-05-15	cxl/mem: Move some definitions to mem.h	Dan Williams
2021-02-17	cxl/mem: Enable commands via CEL	Ben Widawsky
2021-02-17	cxl/mem: Register CXL memX devices	Dan Williams
2021-02-17	cxl/mem: Find device capabilities	Ben Widawsky