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AgeCommit message (Collapse)Author
2023-12-20Merge LACE/NoLACE under OSCE frameworkopus-ng-lace-integration5Jan Buethe
2023-12-15use opus_(re)alloc and opus_free for dnn and DRED related functionsopus-ng-fix-allocMichael Klingbeil
2023-11-30don't redefine _mm_loadu_si32 on MSVCMichael Klingbeil
2023-11-29Trying to fix/update meson buildJean-Marc Valin
Still don't quite know what I'm doing
2023-11-28Oops, fix the fixed-point buildJean-Marc Valin
2023-11-28Fixes for ARMv7/AArch32Jean-Marc Valin
1) Enable asm/intrinsics even for floating-point 2) Make sure ARMv8 asimd enables EDSP/MEDIA/Neon 3) Add dotp architecture to rtcd table since AArch *can* have dotp
2023-11-21Add rtcd for silk_inner_product_FLP()Jean-Marc Valin
2023-11-21Start enabling AVX2 silk_inner_product_FLP()Jean-Marc Valin
Not yet with rtcd
2023-11-21Avoids AVX2 optimizations being disabledJean-Marc Valin
2023-11-21Misc fixes on previous patchJean-Marc Valin
Fixes warnings, undefined behaviour, and check-asm failure
2023-11-21Optimize NSQ_del_dec() for AVX2Victor Ding
The optimization is bit-exact with C function. This optimization speeds up SILK encoder (floating point) as following: AMD Zen: Complexity 0-5 : 0% Complexity 6-7 : 3 - 7% Complexity 8-10: 8 - 15% Intel Skylake: Complexity 0-5 : 0% Complexity 6-7 : 14 - 18% Complexity 8-10: 17 - 22% Adapted by Jean-Marc Valin
2023-11-21AVX2 version of silk_inner_product_FLP()Jean-Marc Valin
Not hooked up
2023-11-18Speed up silk_warped_autocorrelation_FLP()Jean-Marc Valin
Reducing the dependency chain between tmp1 and tmp2 at the cost of an extra multiply.
2023-11-16Remove C99 commentJean-Marc Valin
2023-11-16Adding RTCD for compute_activation()exp_dnn_rtcd6Jean-Marc Valin
2023-11-16Adding RTCD for DNN codeJean-Marc Valin
Starting with compute_linear()
2023-11-15Using sparse GRUs in DRED decoderJean-Marc Valin
Saves ~270 kB of weights in the decoder
2023-11-08DRED: quantize scale and dead zone to 8 bitsJean-Marc Valin
2023-11-07DRED code cleanupJean-Marc Valin
Removing some indirections
2023-11-07Split stats in two and remove useless dimensionsJean-Marc Valin
2023-11-06DRED: quantize r and p0 parameters with 8 bitsJean-Marc Valin
Only code non-degenerate symbols, which makes the encoder faster
2023-11-06Vectorize DRED quantizationJean-Marc Valin
2023-11-04Match silenced overflow checks in the sse4.1 versionFelicia Lim
Update silk/x86/NSQ_del_dec_sse4_1.c to match the remaining silk/NSQ_del_dec.c changes made in https://gitlab.xiph.org/xiph/opus/-/commit/c913dc38 Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>
2023-11-03Silence some overflow checksFelicia Lim
Co-authored-by: James Zern <jzern@google.com>
2023-10-30Don't try to use models that aren't loadedJean-Marc Valin
2023-10-30Don't use reserved identifiers for include guardsJean-Marc Valin
2023-10-30Update blob loading codeJean-Marc Valin
2023-10-21CleanupJean-Marc Valin
2023-10-19Support OPUS_SET_COMPLEXITY() on decoder sideJean-Marc Valin
Controls whether deep PLC is enabled
2023-10-18Don't call the libm tanh()Jean-Marc Valin
2023-10-18Making the build possible without the modelsJean-Marc Valin
No dependency on the data files if no DNN code enabled
2023-10-15Rename ENABLE_NEURAL_FED to ENABLE_DREDJean-Marc Valin
Signed-off-by: Jean-Marc Valin <jmvalin@amazon.com>
2023-10-15Rename NEURAL_PLC to ENABLE_DEEP_PLCJean-Marc Valin
Signed-off-by: Jean-Marc Valin <jmvalin@amazon.com>
2023-10-08Fix warning from casting between 1D and 2D arraysJean-Marc Valin
2023-10-08Silencing alignment warnings on x86 intrinsicsJean-Marc Valin
Those intrinsics don't actually require alignment so we're OK
2023-10-06New model with wider range of bitratesJean-Marc Valin
Using a max lambda of 0.04
2023-10-06Switching to neural pitch estimatorJean-Marc Valin
Remove old pitch estimator and retrain all models
2023-10-02update modelJean-Marc Valin
2023-09-28Fix stats indexing for stateJean-Marc Valin
2023-09-26RDOVAE model updateJean-Marc Valin
2023-09-24Infinite loops are badJean-Marc Valin
2023-09-21Handle the case where the initial state didn't fitJean-Marc Valin
2023-09-21Quantizing initial state with rdovae tooJean-Marc Valin
More efficient than PVQ
2023-08-10Changing DRED exp. ID so we can reserve 127Jean-Marc Valin
There was a suggestion to use 127 for extending the extension ID space
2023-08-10Making it easier to remove DRED experimental IDJean-Marc Valin
When ready, change DRED_EXTENSION_ID to the final ID, remove DRED_EXPERIMENTAL_VERSION completely, and change DRED_EXPERIMENTAL_BYTES to zero (eventually remove it).
2023-07-28Make RDOVAE encoder use LinearLayer directlyopus-ng-linear4Jean-Marc Valin
2023-07-13Make "VBR with cap" less aggressiveJean-Marc Valin
The bits we don't use won't be wasted, so it's less important to get exactly the optimal number of bits below the cap.
2023-07-13Some general SILK CBR tuningJean-Marc Valin
The gain*2 when overshooting was too aggressive and the undershoot case wasn't aggressive enough. This now seems to work reasonably well.
2023-07-12Fix DRED/neural PLC for SILK stereoJean-Marc Valin
Don't attempt to run the neural PLC on the side channel since we only have one state.
2023-07-03Properly compute and use the DRED offset fieldJean-Marc Valin
Also, don't code DRED that's redundant with the main packet
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 22:18:11 +0300