diff options
| -rw-r--r-- | ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/avr.h | 13 |
2 files changed, 12 insertions, 6 deletions
@@ -1,3 +1,8 @@ +2013-06-01 George Thomas <george.thomas@atmel.com> + + * include/opcode/avr.h: Rename AVR_ISA_XCH to AVR_ISA_RMW. Remove + from AVR_ISA_XMEGA and add new AVR_ISA_XMEGAU + 2013-05-06 Sandra Loosemore <sandra@codesourcery.com> * COPYING.NEWLIB: Add Altera Corporation copyright. diff --git a/include/opcode/avr.h b/include/opcode/avr.h index 6e86c07ba..f1d73ad92 100644 --- a/include/opcode/avr.h +++ b/include/opcode/avr.h @@ -33,7 +33,7 @@ #define AVR_ISA_MOVW 0x1000 /* device has MOVW */ #define AVR_ISA_SPMX 0x2000 /* device has SPM Z[+] */ #define AVR_ISA_DES 0x4000 /* device has DES */ -#define AVR_ISA_XCH 0x8000 /* device has XCH, LAC, LAS, LAT */ +#define AVR_ISA_RMW 0x8000 /* device has RMW instructions XCH,LAC,LAS,LAT */ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) @@ -53,7 +53,8 @@ #define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) #define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) #define AVR_ISA_M256 (AVR_ISA_M128 | AVR_ISA_EIND) -#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES | AVR_ISA_XCH) +#define AVR_ISA_XMEGA (AVR_ISA_M256 | AVR_ISA_SPMX | AVR_ISA_DES) +#define AVR_ISA_XMEGAU (AVR_ISA_XMEGA | AVR_ISA_RMW) #define AVR_ISA_AVR1 AVR_ISA_TINY1 #define AVR_ISA_AVR2 AVR_ISA_2xxx @@ -266,10 +267,10 @@ AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) /* Atomic memory operations for XMEGA. List before `sts'. */ -AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_XCH, 0x9204) -AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_XCH, 0x9205) -AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_XCH, 0x9206) -AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_XCH, 0x9207) +AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204) +AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205) +AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206) +AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207) /* Known to be decoded as `nop' by the old core. */ AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) |