Updating Vector<T> to support nint and nuint (#50832)

* Refactoring GenTreeJitIntrinsic to expose SimdSize and SimdBaseType via methods

* Updating the JIT to pass through the CORINFO_TYPE for hardware intrinsics

* Adding support for Vector<nint> and Vector<nuint> to managed code

* Updating the vector tests to cover nint and nuint

* Recognize Vector<nint> and Vector<nuint> in the JIT

* Updating Vector64/128/256<T> NotSupportedTest metadata to include type name

* Updating the Vector64/128/256<T> tests to have NotSupported validation for nint/nuint

* Splitting ThrowHelper.ThrowForUnsupportedVectorBaseType into separate functions for Numerics vs Intrinsics

* Updating Utf16Utility.Validation to directly use Vector<nuint>

* Don't use the auxiliary type to hold a SIMD type, since it can be trivially pulled from the operand instead

* Split the mono handling for ThrowForUnsupportedVectorBaseType into ThrowForUnsupportedNumericsVectorBaseType and ThrowForUnsupportedIntrinsicsVectorBaseType

* Add basic handling for MONO_TYPE_I and MONO_TYPE_U to simd-intrinsics.c

* Ensure simd-intrinsics.c in Mono handles `MONO_TYPE_I` and `MONO_TYPE_U` on relevant code paths

* Ensure we don't assert when encountering synthesized Vector128<nint> handles

* Applying formatting patch

* Fix the handling for Crc32 and Crc32C on ARM64

* Updating Mono mini-amd64 to handle MONO_TYPE_I and MONO_TYPE_U for SIMD operations

* Handle OP_XCOMPARE.CMP_GE_UN for MONO_TYPE_U

* Handle MONO_TYPE_I and MONO_TYPE_U for Vector types in mini-llvm

1 files changed, 19 insertions, 5 deletions

diff --git a/src/coreclr/jit/lsraarm64.cpp b/src/coreclr/jit/lsraarm64.cpp
index d9aa71da582..d7b51ff42bb 100644
--- a/src/coreclr/jit/lsraarm64.cpp
+++ b/src/coreclr/jit/lsraarm64.cpp
@@ -871,9 +871,9 @@ int LinearScan::BuildSIMD(GenTreeSIMD* simdTree)
 
         case SIMDIntrinsicInitN:
         {
-            var_types baseType = simdTree->gtSIMDBaseType;
-            srcCount           = (short)(simdTree->gtSIMDSize / genTypeSize(baseType));
-            if (varTypeIsFloating(simdTree->gtSIMDBaseType))
+            var_types baseType = simdTree->GetSimdBaseType();
+            srcCount           = (short)(simdTree->GetSimdSize() / genTypeSize(baseType));
+            if (varTypeIsFloating(simdTree->GetSimdBaseType()))
             {
                 // Need an internal register to stitch together all the values into a single vector in a SIMD reg.
                 buildInternalFloatRegisterDefForNode(simdTree);
@@ -978,13 +978,27 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree)
 
         if (intrin.category == HW_Category_SIMDByIndexedElement)
         {
-            const unsigned int indexedElementSimdSize = genTypeSize(intrinsicTree->GetAuxiliaryType());
+            var_types indexedElementOpType;
+
+            if (intrin.numOperands == 3)
+            {
+                indexedElementOpType = intrin.op2->TypeGet();
+            }
+            else
+            {
+                assert(intrin.numOperands == 4);
+                indexedElementOpType = intrin.op3->TypeGet();
+            }
+
+            assert(varTypeIsSIMD(indexedElementOpType));
+
+            const unsigned int indexedElementSimdSize = genTypeSize(indexedElementOpType);
             HWIntrinsicInfo::lookupImmBounds(intrin.id, indexedElementSimdSize, intrin.baseType, &immLowerBound,
                                              &immUpperBound);
         }
         else
         {
-            HWIntrinsicInfo::lookupImmBounds(intrin.id, intrinsicTree->gtSIMDSize, intrin.baseType, &immLowerBound,
+            HWIntrinsicInfo::lookupImmBounds(intrin.id, intrinsicTree->GetSimdSize(), intrin.baseType, &immLowerBound,
                                              &immUpperBound);
         }