diff options
Diffstat (limited to 'src/coreclr/jit/lsraarm64.cpp')
| -rw-r--r-- | src/coreclr/jit/lsraarm64.cpp | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/src/coreclr/jit/lsraarm64.cpp b/src/coreclr/jit/lsraarm64.cpp index d9aa71da582..d7b51ff42bb 100644 --- a/src/coreclr/jit/lsraarm64.cpp +++ b/src/coreclr/jit/lsraarm64.cpp @@ -871,9 +871,9 @@ int LinearScan::BuildSIMD(GenTreeSIMD* simdTree) case SIMDIntrinsicInitN: { - var_types baseType = simdTree->gtSIMDBaseType; - srcCount = (short)(simdTree->gtSIMDSize / genTypeSize(baseType)); - if (varTypeIsFloating(simdTree->gtSIMDBaseType)) + var_types baseType = simdTree->GetSimdBaseType(); + srcCount = (short)(simdTree->GetSimdSize() / genTypeSize(baseType)); + if (varTypeIsFloating(simdTree->GetSimdBaseType())) { // Need an internal register to stitch together all the values into a single vector in a SIMD reg. buildInternalFloatRegisterDefForNode(simdTree); @@ -978,13 +978,27 @@ int LinearScan::BuildHWIntrinsic(GenTreeHWIntrinsic* intrinsicTree) if (intrin.category == HW_Category_SIMDByIndexedElement) { - const unsigned int indexedElementSimdSize = genTypeSize(intrinsicTree->GetAuxiliaryType()); + var_types indexedElementOpType; + + if (intrin.numOperands == 3) + { + indexedElementOpType = intrin.op2->TypeGet(); + } + else + { + assert(intrin.numOperands == 4); + indexedElementOpType = intrin.op3->TypeGet(); + } + + assert(varTypeIsSIMD(indexedElementOpType)); + + const unsigned int indexedElementSimdSize = genTypeSize(indexedElementOpType); HWIntrinsicInfo::lookupImmBounds(intrin.id, indexedElementSimdSize, intrin.baseType, &immLowerBound, &immUpperBound); } else { - HWIntrinsicInfo::lookupImmBounds(intrin.id, intrinsicTree->gtSIMDSize, intrin.baseType, &immLowerBound, + HWIntrinsicInfo::lookupImmBounds(intrin.id, intrinsicTree->GetSimdSize(), intrin.baseType, &immLowerBound, &immUpperBound); } |