diff options
| author | Mykola Hohsdze <Mykola_Hohsadze@epam.com> | 2022-08-04 22:01:47 +0300 |
|---|---|---|
| committer | Mizux <mizux.dev@gmail.com> | 2022-08-04 22:56:32 +0300 |
| commit | c6b0a803a879105f997ddbab80506c2978cd7980 (patch) | |
| tree | dcedf0369748b4154c547070e0b1f1495c271517 | |
| parent | cbc8f9c7a37db9169f8c361fba42b7eace7fdc3d (diff) | |
Add AVX_VNNI
| -rw-r--r-- | include/cpuinfo_x86.h | 2 | ||||
| -rw-r--r-- | src/impl_x86__base_implementation.inl | 2 | ||||
| -rw-r--r-- | test/cpuinfo_x86_test.cc | 18 |
3 files changed, 22 insertions, 0 deletions
diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 197432f..a483d09 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -60,6 +60,7 @@ typedef struct { int sse4a : 1; int avx : 1; + int avx_vnni : 1; int avx2 : 1; int avx512f : 1; @@ -215,6 +216,7 @@ typedef enum { X86_SSE4_2, X86_SSE4A, X86_AVX, + X86_AVX_VNNI, X86_AVX2, X86_AVX512F, X86_AVX512CD, diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index b719a64..12bc918 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -342,6 +342,7 @@ static void ParseCpuId(const Leaves* leaves, X86Info* info, if (os_preserves->avx_registers) { features->fma3 = IsBitSet(leaf_1.ecx, 12); features->avx = IsBitSet(leaf_1.ecx, 28); + features->avx_vnni = IsBitSet(leaf_7_1.eax, 4); features->avx2 = IsBitSet(leaf_7.ebx, 5); } if (os_preserves->avx512_registers) { @@ -1729,6 +1730,7 @@ CacheInfo GetX86CacheInfo(void) { LINE(X86_SSE4_2, sse4_2, , , ) \ LINE(X86_SSE4A, sse4a, , , ) \ LINE(X86_AVX, avx, , , ) \ + LINE(X86_AVX_VNNI, avx_vnni, , , ) \ LINE(X86_AVX2, avx2, , , ) \ LINE(X86_AVX512F, avx512f, , , ) \ LINE(X86_AVX512CD, avx512cd, , , ) \ diff --git a/test/cpuinfo_x86_test.cc b/test/cpuinfo_x86_test.cc index 2e34d12..1c66314 100644 --- a/test/cpuinfo_x86_test.cc +++ b/test/cpuinfo_x86_test.cc @@ -828,6 +828,24 @@ TEST_F(CpuidX86Test, AMD_K18_ZEN_DHYANA_OCTAL_CORE_C86_3250) { EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::AMD_ZEN); } +// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00906A4_AlderLakeP_00_CPUID.txt +TEST_F(CpuidX86Test, INTEL_ALDER_LAKE_AVX_VNNI) { + cpu().SetOsBackupsExtendedRegisters(true); + cpu().SetLeaves({ + {{0x00000000, 0}, Leaf{0x00000020, 0x756E6547, 0x6C65746E, 0x49656E69}}, + {{0x00000001, 0}, Leaf{0x000906A4, 0x00400800, 0x7FFAFBBF, 0xBFEBFBFF}}, + {{0x00000007, 0}, Leaf{0x00000001, 0x239CA7EB, 0x984007AC, 0xFC18C410}}, + {{0x00000007, 1}, Leaf{0x00400810, 0x00000000, 0x00000000, 0x00000000}}, + }); + const auto info = GetX86Info(); + + EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL); + EXPECT_EQ(info.family, 0x06); + EXPECT_EQ(info.model, 0x9A); + EXPECT_TRUE(info.features.avx_vnni); + EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ADL); +} + // https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00106A1_Nehalem_CPUID.txt TEST_F(CpuidX86Test, Nehalem) { // Pre AVX cpus don't have xsave |