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2022-11-08Add Intel Raptor Lake uarch detection (#283)Mykola Hohsadze
2022-11-02S390X Support (#274)marquitos0119
* support for s390x * added z15 T01, T02 model checking * removed z15 checking * removed empty strings * added s390x unit tests * added reference url for hwcaps * moved documentation to S390XFeatures struct, updated copyright date, removed unused include statement * changed num_processors to int * removed newlines from test inputs * scripts: Add bootlin s390x support * cmake(ci): Add s390x support * ci: Add s390x workflow Co-authored-by: Marcos <marcos.araque.fiallos@ibm.com> Co-authored-by: Corentin Le Molgat <corentinl@google.com>
2022-10-26Add REP instructions detection (#282)Mykola Hohsadze
2022-10-25Add X86 movdir detection (#281)Mykola Hohsadze
2022-10-24Add X86 GFNI detectionMykola Hohsdze
2022-10-20add x86/avx512_fp16 detection (#279)damageboy
fixes #278
2022-10-19Add AMD ZEN4 Raphael detection (#277)Mykola Hohsadze
2022-10-19add mobile core flavor (#266)Andrei Kurushin
2022-09-19Replace hardcoded cache type value to enum type for X86 tests (#270)Mykola Hohsadze
Replaced hardcoded integer values of cache type to `CacheType` values for X86 tests and added declaration `CacheType` for `P4_CacheInfo` test
2022-09-19Add support for detecting Intel CascadeLake CPUs (#271)William Tambellini
Should close https://github.com/google/cpu_features/issues/260
2022-08-18Add cache detection for old AMD processors (#199)Mykola Hohsadze
* Add cache detection for of old AMD processors update links * Add documentation link for cache_size * 512 * Update legacy amd cache detection
2022-08-18add amd cato (#267)Andrei Kurushin
* add AMD RX-8125, RX-8120, and A9-9820 detection
2022-08-08add intel goldmont plus (#256)Andrei Kurushin
* add intel goldmont plus (INTEL_ATOM_GMT_PLUS)
2022-08-05add amd piledriver 0x10 model (#255)Andrei Kurushin
* add amd piledriver 0x10 model
2022-08-05add CometLake model 166Andrew Kurushin
2022-08-05Replace hardcode values to constantsMykola Hohsdze
2022-08-04Add AVX_VNNIMykola Hohsdze
2022-08-04add LakefieldAndrew Kurushin
2022-08-04add intel Tremont microarchAndrew Kurushin
2022-07-28test enum macro consistency (#257)Andrei Kurushin
2022-07-28Add detection LZCNT (#254)Mykola Hohsadze
Fixes #253
2022-07-25remove internal FillX86BrandString usage (#258)Andrei Kurushin
2022-07-21add comet lake unit test #248 (#250)Andrei Kurushin
2022-07-21add windows ssse3,sse4_1,sse4_2 detection for non avx path (#251)Andrei Kurushin
* add windows ssse3,sse4_1,sse4_2 detection for non avx path * remove special WESTMERE case * move windows conditional redefinition to separate header * fix minor issues
2022-06-17Add AMD ZEN 4 uarch and update detection (#243)Mykola Hohsadze
* Add AMD ZEN 4 uarch and update detection * Add tests via cpuid dump
2022-06-01Added some MIPS features. (#241)michael-roe
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-04-27Update AArch64 features to Linux 5.17. (#237)Tamas Zsoldos
2022-02-22replace sse3 detection with pni when reading /proc/cpuinfo (#225)jmfriedt
2022-02-01Fix a getauxval comment and expand the Krait idiv workaround (#206)Ryan Prichard
* Fix getauxval comment (API 18 not 20) getauxval is available in Android starting with API 18, not 20. The comment about __ANDROID_API__ appears to have been copied from the NDK's cpufeatures, which always uses dlopen/dlsym and doesn't assume it can directly call getauxval, even if __ANDROID_API__ is new enough. With this project, though, when __ANDROID_API__ is 18 or up, the CMakeLists.txt file would detect that getauxval is available and define HAVE_STRONG_GETAUXVAL. * Broaden Qualcomm Krait idiv workaround Some Qualcomm Krait CPUs have IDIV support but the kernel doesn't report it. Previously, this code looked for two CPUs: - 0x510006F2 (0x51/'Q', variant 0, part 0x06f, rev 2) - 0x510006F3 (0x51/'Q', variant 0, part 0x06f, rev 3) This check misses my 2013 Nexus 7 device, which has this CPU ID: - 0x511006f0 (0x51/'Q', variant 1, part 0x06f, rev 0) My Nexus 7 device doesn't report idiv through AT_HWCAP or through /proc/cpuinfo (AT_HWCAP is 0x1b0d7). Expand the check to anything with: - implementer 0x51 - architecture 7 - part 0x4d or 0x6f Part 0x4d appears to be a dual-core Krait (e.g. see https://crbug.com/341598#c43). This new matching behavior is a subset of what the upstream kernel does (patch[1] contributed by CodeAurora), and also closely matches the behavior of pytorch/cpuinfo. [1] https://github.com/torvalds/linux/commit/120ecfafabec382c4feb79ff159ef42a39b6d33b
2022-01-31Fix list_cpu_features.exe does not detect SSE42 on Xeon X5650 (Windows) (#220)Mykola Hohsadze
2022-01-14[x86] Embed brand_string and mark FillX86BrandString as deprecated (#214)Guillaume Chatelet
2021-10-29Update uarch detection for Intel processors (#184)Nikolay Hohsadze
2021-10-28New code layout - breaking change in cpu_features_macros.h (#194)Guillaume Chatelet
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch. Note: this patch contains breaking changes in `include/cpu_features_macros.h` - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`) - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
2021-10-20Fixes wrong cache detection of old processors (#183)Guillaume Chatelet
2021-10-20[NFC] encapsulate fake cpu instance in x86 testGuillaume Chatelet
2021-10-18Add cache info for new AMD CPUs (0x8000001D) (#171)Nikolay Hohsadze
2021-10-18Add separator to CpuFeatures_StringView_HasWord (#174)Guillaume Chatelet
2021-07-02Add support for FreeBSD on x86 (#163)Guillaume Chatelet
2021-06-30CPU features for AMD (#165)Nikolay Hohsadze
2021-06-30Avoid leaking internal headers for ppc (#164)Guillaume Chatelet
2021-05-21Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157)Kris Kwiatkowski
2020-12-15Update AArch64 features to Linux 5.10 (#149)Tamas Zsoldos
Added feature: MTE.
2020-10-12[NFC] Generate separate tables via macro (#137)Guillaume Chatelet
This is a non functional change, it allows: - Getting rid of `unix_features_aggregator` - Have a single blob describing the features - Fix wrong mocking of `hwcaps` Downside: abuse of macros makes the code slightly magical and harder to understand. It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
2020-10-12[NFC] Update copyright from Google Inc. to Google LLCGuillaume Chatelet
2020-10-09Remove need for utsname (#136)Guillaume Chatelet
2020-10-09Fix SSE detection on non-AVX CPUs (#135)Guillaume Chatelet
Fixes #4. This is based on #115 with a few modifications: - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation, - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2, - Added tests for Atom, Nehalem, and P3 processors, Thx to @gadoofou87 for providing the original PR. It also removes the need for #92 * Fix SSE detection on non-AVX CPUs * Fixes typo * Mock OSX sysctlbyname in tests * Also update other tests * FakeCpu is reset between each tests * Fix conflicting name on Windows * Disable pre AVX cpu sse detection tests on Windows * Guard OS specific code with macros * Fix missing import for tests * Fix wrong function prototype * Fix wrong mocking of P3 on Windows * Completely guard OS specific parts in x86 tests * Store DWORD instead unsigned long for x86 tests
2020-09-23[NFC] clang-format codebase (#134)Guillaume Chatelet
* [NFC] clang-format codebase * revert to 80 char columns at the price of uglier table init * Specifically disabling clang-format for table initialization
2020-09-21detect future Intel AVX/AMX features (#124)Jeff Hammond
* add Ice Lake Server and Sapphire Rapids models The information contained in this commit was obtained from "Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com> * Tiger Lake; Ice Lake NNP-I; SPR string Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com> * add AVX512_BF16 and AVX512_VP2INTERSECT detection Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com> * correction for KNM features: s/4VBMI2/4FMAPS/g Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com> * add AMX/TMUL bits from 319433-040 Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com> * add Intel copyright Fixes #128
2020-09-21Update features for AArch64 to Linux 5.8 (#122)Tamas Zsoldos
This adds the following features: dcpodp, sve2, sveaes, svepmull, svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm, svef64mm, svebf16, i8mm, bf16, dgh and rng. With these, all features used by Linux 5.8 on AArch64 is supported. Fixes #126
2020-09-21Add more test cases for the string view (#119)Henry Lee
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 08:12:16 +0300