diff options
| author | Icenowy Zheng <icenowy@aosc.io> | 2018-01-13 14:59:47 +0300 |
|---|---|---|
| committer | Andre Przywara <osp@andrep.de> | 2022-03-06 03:48:11 +0300 |
| commit | 0512f4d9164ed928bd374376fd375e35af6be483 (patch) | |
| tree | 2f63ad32adf0ecc914dea8ec277dcea1d1f36a15 | |
| parent | 4fb307f1e4441b8fc3e24fa7dd0633b4572fe694 (diff) | |
fel: ignore more bits in SCTLR
Some bits are not meaningful both in ARMv5 and ARMv7/8, however they're
read as 0 in ARMv5 but 1 in ARMv7/8.
Ignore them.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Andre Przywara <osp@andrep.de>
| -rw-r--r-- | fel.c | 9 |
1 files changed, 7 insertions, 2 deletions
@@ -623,9 +623,14 @@ uint32_t *aw_backup_and_disable_mmu(feldev_handle *dev, * checks needs to be relaxed). */ - /* Basically, ignore M/Z/I/V/UNK bits and expect no TEX remap */ + /* + * Basically, ignore M/Z/I/V/UNK bits and expect no TEX remap. + * Bits [23:22] are Read-As-One on ARMv7, but Should-Be-Zero + * on ARMv5, so ignore them. + * We need the RES1 bits[18,16,4,3] and CP15BEN[5]. + */ sctlr = aw_get_sctlr(dev, soc_info); - if ((sctlr & ~((0x7 << 11) | (1 << 6) | 1)) != 0x00C50038) + if ((sctlr & ~((0x3 << 22) | (0x7 << 11) | (1 << 6) | 1)) != 0x00050038) pr_fatal("Unexpected SCTLR (%08X)\n", sctlr); if (!(sctlr & 1)) { |