diff options
| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-11-13 12:34:19 +0300 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2022-11-13 12:34:27 +0300 |
| commit | 4e0d2f8e6f140573fbe527b65be99f3347b94155 (patch) | |
| tree | c518dcad96efe90de45c6cf2bd15430bd8b75e69 | |
| parent | ff1ebcc5fe19c7f9a3da9d505e66f07ac89700b4 (diff) | |
[X86] Fix sched class typo - the CVTPD2DQrr instructions were mapping to ZnWriteCVTDQ2PDr instead of ZnWriteCVTPD2DQr
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleZnver1.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 705100d85f36..1185d5f5ca07 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -1233,7 +1233,7 @@ def ZnWriteCVTPD2DQr: SchedWriteRes<[ZnFPU12, ZnFPU3]> { } // CVT(T)PD2DQ. // x,x. -def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V?)CVT(T?)PD2DQrr")>; +def : InstRW<[ZnWriteCVTPD2DQr], (instregex "(V?)CVT(T?)PD2DQrr")>; def ZnWriteCVTPD2DQLd: SchedWriteRes<[ZnAGU,ZnFPU12,ZnFPU3]> { let Latency = 12; |