diff options
author | Amir Ayupov <aaupov@fb.com> | 2022-05-12 02:23:27 +0300 |
---|---|---|
committer | Amir Ayupov <aaupov@fb.com> | 2022-05-12 02:23:44 +0300 |
commit | d63c5a38fe0d06148a5881e3c51472f50d9a397b (patch) | |
tree | 3e60ded3c4f32eab7caecb2154b46b5e37b83f01 /bolt | |
parent | 91d5bfdb7996b353097c886128fc984e310f7122 (diff) |
[BOLT][NFC] Use BitVector::set_bits
Refactor and use `set_bits` BitVector interface.
Reviewed By: rafauler
Differential Revision: https://reviews.llvm.org/D125374
Diffstat (limited to 'bolt')
-rw-r--r-- | bolt/include/bolt/Passes/ReorderUtils.h | 6 | ||||
-rw-r--r-- | bolt/lib/Passes/DataflowAnalysis.cpp | 8 | ||||
-rw-r--r-- | bolt/lib/Passes/RegReAssign.cpp | 10 | ||||
-rw-r--r-- | bolt/lib/Passes/ShrinkWrapping.cpp | 10 | ||||
-rw-r--r-- | bolt/lib/Passes/StokeInfo.cpp | 4 | ||||
-rw-r--r-- | bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp | 4 |
6 files changed, 16 insertions, 26 deletions
diff --git a/bolt/include/bolt/Passes/ReorderUtils.h b/bolt/include/bolt/Passes/ReorderUtils.h index ffebb58f320e..bc82b4f436fa 100644 --- a/bolt/include/bolt/Passes/ReorderUtils.h +++ b/bolt/include/bolt/Passes/ReorderUtils.h @@ -36,8 +36,7 @@ public: } template <typename F> void forAllAdjacent(const Cluster *C, F Func) { - for (int I = Bits[C->id()].find_first(); I != -1; - I = Bits[C->id()].find_next(I)) + for (int I : Bits[C->id()].set_bits()) Func(Clusters[I]); } @@ -48,8 +47,7 @@ public: Bits[A->id()][A->id()] = false; Bits[A->id()][B->id()] = false; Bits[B->id()][A->id()] = false; - for (int I = Bits[B->id()].find_first(); I != -1; - I = Bits[B->id()].find_next(I)) { + for (int I : Bits[B->id()].set_bits()) { Bits[I][A->id()] = true; Bits[I][B->id()] = false; } diff --git a/bolt/lib/Passes/DataflowAnalysis.cpp b/bolt/lib/Passes/DataflowAnalysis.cpp index d5e09f956b31..02029ded0a8e 100644 --- a/bolt/lib/Passes/DataflowAnalysis.cpp +++ b/bolt/lib/Passes/DataflowAnalysis.cpp @@ -25,14 +25,14 @@ raw_ostream &operator<<(raw_ostream &OS, const BitVector &State) { OS << "all, except: "; BitVector BV = State; BV.flip(); - for (int I = BV.find_first(); I != -1; I = BV.find_next(I)) { + for (int I : BV.set_bits()) { OS << Sep << I; Sep = " "; } OS << ")"; return OS; } - for (int I = State.find_first(); I != -1; I = State.find_next(I)) { + for (int I : State.set_bits()) { OS << Sep << I; Sep = " "; } @@ -83,11 +83,11 @@ void RegStatePrinter::print(raw_ostream &OS, const BitVector &State) const { OS << "all, except: "; BitVector BV = State; BV.flip(); - for (int I = BV.find_first(); I != -1; I = BV.find_next(I)) + for (int I : BV.set_bits()) OS << BC.MRI->getName(I) << " "; return; } - for (int I = State.find_first(); I != -1; I = State.find_next(I)) + for (int I : State.set_bits()) OS << BC.MRI->getName(I) << " "; } diff --git a/bolt/lib/Passes/RegReAssign.cpp b/bolt/lib/Passes/RegReAssign.cpp index ce12da6fa5ee..a2eb5a9dc8d2 100644 --- a/bolt/lib/Passes/RegReAssign.cpp +++ b/bolt/lib/Passes/RegReAssign.cpp @@ -224,8 +224,7 @@ void RegReAssign::aggressivePassOverFunction(BinaryFunction &Function) { // analysis passes bool Bail = true; int64_t LowScoreClassic = std::numeric_limits<int64_t>::max(); - for (int J = ClassicRegs.find_first(); J != -1; - J = ClassicRegs.find_next(J)) { + for (int J : ClassicRegs.set_bits()) { if (RegScore[J] <= 0) continue; Bail = false; @@ -239,7 +238,7 @@ void RegReAssign::aggressivePassOverFunction(BinaryFunction &Function) { Extended &= GPRegs; Bail = true; int64_t HighScoreExtended = 0; - for (int J = Extended.find_first(); J != -1; J = Extended.find_next(J)) { + for (int J : Extended.set_bits()) { if (RegScore[J] <= 0) continue; Bail = false; @@ -326,8 +325,7 @@ bool RegReAssign::conservativePassOverFunction(BinaryFunction &Function) { // Try swapping R12, R13, R14 or R15 with RBX (we work with all callee-saved // regs except RBP) MCPhysReg Candidate = 0; - for (int J = ExtendedCSR.find_first(); J != -1; - J = ExtendedCSR.find_next(J)) + for (int J : ExtendedCSR.set_bits()) if (RegScore[J] > RegScore[Candidate]) Candidate = J; @@ -337,7 +335,7 @@ bool RegReAssign::conservativePassOverFunction(BinaryFunction &Function) { // Check if our classic callee-saved reg (RBX is the only one) has lower // score / utilization rate MCPhysReg RBX = 0; - for (int I = ClassicCSR.find_first(); I != -1; I = ClassicCSR.find_next(I)) { + for (int I : ClassicCSR.set_bits()) { int64_t ScoreRBX = RegScore[I]; if (ScoreRBX <= 0) continue; diff --git a/bolt/lib/Passes/ShrinkWrapping.cpp b/bolt/lib/Passes/ShrinkWrapping.cpp index 0e4e1504766f..f150965a67e0 100644 --- a/bolt/lib/Passes/ShrinkWrapping.cpp +++ b/bolt/lib/Passes/ShrinkWrapping.cpp @@ -729,7 +729,7 @@ void ShrinkWrapping::classifyCSRUses() { BitVector BV = BitVector(BC.MRI->getNumRegs(), false); BC.MIB->getTouchedRegs(Inst, BV); BV &= CSA.CalleeSaved; - for (int I = BV.find_first(); I != -1; I = BV.find_next(I)) { + for (int I : BV.set_bits()) { if (I == 0) continue; if (CSA.getSavedReg(Inst) != I && CSA.getRestoredReg(Inst) != I) @@ -739,7 +739,7 @@ void ShrinkWrapping::classifyCSRUses() { continue; BV = CSA.CalleeSaved; BV &= FPAliases; - for (int I = BV.find_first(); I > 0; I = BV.find_next(I)) + for (int I : BV.set_bits()) UsesByReg[I].set(DA.ExprToIdx[&Inst]); } } @@ -802,8 +802,7 @@ void ShrinkWrapping::computeSaveLocations() { continue; BitVector BBDominatedUses = BitVector(DA.NumInstrs, false); - for (int J = UsesByReg[I].find_first(); J > 0; - J = UsesByReg[I].find_next(J)) + for (int J : UsesByReg[I].set_bits()) if (DA.doesADominateB(*First, J)) BBDominatedUses.set(J); LLVM_DEBUG(dbgs() << "\t\tBB " << BB.getName() << " dominates " @@ -817,8 +816,7 @@ void ShrinkWrapping::computeSaveLocations() { SavePos[I].insert(First); LLVM_DEBUG({ dbgs() << "Dominated uses are:\n"; - for (int J = UsesByReg[I].find_first(); J > 0; - J = UsesByReg[I].find_next(J)) { + for (int J : UsesByReg[I].set_bits()) { dbgs() << "Idx " << J << ": "; DA.Expressions[J]->dump(); } diff --git a/bolt/lib/Passes/StokeInfo.cpp b/bolt/lib/Passes/StokeInfo.cpp index efe9668827ff..df6d85aced4e 100644 --- a/bolt/lib/Passes/StokeInfo.cpp +++ b/bolt/lib/Passes/StokeInfo.cpp @@ -35,12 +35,10 @@ namespace bolt { void getRegNameFromBitVec(const BinaryContext &BC, const BitVector &RegV, std::set<std::string> *NameVec = nullptr) { - int RegIdx = RegV.find_first(); - while (RegIdx != -1) { + for (int RegIdx : RegV.set_bits()) { LLVM_DEBUG(dbgs() << BC.MRI->getName(RegIdx) << " "); if (NameVec) NameVec->insert(std::string(BC.MRI->getName(RegIdx))); - RegIdx = RegV.find_next(RegIdx); } LLVM_DEBUG(dbgs() << "\n"); } diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp index cc148e914ae6..5f0388a5da72 100644 --- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp +++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp @@ -655,12 +655,10 @@ public: getWrittenRegs(Instr, Regs); // Update register definitions after this point - int Idx = Regs.find_first(); - while (Idx != -1) { + for (int Idx : Regs.set_bits()) { RegAliasTable[Idx] = &Instr; LLVM_DEBUG(dbgs() << "Setting reg " << Idx << " def to current instr.\n"); - Idx = Regs.find_next(Idx); } TerminatorSeen = isTerminator(Instr); |