diff options
author | Amir Ayupov <aaupov@fb.com> | 2022-04-06 00:30:44 +0300 |
---|---|---|
committer | Amir Ayupov <aaupov@fb.com> | 2022-04-06 00:32:07 +0300 |
commit | f99398fe0ee943c3c0493da0d6488d45658f7327 (patch) | |
tree | d99e7c7ef7dd81d914b8f37a1369db04a8e5409d /bolt | |
parent | 6302a91468ebcaeac63951f9c89da9d89bc38ede (diff) |
[BOLT][NFC] Move isADD64rr and isADDri out of MCPlusBuilder class
Reviewed By: rafauler
Differential Revision: https://reviews.llvm.org/D123077
Diffstat (limited to 'bolt')
-rw-r--r-- | bolt/include/bolt/Core/MCPlusBuilder.h | 5 | ||||
-rw-r--r-- | bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp | 2 | ||||
-rw-r--r-- | bolt/lib/Target/X86/X86MCPlusBuilder.cpp | 16 |
3 files changed, 7 insertions, 16 deletions
diff --git a/bolt/include/bolt/Core/MCPlusBuilder.h b/bolt/include/bolt/Core/MCPlusBuilder.h index 02588c29462a..64e98e5f400e 100644 --- a/bolt/include/bolt/Core/MCPlusBuilder.h +++ b/bolt/include/bolt/Core/MCPlusBuilder.h @@ -511,11 +511,6 @@ public: return 0; } - virtual bool isADD64rr(const MCInst &Inst) const { - llvm_unreachable("not implemented"); - return false; - } - virtual bool isSUB(const MCInst &Inst) const { llvm_unreachable("not implemented"); return false; diff --git a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp index c4bceac5db3c..e83a09c8e524 100644 --- a/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp +++ b/bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp @@ -1103,8 +1103,6 @@ public: bool isMoveMem2Reg(const MCInst &Inst) const override { return false; } - bool isADD64rr(const MCInst &Inst) const override { return false; } - bool isLeave(const MCInst &Inst) const override { return false; } bool isPop(const MCInst &Inst) const override { return false; } diff --git a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp index b7678cbff06b..82681700e3a9 100644 --- a/bolt/lib/Target/X86/X86MCPlusBuilder.cpp +++ b/bolt/lib/Target/X86/X86MCPlusBuilder.cpp @@ -68,6 +68,13 @@ bool isMOVSX64rm32(const MCInst &Inst) { return Inst.getOpcode() == X86::MOVSX64rm32; } +bool isADD64rr(const MCInst &Inst) { return Inst.getOpcode() == X86::ADD64rr; } + +bool isADDri(const MCInst &Inst) { + return Inst.getOpcode() == X86::ADD64ri32 || + Inst.getOpcode() == X86::ADD64ri8; +} + class X86MCPlusBuilder : public MCPlusBuilder { public: X86MCPlusBuilder(const MCInstrAnalysis *Analysis, const MCInstrInfo *Info, @@ -292,19 +299,10 @@ public: return 0; } - bool isADD64rr(const MCInst &Inst) const override { - return Inst.getOpcode() == X86::ADD64rr; - } - bool isSUB(const MCInst &Inst) const override { return X86::isSUB(Inst.getOpcode()); } - bool isADDri(const MCInst &Inst) const { - return Inst.getOpcode() == X86::ADD64ri32 || - Inst.getOpcode() == X86::ADD64ri8; - } - bool isLEA64r(const MCInst &Inst) const override { return Inst.getOpcode() == X86::LEA64r; } |