diff options
author | Shraiysh Vaishay <Shraiysh.Vaishay@amd.com> | 2022-03-09 12:33:17 +0300 |
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committer | Shraiysh Vaishay <Shraiysh.Vaishay@amd.com> | 2022-03-09 17:40:45 +0300 |
commit | 7c385c4b2f653d6853fe4601f02bbc7fcd60cd91 (patch) | |
tree | afbc6be3feecff97e1982e30044cb5cd66041fb5 /mlir | |
parent | 36e4ad1ed0f0eb0116d8335a85e42672a29fd9aa (diff) |
[mlir][OpenMP] Generating enums in accordance with the guidelines
This patch changes the enums generated from `OMP.td` for MLIR according
to the enum naming guidelines in LLVM Coding Standards.
This also helps the issues we had with `static` being a C++ keyword and
also a value for the schedule clause.
Enumerator naming guidelines: https://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly
Reviewed By: kiranchandramohan
Differential Revision: https://reviews.llvm.org/D120825
Diffstat (limited to 'mlir')
-rw-r--r-- | mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 13 | ||||
-rw-r--r-- | mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp | 18 | ||||
-rw-r--r-- | mlir/test/Dialect/OpenMP/ops.mlir | 8 | ||||
-rw-r--r-- | mlir/test/mlir-tblgen/directive-common.td | 4 | ||||
-rw-r--r-- | mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp | 10 |
5 files changed, 28 insertions, 25 deletions
diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index b4e08ac7b9a1..87098b9f7421 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -674,7 +674,6 @@ static ParseResult parseClauses(OpAsmParser &parser, OperationState &result, // Add schedule parameters if (done[scheduleClause] && !schedule.empty()) { - schedule[0] = llvm::toUpper(schedule[0]); if (Optional<ClauseScheduleKind> sched = symbolizeClauseScheduleKind(schedule)) { auto attr = ClauseScheduleKindAttr::get(parser.getContext(), *sched); @@ -999,8 +998,8 @@ LogicalResult OrderedRegionOp::verify() { LogicalResult AtomicReadOp::verify() { if (auto mo = memory_order_val()) { - if (*mo == ClauseMemoryOrderKind::acq_rel || - *mo == ClauseMemoryOrderKind::release) { + if (*mo == ClauseMemoryOrderKind::Acq_rel || + *mo == ClauseMemoryOrderKind::Release) { return emitError( "memory-order must not be acq_rel or release for atomic reads"); } @@ -1017,8 +1016,8 @@ LogicalResult AtomicReadOp::verify() { LogicalResult AtomicWriteOp::verify() { if (auto mo = memory_order_val()) { - if (*mo == ClauseMemoryOrderKind::acq_rel || - *mo == ClauseMemoryOrderKind::acquire) { + if (*mo == ClauseMemoryOrderKind::Acq_rel || + *mo == ClauseMemoryOrderKind::Acquire) { return emitError( "memory-order must not be acq_rel or acquire for atomic writes"); } @@ -1032,8 +1031,8 @@ LogicalResult AtomicWriteOp::verify() { LogicalResult AtomicUpdateOp::verify() { if (auto mo = memory_order_val()) { - if (*mo == ClauseMemoryOrderKind::acq_rel || - *mo == ClauseMemoryOrderKind::acquire) { + if (*mo == ClauseMemoryOrderKind::Acq_rel || + *mo == ClauseMemoryOrderKind::Acquire) { return emitError( "memory-order must not be acq_rel or acquire for atomic updates"); } diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index 5c19b995b6b6..feaa75c0bc21 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -190,13 +190,13 @@ static void convertOmpOpRegions( /// Convert ProcBindKind from MLIR-generated enum to LLVM enum. static llvm::omp::ProcBindKind getProcBindKind(omp::ClauseProcBindKind kind) { switch (kind) { - case omp::ClauseProcBindKind::close: + case omp::ClauseProcBindKind::Close: return llvm::omp::ProcBindKind::OMP_PROC_BIND_close; - case omp::ClauseProcBindKind::master: + case omp::ClauseProcBindKind::Master: return llvm::omp::ProcBindKind::OMP_PROC_BIND_master; - case omp::ClauseProcBindKind::primary: + case omp::ClauseProcBindKind::Primary: return llvm::omp::ProcBindKind::OMP_PROC_BIND_primary; - case omp::ClauseProcBindKind::spread: + case omp::ClauseProcBindKind::Spread: return llvm::omp::ProcBindKind::OMP_PROC_BIND_spread; } llvm_unreachable("Unknown ClauseProcBindKind kind"); @@ -887,15 +887,15 @@ convertAtomicOrdering(Optional<omp::ClauseMemoryOrderKind> ao) { return llvm::AtomicOrdering::Monotonic; // Default Memory Ordering switch (*ao) { - case omp::ClauseMemoryOrderKind::seq_cst: + case omp::ClauseMemoryOrderKind::Seq_cst: return llvm::AtomicOrdering::SequentiallyConsistent; - case omp::ClauseMemoryOrderKind::acq_rel: + case omp::ClauseMemoryOrderKind::Acq_rel: return llvm::AtomicOrdering::AcquireRelease; - case omp::ClauseMemoryOrderKind::acquire: + case omp::ClauseMemoryOrderKind::Acquire: return llvm::AtomicOrdering::Acquire; - case omp::ClauseMemoryOrderKind::release: + case omp::ClauseMemoryOrderKind::Release: return llvm::AtomicOrdering::Release; - case omp::ClauseMemoryOrderKind::relaxed: + case omp::ClauseMemoryOrderKind::Relaxed: return llvm::AtomicOrdering::Monotonic; } llvm_unreachable("Unknown ClauseMemoryOrderKind kind"); diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index 3d6834f0d934..62776e2db9d9 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -135,28 +135,28 @@ func @omp_wsloop(%lb : index, %ub : index, %step : index, %data_var : memref<i32 "omp.wsloop" (%lb, %ub, %step, %data_var, %linear_var) ({ ^bb0(%iv: index): omp.yield - }) {operand_segment_sizes = dense<[1,1,1,1,1,0,0]> : vector<7xi32>, schedule_val = #omp<"schedulekind Static">} : + }) {operand_segment_sizes = dense<[1,1,1,1,1,0,0]> : vector<7xi32>, schedule_val = #omp<"schedulekind static">} : (index, index, index, memref<i32>, i32) -> () // CHECK: omp.wsloop (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) linear(%{{.*}} = %{{.*}} : memref<i32>, %{{.*}} = %{{.*}} : memref<i32>) schedule(static) "omp.wsloop" (%lb, %ub, %step, %data_var, %data_var, %linear_var, %linear_var) ({ ^bb0(%iv: index): omp.yield - }) {operand_segment_sizes = dense<[1,1,1,2,2,0,0]> : vector<7xi32>, schedule_val = #omp<"schedulekind Static">} : + }) {operand_segment_sizes = dense<[1,1,1,2,2,0,0]> : vector<7xi32>, schedule_val = #omp<"schedulekind static">} : (index, index, index, memref<i32>, memref<i32>, i32, i32) -> () // CHECK: omp.wsloop (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) linear(%{{.*}} = %{{.*}} : memref<i32>) schedule(dynamic = %{{.*}}) collapse(3) ordered(2) "omp.wsloop" (%lb, %ub, %step, %data_var, %linear_var, %chunk_var) ({ ^bb0(%iv: index): omp.yield - }) {operand_segment_sizes = dense<[1,1,1,1,1,0,1]> : vector<7xi32>, schedule_val = #omp<"schedulekind Dynamic">, collapse_val = 3, ordered_val = 2} : + }) {operand_segment_sizes = dense<[1,1,1,1,1,0,1]> : vector<7xi32>, schedule_val = #omp<"schedulekind dynamic">, collapse_val = 3, ordered_val = 2} : (index, index, index, memref<i32>, i32, i32) -> () // CHECK: omp.wsloop (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) schedule(auto) nowait "omp.wsloop" (%lb, %ub, %step) ({ ^bb0(%iv: index): omp.yield - }) {operand_segment_sizes = dense<[1,1,1,0,0,0,0]> : vector<7xi32>, nowait, schedule_val = #omp<"schedulekind Auto">} : + }) {operand_segment_sizes = dense<[1,1,1,0,0,0,0]> : vector<7xi32>, nowait, schedule_val = #omp<"schedulekind auto">} : (index, index, index) -> () return diff --git a/mlir/test/mlir-tblgen/directive-common.td b/mlir/test/mlir-tblgen/directive-common.td index b1d554c4c703..dd86dea36417 100644 --- a/mlir/test/mlir-tblgen/directive-common.td +++ b/mlir/test/mlir-tblgen/directive-common.td @@ -21,8 +21,8 @@ def TDLC_ClauseA : Clause<"clausea"> { ]; } -// CHECK: def AKindvala : I32EnumAttrCase<"vala", 0>; -// CHECK: def AKindvalb : I32EnumAttrCase<"valb", 1>; +// CHECK: def AKindvala : I32EnumAttrCase<"Vala", 0, "vala">; +// CHECK: def AKindvalb : I32EnumAttrCase<"Valb", 1, "valb">; // CHECK: def AKind: I32EnumAttr< // CHECK: "ClauseAKind", // CHECK: "AKind Clause", diff --git a/mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp b/mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp index 4873f914afe4..a5c89344b2d6 100644 --- a/mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp +++ b/mlir/tools/mlir-tblgen/DirectiveCommonGen.cpp @@ -70,10 +70,14 @@ static bool emitDecls(const RecordKeeper &recordKeeper, llvm::StringRef dialect, if (!cval.isUserVisible()) continue; - const auto name = cval.getFormattedName(); + std::string name = cval.getFormattedName(); + std::string enumValName(name.length(), ' '); + std::transform(name.begin(), name.end(), enumValName.begin(), + llvm::toLower); + enumValName[0] = llvm::toUpper(enumValName[0]); std::string cvDef{(enumName + llvm::Twine(name)).str()}; - os << "def " << cvDef << " : I32EnumAttrCase<\"" << name << "\", " - << it.index() << ">;\n"; + os << "def " << cvDef << " : I32EnumAttrCase<\"" << enumValName << "\", " + << it.index() << ", \"" << name << "\">;\n"; cvDefs.push_back(cvDef); } |