diff options
author | Guillaume Revaillot <revaillot@archos.com> | 2019-06-18 14:33:11 +0300 |
---|---|---|
committer | Guillaume Revaillot <revaillot@archos.com> | 2019-07-05 12:43:11 +0300 |
commit | 2035d84e550f64b9423b37bdef578be2708530c9 (patch) | |
tree | 015ba7100cdb0db8c46a76c6f44e08b046de84f3 | |
parent | f99e7118732f5749f9de2c56fccb0c5ac05fdf00 (diff) |
stm32: lptim: add base support
Add basically what's needed to have some minimal but usefull subset of
function for a timer: irqs, compare, period, out polarity, enable/disable
and start.
-rw-r--r-- | include/libopencm3/stm32/common/lptimer_common_all.h | 35 | ||||
-rw-r--r-- | lib/stm32/common/lptimer_common_all.c | 294 | ||||
-rw-r--r-- | lib/stm32/f4/Makefile | 1 | ||||
-rw-r--r-- | lib/stm32/f7/Makefile | 1 | ||||
-rw-r--r-- | lib/stm32/g0/Makefile | 1 | ||||
-rw-r--r-- | lib/stm32/l0/Makefile | 1 | ||||
-rw-r--r-- | lib/stm32/l4/Makefile | 1 |
7 files changed, 334 insertions, 0 deletions
diff --git a/include/libopencm3/stm32/common/lptimer_common_all.h b/include/libopencm3/stm32/common/lptimer_common_all.h index d1f6187f..37ea10f1 100644 --- a/include/libopencm3/stm32/common/lptimer_common_all.h +++ b/include/libopencm3/stm32/common/lptimer_common_all.h @@ -1,12 +1,14 @@ /** @addtogroup lptimer_defines * * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net> + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> * */ /* * This file is part of the libopencm3 project. * * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net> + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -252,10 +254,43 @@ #define LPTIM_CR_CNTSTRT (1 << 2) /**@}*/ + +/* --- LPTIM function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void lptimer_enable(uint32_t timer_peripheral); +void lptimer_disable(uint32_t timer_peripheral); + +void lptimer_start_counter(uint32_t timer_peripheral, uint32_t mode); +void lptimer_set_counter(uint32_t timer_peripheral, uint16_t count); +uint16_t lptimer_get_counter(uint32_t timer_peripheral); +void lptimer_set_compare(uint32_t timer_peripheral, uint16_t compare_value); +void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value); +void lptimer_enable_preload(uint32_t lptimer_peripheral); +void lptimer_disable_preload(uint32_t lptimer_peripheral); +void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral); +void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral); + +void lptimer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); +void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen); +void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source); +void lptimer_set_internal_clock_source(uint32_t timer_peripheral); +void lptimer_set_external_clock_source(uint32_t timer_peripheral); + +void lptimer_clear_flag(uint32_t timer_peripheral, uint32_t flag); +bool lptimer_get_flag(uint32_t timer_peripheral, uint32_t flag); +void lptimer_enable_irq(uint32_t timer_peripheral, uint32_t irq); +void lptimer_disable_irq(uint32_t timer_peripheral, uint32_t irq); + + +END_DECLS + #endif /** @cond */ #else #warning "lptimer_common_all.h should not be included directly, only via lptimer.h" #endif /** @endcond */ + /**@}*/ diff --git a/lib/stm32/common/lptimer_common_all.c b/lib/stm32/common/lptimer_common_all.c new file mode 100644 index 00000000..1dc4e0ab --- /dev/null +++ b/lib/stm32/common/lptimer_common_all.c @@ -0,0 +1,294 @@ +/** @addtogroup lptimer_file LPTIM peripheral API + * @ingroup peripheral_apis + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * @date 2 July 2019 + * + * LGPL License Terms @ref lgpl_license + * + * @section lptim_api_ex Basic LPTIMER handling API. + * + * Example: LPTIM1 with 2x clock prescaler, from internal clock (LSE), irq on match and reload. + * + * @code + * + * rcc_set_peripheral_clk_sel(LPTIM1, RCC_CCIPR_LPTIM1SEL_LSE); + * + * rcc_periph_clock_enable(RCC_LPTIM1); + * + * lptimer_set_internal_clock_source(LPTIM1); + * lptimer_enable_trigger(LPTIM1, LPTIM_CFGR_TRIGEN_SW); + * lptimer_set_prescaler(LPTIM1, LPTIM_CFGR_PRESC_2); + * + * lptimer_enable(LPTIM1); + * + * lptimer_set_period(LPTIM1, 0xffff); + * lptimer_set_compare(LPTIM1, 1234); + * + * lptimer_enable_irq(LPTIM1, LPTIM_IER_ARRMIE | LPTIM_IER_CMPMIE); + * nvic_enable_irq(NVIC_LPTIM1_IRQ); + * + * lptimer_start_counter(LPTIM1, LPTIM_CR_CNTSTRT); + * + * @endcode + * + * Note: LPTIM internal clock source selection is device specific, see clock tree + * and rcc section of reference manual. + * + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/stm32/lptimer.h> + +/** @brief Set lptimer Counter + * + * Set the value of a lptimer counter. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] count Counter value. +*/ +void lptimer_set_counter(uint32_t lptimer_peripheral, uint16_t count) +{ + LPTIM_CNT(lptimer_peripheral) = count; +} + +/** @brief Read lptimer Counter + * + * Read back the value of lptimer counter. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @returns Counter value. + */ +uint16_t lptimer_get_counter(uint32_t lptimer_peripheral) +{ + return LPTIM_CNT(lptimer_peripheral); +} + +/** @brief Clear lptimer Status Flag. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] flag Status Register clear flag (@ref lptim_icr) + */ +void lptimer_clear_flag(uint32_t lptimer_peripheral, uint32_t flag) +{ + LPTIM_ICR(lptimer_peripheral) = flag; +} + +/** @brief Read lptimer Status Flag. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] flag Status Register flag (@ref lptim_isr) + * @returns flag set. + */ +bool lptimer_get_flag(uint32_t lptimer_peripheral, uint32_t flag) +{ + return (LPTIM_ISR(lptimer_peripheral) & flag); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable lptimer interrupts. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] irq Logical or of all interrupt enable bits to be set (@ref lptim_ier) + */ +void lptimer_enable_irq(uint32_t lptimer_peripheral, uint32_t irq) +{ + LPTIM_IER(lptimer_peripheral) |= irq; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable lptimer Interrupts. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] irq Logical or of all interrupt enable bits to be cleared (@ref lptim_ier) + */ +void lptimer_disable_irq(uint32_t lptimer_peripheral, uint32_t irq) +{ + LPTIM_IER(lptimer_peripheral) &= ~irq; +} + +/** @brief Enable lptimer. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_enable(uint32_t lptimer_peripheral) +{ + LPTIM_CR(lptimer_peripheral) |= LPTIM_CR_ENABLE; +} + +/** @brief Disable lptimer. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_disable(uint32_t lptimer_peripheral) +{ + LPTIM_CR(lptimer_peripheral) &= ~LPTIM_CR_ENABLE; +} + +/** @brief Start lptimer in a given mode. + * + * Starts the timer in specified mode - Either Single (@ref LPTIM_CR_SNGSTRT) or + * Continuous mode (@ref LPTIM_CR_CNTSTRT). In Single mode, the timer will stop at + * next match on compare or period value. + * If LPTIM_CR_SNGSTRT is set while timer is started in countious mode, it + * will stop at next match on compare or period value. + * If Software trigger is disabled, start will be delayed until programmed + * triggers is detected. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] mode lptimer start mode (@ref LPTIM_CR_SNGSTRT or @ref LPTIM_CR_CNTSTRT) + */ +void lptimer_start_counter(uint32_t lptimer_peripheral, uint32_t mode) +{ + LPTIM_CR(lptimer_peripheral) |= mode; +} + +/** @brief Set lptimer clock prescaler. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] prescaler Clock prescaler (@ref lptim_cfgr_presc) + */ +void lptimer_set_prescaler(uint32_t lptimer_peripheral, uint32_t prescaler) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_PRESC_MASK << LPTIM_CFGR_PRESC_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | prescaler; +} + +/** @brief Enable lptimer External Trigger + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel) + */ +void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_TRIGEN_MASK << LPTIM_CFGR_TRIGEN_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | trigen; +} + +/** @brief Select lptimer Trigger Source + * + * Select timer external trigger source. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel) + */ +void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_TRIGSEL_MASK << LPTIM_CFGR_TRIGSEL_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | trigger_source; +} + +/** @brief Set lptimer counter Compare Value + * + * Set the timer compare value. Must only be set with timer enabled. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] compare_value Compare value. + */ +void lptimer_set_compare(uint32_t lptimer_peripheral, uint16_t compare_value) +{ + LPTIM_CMP(lptimer_peripheral) = compare_value; +} + +/** @brief Set lptimer period + * + * Set the timer period in the auto-reload register. Must only be set with timer + * enabled. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] period_value Autoreload value. Must be greater that CMP value. + */ +void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value) +{ + LPTIM_ARR(lptimer_peripheral) = period_value; +} + +/** @brief Enable lptimer Preload mode. + * + * Enable lptimer preload mode, delaying update of period and compare registers + * to the end of current period. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_enable_preload(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_PRELOAD; +} + +/** @brief Disable lptimer Preload mode. + * + * Disable lptimer preload mode, ensureing updated period and compare registers + * values are taken in account immediatly. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_disable_preload(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_PRELOAD; +} + + +/** @brief Set lptimer Internal Clock source + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_internal_clock_source(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_CKSEL; +} + +/** @brief Set lptimer External Clock source + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_external_clock_source(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_CKSEL; +} + +/** @brief Set lptimer Waveform Output Polarity High + * + * Set lptimer waveform output to reflect compare result between LPTIN_CNT + * and LPTIM_CMP. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_WAVPOL; +} + +/** @brief Set lptimer Waveform Output Polarity Low + * + * Set lptimer waveform output to reflect the inverse of the compare result + * between LPTIN_CNT and LPTIM_CMP. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_WAVPOL; +} + +/**@}*/ diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 747ee549..ebcf5f78 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -54,6 +54,7 @@ OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += hash_common_f24.o OBJS += i2c_common_v1.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += ltdc_common_f47.o OBJS += pwr_common_v1.o pwr.o OBJS += rcc_common_all.o rcc.o diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 693bb58d..ff078655 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -54,6 +54,7 @@ OBJS += fmc_common_f47.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += ltdc_common_f47.o OBJS += pwr.o rcc.o OBJS += rcc_common_all.o diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile index 376ee203..cb75e4fe 100644 --- a/lib/stm32/g0/Makefile +++ b/lib/stm32/g0/Makefile @@ -40,6 +40,7 @@ OBJS += flash.o flash_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index a9743caf..857d3d5c 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -43,6 +43,7 @@ OBJS += flash_common_all.o flash_common_l01.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += pwr_common_v1.o pwr_common_v2.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index 514128f6..6a1594ff 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -46,6 +46,7 @@ OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o OBJS += gpio_common_all.o gpio_common_f0234.o OBJS += i2c_common_v2.o OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o OBJS += pwr.o OBJS += rcc.o rcc_common_all.o OBJS += rng_common_v1.o |