diff options
| author | D. Lisin <mrlisdim@gmail.com> | 2019-09-21 21:12:07 +0300 |
|---|---|---|
| committer | D. Lisin <mrlisdim@gmail.com> | 2019-09-21 21:12:21 +0300 |
| commit | decb98c6d434260a38f3f671554cd7234fc08849 (patch) | |
| tree | 59c69ef4718c65866349d38f5c5fdc31f88eb5f5 /include/libopencm3/stm32/common | |
| parent | 293cfebe971eaaee54d38b7e42def1194103d130 (diff) | |
| parent | b0c3de8d8516557f1f4ac85c5deb4fb45fb8a10b (diff) | |
Merge remote-tracking branch 'upstream/master'
# Conflicts:
# lib/stm32/f2/Makefile
# lib/stm32/f4/Makefile
Diffstat (limited to 'include/libopencm3/stm32/common')
22 files changed, 2763 insertions, 108 deletions
diff --git a/include/libopencm3/stm32/common/adc_common_v1_multi.h b/include/libopencm3/stm32/common/adc_common_v1_multi.h new file mode 100644 index 00000000..05a2ac6c --- /dev/null +++ b/include/libopencm3/stm32/common/adc_common_v1_multi.h @@ -0,0 +1,379 @@ +/** @addtogroup adc_defines + +@author @htmlonly © @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au> + + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Matthew Lai <m@matthewlai.ca> + * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H +The order of header inclusion is important. adc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_ADC_H +/** @endcond */ +#ifndef LIBOPENCM3_ADC_COMMON_V1_MULTI_H +#define LIBOPENCM3_ADC_COMMON_V1_MULTI_H + +#include <libopencm3/stm32/common/adc_common_v1.h> + +/* --- Convenience macros -------------------------------------------------- */ + + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) + +/* --- ADC Channels ------------------------------------------------------- */ + + +/* --- ADC_SR values ------------------------------------------------------- */ + +/** @defgroup adc_sr_values ADC Status Register Flags + * @ingroup adc_defines + *@{*/ + +/* OVR:*//** Overrun */ +#define ADC_SR_OVR (1 << 5) +/**@}*/ + +/* OVRIE: Overrun interrupt enable */ +#define ADC_CR1_OVRIE (1 << 26) + +/* RES[1:0]: Resolution */ +/****************************************************************************/ +/** @defgroup adc_cr1_res ADC Resolution. +@ingroup adc_defines + +@{*/ +#define ADC_CR1_RES_12BIT (0x0 << 24) +#define ADC_CR1_RES_10BIT (0x1 << 24) +#define ADC_CR1_RES_8BIT (0x2 << 24) +#define ADC_CR1_RES_6BIT (0x3 << 24) +/**@}*/ +#define ADC_CR1_RES_MASK (0x3 << 24) +#define ADC_CR1_RES_SHIFT 24 + +/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ + + + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* SWSTART: Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 30) + +/* EXTEN[1:0]: External trigger enable for regular channels. */ +/****************************************************************************/ +#define ADC_CR2_EXTEN_SHIFT 28 +#define ADC_CR2_EXTEN_MASK (0x3 << ADC_CR2_EXTEN_SHIFT) +/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity +@ingroup adc_defines +@{*/ +#define ADC_CR2_EXTEN_DISABLED (0x0 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << ADC_CR2_EXTEN_SHIFT) +/**@}*/ + +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +/* Note: Selection values are family-dependent. */ +#define ADC_CR2_EXTSEL_MASK (0xF << 24) +#define ADC_CR2_EXTSEL_SHIFT 24 + +/* Bit 23 is reserved */ + +/* JSWSTART: Start conversion of injected channels. */ +#define ADC_CR2_JSWSTART (1 << 22) + +/* JEXTEN[1:0]: External trigger enable for injected channels. */ +/****************************************************************************/ +#define ADC_CR2_JEXTEN_SHIFT 20 +#define ADC_CR2_JEXTEN_MASK (0x3 << ADC_CR2_JEXTEN_SHIFT) +/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity +@ingroup adc_defines +@{*/ +#define ADC_CR2_JEXTEN_DISABLED (0x0 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << ADC_CR2_JEXTEN_SHIFT) +/**@}*/ + +/* JEXTSEL[3:0]: External event selection for injected group. */ +/****************************************************************************/ +/* Note: Selection values are family-dependent. */ +#define ADC_CR2_JEXTSEL_SHIFT 16 +#define ADC_CR2_JEXTSEL_MASK (0xF << ADC_CR2_JEXTSEL_SHIFT) + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* EOCS: End of conversion selection. */ +#define ADC_CR2_EOCS (1 << 10) + +/* DDS: DMA disable selection */ +#define ADC_CR2_DDS (1 << 9) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* Note: Bits [7:2] are reserved and must be kept at reset value. */ + +/* CONT: Continuous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + + +/* --- ADC_SMPRx values --------------------------------------------------- */ +/****************************************************************************/ + +#define ADC_SQRx_MASK 0x1f + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) + +/* --- Common Registers ---------------------------------------------------- */ + +/* --- ADC_CSR values (read only images) ------------------------------------ */ + +/* OVR3: Overrun ADC3. */ +#define ADC_CSR_OVR3 (1 << 21) + +/* STRT3: Regular channel start ADC3. */ +#define ADC_CSR_STRT3 (1 << 20) + +/* JSTRT3: Injected channel start ADC3. */ +#define ADC_CSR_JSTRT3 (1 << 19) + +/* JEOC3: Injected channel end of conversion ADC3. */ +#define ADC_CSR_JEOC3 (1 << 18) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_EOC3 (1 << 17) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_AWD3 (1 << 16) + +/* Bits 15:14 Reserved, must be kept at reset value */ + +/* OVR2: Overrun ADC2. */ +#define ADC_CSR_OVR2 (1 << 13) + +/* STRT2: Regular channel start ADC2. */ +#define ADC_CSR_STRT2 (1 << 12) + +/* JSTRT2: Injected channel start ADC2. */ +#define ADC_CSR_JSTRT2 (1 << 11) + +/* JEOC2: Injected channel end of conversion ADC2. */ +#define ADC_CSR_JEOC2 (1 << 10) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_EOC2 (1 << 9) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_AWD2 (1 << 8) + +/* Bits 7:6 Reserved, must be kept at reset value */ + +/* OVR1: Overrun ADC1. */ +#define ADC_CSR_OVR1 (1 << 5) + +/* STRT1: Regular channel start ADC1. */ +#define ADC_CSR_STRT1 (1 << 4) + +/* JSTRT1: Injected channel start ADC1. */ +#define ADC_CSR_JSTRT1 (1 << 3) + +/* JEOC1: Injected channel end of conversion ADC1. */ +#define ADC_CSR_JEOC1 (1 << 2) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_EOC1 (1 << 1) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_AWD1 (1 << 0) + +/* --- ADC_CCR values ------------------------------------------------------ */ + +/* TSVREFE: Temperature sensor and Vrefint enable. */ +#define ADC_CCR_TSVREFE (1 << 23) + +/* VBATE: VBat enable. */ +#define ADC_CCR_VBATE (1 << 22) + +/* Bit 18:21 reserved, must be kept at reset value. */ + +/* DMA: Direct memory access mode for multi ADC mode. */ +/****************************************************************************/ +/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DMA_DISABLE (0x0 << 14) +#define ADC_CCR_DMA_MODE_1 (0x1 << 14) +#define ADC_CCR_DMA_MODE_2 (0x2 << 14) +#define ADC_CCR_DMA_MODE_3 (0x3 << 14) +/**@}*/ +#define ADC_CCR_DMA_MASK (0x3 << 14) +#define ADC_CCR_DMA_SHIFT 14 + +/* DDS: DMA disable selection (for multi-ADC mode). */ +#define ADC_CCR_DDS (1 << 13) + +/* Bit 12 reserved, must be kept at reset value */ + +/* DELAY: Delay between 2 sampling phases. */ +/****************************************************************************/ +/** @defgroup adc_delay ADC Delay between 2 sampling phases +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) +#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) +#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) +#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) +#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) +#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) +#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) +#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) +#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) +#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) +#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) +#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) +#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) +#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) +#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) +#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) +/**@}*/ +#define ADC_CCR_DELAY_MASK (0xf << 8) +#define ADC_CCR_DELAY_SHIFT 8 + +/* Bit 7:5 reserved, must be kept at reset value */ + +/* MULTI: Multi ADC mode selection. */ +/****************************************************************************/ +/** @defgroup adc_multi_mode ADC Multi mode selection +@ingroup adc_defines + +@{*/ + +/** All ADCs independent */ +#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) + +/* Dual modes (ADC1 + ADC2) */ +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) +/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) +/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) +/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ +#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) +/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) + +/* Triple modes (ADC1 + ADC2 + ADC3) */ +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) +/**@}*/ + +#define ADC_CCR_MULTI_MASK (0x1f << 0) +#define ADC_CCR_MULTI_SHIFT 0 + +/* --- ADC_CDR values ------------------------------------------------------ */ + +#define ADC_CDR_DATA2_MASK (0xffff << 16) +#define ADC_CDR_DATA2_SHIFT 16 + +#define ADC_CDR_DATA1_MASK (0xffff << 0) +#define ADC_CDR_DATA1_SHIFT 0 + +BEGIN_DECLS + +void adc_set_clk_prescale(uint32_t prescaler); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_set_resolution(uint32_t adc, uint32_t resolution); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +bool adc_awd(uint32_t adc); +void adc_eoc_after_each(uint32_t adc); +void adc_eoc_after_group(uint32_t adc); +void adc_set_dma_continue(uint32_t adc); +void adc_set_dma_terminate(uint32_t adc); +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + +#endif +/** @cond */ +#endif +/** @endcond */ +/**@}*/ diff --git a/include/libopencm3/stm32/common/adc_common_v2.h b/include/libopencm3/stm32/common/adc_common_v2.h index afe23c39..d46bd496 100644 --- a/include/libopencm3/stm32/common/adc_common_v2.h +++ b/include/libopencm3/stm32/common/adc_common_v2.h @@ -36,138 +36,181 @@ specific memorymap.h header before including this header file.*/ #define LIBOPENCM3_ADC_COMMON_V2_H /* ----- ADC registers -----------------------------------------------------*/ -/* ADC interrupt and status register */ +/** ADC interrupt and status register */ #define ADC_ISR(adc) MMIO32((adc) + 0x00) -/* Interrupt Enable Register */ +/** Interrupt Enable Register */ #define ADC_IER(adc) MMIO32((adc) + 0x04) -/* Control Register */ +/** Control Register */ #define ADC_CR(adc) MMIO32((adc) + 0x08) -/* Configuration Register 1 */ +/** Configuration Register 1 */ #define ADC_CFGR1(adc) MMIO32((adc) + 0x0C) -/* Configuration Register 2 */ +/** Configuration Register 2 */ #define ADC_CFGR2(adc) MMIO32((adc) + 0x10) -/* Sample Time Register 1 */ +/** Sample Time Register 1 */ #define ADC_SMPR1(adc) MMIO32((adc) + 0x14) -/* Watchdog Threshold Register 1*/ +/** Watchdog Threshold Register 1*/ #define ADC_TR1(adc) MMIO32((adc) + 0x20) -/* Regular Data Register */ +/** Regular Data Register */ #define ADC_DR(adc) MMIO32((adc) + 0x40) /* CALFACT for all but f0 :(*/ -/* ADC common (shared) registers */ +/** Common Configuration register */ #define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8) /* --- Register values -------------------------------------------------------*/ /* ADC_ISR Values -----------------------------------------------------------*/ +/** @defgroup adc_isr ISR ADC interrupt status register +@{*/ -/* AWD1: Analog watchdog 1 flag */ +/** AWD1: Analog watchdog 1 flag */ #define ADC_ISR_AWD1 (1 << 7) +/** OVR: Overrun flag */ #define ADC_ISR_OVR (1 << 4) +/** EOS: End of sequence conversions flag */ #define ADC_ISR_EOS (1 << 3) // FIXME - move to single/multi here. #define ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */ +/** EOS: End of regular conversion flag */ #define ADC_ISR_EOC (1 << 2) +/** EOSMP: End of sampling flag */ #define ADC_ISR_EOSMP (1 << 1) +/** ADRDY: Ready flag */ #define ADC_ISR_ADRDY (1 << 0) +/**@}*/ + /* ADC_IER Values -----------------------------------------------------------*/ +/** @defgroup adc_ier IER ADC interrupt enable register +@{*/ -/* AWD1IE: Analog watchdog 1 interrupt enable */ +/** AWD1IE: Analog watchdog 1 interrupt enable */ #define ADC_IER_AWD1IE (1 << 7) -/* OVRIE: Overrun interrupt enable */ +/** OVRIE: Overrun interrupt enable */ #define ADC_IER_OVRIE (1 << 4) -/* EOSIE: End of regular sequence of conversions interrupt enable */ +/** EOSIE: End of regular sequence of conversions interrupt enable */ #define ADC_IER_EOSIE (1 << 3) #define ADC_IER_EOSEQIE ADC_IER_EOSIE /* TODO - keep only one? */ -/* EOCIE: End of regular conversion interrupt enable */ +/** EOCIE: End of regular conversion interrupt enable */ #define ADC_IER_EOCIE (1 << 2) -/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ +/** EOSMPIE: End of sampling flag interrupt enable for regular conversions */ #define ADC_IER_EOSMPIE (1 << 1) -/* ADRDYIE : ADC ready interrupt enable */ +/** ADRDYIE: ADC ready interrupt enable */ #define ADC_IER_ADRDYIE (1 << 0) +/**@}*/ + /* ADC_CR Values -----------------------------------------------------------*/ +/** @defgroup adc_cr CR ADC control register +@{*/ -/* ADCAL: ADC calibration */ +/** ADCAL: ADC calibration */ #define ADC_CR_ADCAL (1 << 31) -/* ADSTP: ADC stop of regular conversion command */ +/** ADSTP: ADC stop of regular conversion command */ #define ADC_CR_ADSTP (1 << 4) -/* ADSTART: ADC start of regular conversion */ +/** ADSTART: ADC start of regular conversion */ #define ADC_CR_ADSTART (1 << 2) -/* ADDIS: ADC disable command */ +/** ADDIS: ADC disable command */ #define ADC_CR_ADDIS (1 << 1) -/* ADEN: ADC enable control */ +/** ADEN: ADC enable control */ #define ADC_CR_ADEN (1 << 0) +/**@}*/ + /* ADC_CFGR1 Values -----------------------------------------------------------*/ +/** @defgroup adc_cfgr1 CFGR1 ADC configuration register 1 +@{*/ -/* AWD1CH[4:0]: Analog watchdog 1 channel selection */ #define ADC_CFGR1_AWD1CH_SHIFT 26 #define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT) +/** AWD1CH: Analog watchdog 1 channel selection */ #define ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT) -/* AWD1EN: Analog watchdog 1 enable on regular channels */ +/** AWD1EN: Analog watchdog 1 enable on regular channels */ #define ADC_CFGR1_AWD1EN (1 << 23) - -/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ +/** AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ #define ADC_CFGR1_AWD1SGL (1 << 22) - -/* DISCEN: Discontinuous mode for regular channels */ +/** DISCEN: Discontinuous mode for regular channels */ #define ADC_CFGR1_DISCEN (1 << 16) - -/* AUTDLY: Delayed conversion mode */ +/** AUTDLY: Delayed conversion mode */ #define ADC_CFGR1_AUTDLY (1 << 14) - -/* CONT: Single / continuous conversion mode for regular conversions */ +/** CONT: Single / continuous conversion mode for regular conversions */ #define ADC_CFGR1_CONT (1 << 13) - -/* OVRMOD: Overrun Mode */ +/** OVRMOD: Overrun Mode */ #define ADC_CFGR1_OVRMOD (1 << 12) -/* - * EXTEN[1:0]: External trigger enable and polarity selection for regular - * channels - */ +#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) +/** @defgroup adc_cfgr1_exten EXTEN: External trigger enable and polarity selection for regular channels +@{*/ #define ADC_CFGR1_EXTEN_DISABLED (0x0 << 10) #define ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10) #define ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10) #define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10) +/**@}*/ -#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) - -/* ALIGN: Data alignment */ +/** ALIGN: Data alignment */ #define ADC_CFGR1_ALIGN (1 << 5) -/* RES[1:0]: Data resolution */ +#define ADC_CFGR1_RES_MASK (0x3 << 3) +/** @defgroup adc_cfgr1_res RES: Data resolution +@{*/ #define ADC_CFGR1_RES_12_BIT (0x0 << 3) #define ADC_CFGR1_RES_10_BIT (0x1 << 3) #define ADC_CFGR1_RES_8_BIT (0x2 << 3) #define ADC_CFGR1_RES_6_BIT (0x3 << 3) -#define ADC_CFGR1_RES_MASK (0x3 << 3) +/**@}*/ -/* DMACFG: Direct memory access configuration */ +/** DMACFG: Direct memory access configuration */ #define ADC_CFGR1_DMACFG (1 << 1) -/* DMAEN: Direct memory access enable */ +/** DMAEN: Direct memory access enable */ #define ADC_CFGR1_DMAEN (1 << 0) +/**@}*/ + +/* ADC_SMPR Values -----------------------------------------------------------*/ +/** @defgroup adc_smpr SMPR ADC sample time register +@{*/ + +/**@}*/ + +/* ADC_CFGR2 Values -----------------------------------------------------------*/ +/** @defgroup adc_cfgr2 CFGR2 ADC configuration register 2 +@{*/ + +/**@}*/ + /* ADC_TR1 Values ------------------------------------------------------------*/ +/** @defgroup adc_tr1 TR1 ADC watchdog threshold register 1 +@{*/ #define ADC_TR1_LT_SHIFT 0 +#define ADC_TR1_LT_MASK 0xFFF #define ADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT) +/** TR1_LT: analog watchdog 1 threshold low */ #define ADC_TR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT) #define ADC_TR1_HT_SHIFT 16 +#define ADC_TR1_HT_MASK 0xFFF #define ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT) +/** TR1_HT: analog watchdog 1 threshold high */ #define ADC_TR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT) - +/**@}*/ /* ADC_CCR Values -----------------------------------------------------------*/ +/** @defgroup adc_ccr CCR ADC common configuration register +@{*/ + +/** VBATEN: Enable VBAT Channel */ #define ADC_CCR_VBATEN (1 << 24) + +/** TSEN: Enable Temperature Sensor */ #define ADC_CCR_TSEN (1 << 23) + +/** VREFEN: Enable internal Voltage Reference */ #define ADC_CCR_VREFEN (1 << 22) +/**@}*/ /* --- Function prototypes ------------------------------------------------- */ @@ -205,7 +248,8 @@ bool adc_get_overrun_flag(uint32_t adc); void adc_clear_overrun_flag(uint32_t adc); uint32_t adc_read_regular(uint32_t adc); void adc_start_conversion_regular(uint32_t adc); - +void adc_enable_dma_circular_mode(uint32_t adc); +void adc_disable_dma_circular_mode(uint32_t adc); END_DECLS #endif diff --git a/include/libopencm3/stm32/common/adc_common_v2_single.h b/include/libopencm3/stm32/common/adc_common_v2_single.h index 1d6729d1..d2db6dce 100644 --- a/include/libopencm3/stm32/common/adc_common_v2_single.h +++ b/include/libopencm3/stm32/common/adc_common_v2_single.h @@ -48,22 +48,27 @@ specific memorymap.h header before including this header file.*/ /* ----- ADC registers values -----------------------------------------------*/ /* ADC_CFGR1 values */ +/** @addtogroup adc_cfgr1 +@{*/ /** Wait conversion mode */ #define ADC_CFGR1_WAIT (1<<14) /** Auto off mode */ #define ADC_CFGR1_AUTOFF (1 << 15) -/* EXTSEL[2:0]: External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_SHIFT 6 #define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT) +/** EXTSEL[2:0]: External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) +/** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */ #define ADC_CFGR1_SCANDIR (1 << 2) +/**@}*/ /* ADC_CHSELR Values --------------------------------------------------------*/ - +/** @addtogroup adc_chselr +@{*/ #define ADC_CHSELR_CHSEL(x) (1 << (x)) - +/**@}*/ /* --- Function prototypes ------------------------------------------------- */ diff --git a/include/libopencm3/stm32/common/crc_common_all.h b/include/libopencm3/stm32/common/crc_common_all.h index f883590c..f0cd13d6 100644 --- a/include/libopencm3/stm32/common/crc_common_all.h +++ b/include/libopencm3/stm32/common/crc_common_all.h @@ -43,6 +43,8 @@ specific memorymap.h header before including this header file.*/ /* Register definitions */ /*****************************************************************************/ +/**@defgroup crc_registers CRC Registers + @{*/ /** CRC_DR Data register */ #define CRC_DR MMIO32(CRC_BASE + 0x00) @@ -51,6 +53,7 @@ specific memorymap.h header before including this header file.*/ /** CRC_CR Control register */ #define CRC_CR MMIO32(CRC_BASE + 0x08) +/*@}*/ /*****************************************************************************/ /* Register values */ diff --git a/include/libopencm3/stm32/common/crc_v2.h b/include/libopencm3/stm32/common/crc_v2.h index 850dc252..515f7570 100644 --- a/include/libopencm3/stm32/common/crc_v2.h +++ b/include/libopencm3/stm32/common/crc_v2.h @@ -27,11 +27,7 @@ The order of header inclusion is important. crc.h includes the device specific memorymap.h header before including this header file.*/ -/** @cond */ -#ifdef LIBOPENCM3_CRC_H -/** @endcond */ -#ifndef LIBOPENCM3_CRC_V2_H -#define LIBOPENCM3_CRC_V2_H +#pragma once /**@{*/ @@ -45,6 +41,8 @@ /* Register definitions */ /*****************************************************************************/ +/** @addtogroup crc_registers CRC Registers +@{*/ /** CRC_DR Data register 8bit wide access */ #define CRC_DR8 MMIO8(CRC_BASE + 0x00) /** CRC_DR Data register 16bit wide access */ @@ -55,6 +53,7 @@ /** CRC_POL CRC Polynomial */ #define CRC_POL MMIO32(CRC_BASE + 0x14) +/**@}*/ /*****************************************************************************/ /* Register values */ @@ -65,29 +64,31 @@ #define CRC_CR_REV_IN_SHIFT 5 #define CRC_CR_REV_IN (3 << CRC_CR_REV_IN_SHIFT) +/** @defgroup crc_rev_in CRC Reverse input options + @{*/ #define CRC_CR_REV_IN_NONE (0 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_BYTE (1 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_HALF (2 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_WORD (3 << CRC_CR_REV_IN_SHIFT) +/**@}*/ #define CRC_CR_POLYSIZE_SHIFT 3 -#define CRC_CR_POLYSIZE (3 << CRC_CR_POLYSIZE_SHIFT) +#define CRC_CR_POLYSIZE (3 << CRC_CR_POLYSIZE_SHIFT) +/** + * @defgroup crc_polysize CRC Polynomial size + * @{ + */ #define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) #define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) #define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) #define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) +/**@}*/ -/* Default polynomial */ -#define CRC_POL_DEFAULT 0x04C11DB7 /**@}*/ -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ +/** Default polynomial */ +#define CRC_POL_DEFAULT 0x04C11DB7 -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ BEGIN_DECLS @@ -104,10 +105,3 @@ END_DECLS /**@}*/ -#endif -/** @cond */ -#else -#warning "crc_v2.h should not be included explicitly, only via crc.h" -#endif -/** @endcond */ - diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h index 7a241ab8..258af88b 100644 --- a/include/libopencm3/stm32/common/dac_common_all.h +++ b/include/libopencm3/stm32/common/dac_common_all.h @@ -77,6 +77,10 @@ specific memorymap.h header before including this header file.*/ /* DAC channel2 data output register (DAC_DOR2) */ #define DAC_DOR2 MMIO32(DAC_BASE + 0x30) +/** DAC status register. + * @note not available on F1 + */ +#define DAC_SR MMIO32(DAC_BASE + 0x34) /* --- DAC_CR values ------------------------------------------------------- */ @@ -377,6 +381,15 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 #define DAC_DOR2_DACC2DOR_LSB (1 << 0) #define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) +/** @defgroup dac_sr_values DAC_SR Values +@{*/ +/** DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR1 (1 << 13) + +/** DAC channel 2 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) +/*@}*/ + /** DAC channel identifier */ typedef enum { CHANNEL_1, CHANNEL_2, CHANNEL_D diff --git a/include/libopencm3/stm32/common/dma2d_common_f47.h b/include/libopencm3/stm32/common/dma2d_common_f47.h new file mode 100644 index 00000000..d66e37e3 --- /dev/null +++ b/include/libopencm3/stm32/common/dma2d_common_f47.h @@ -0,0 +1,188 @@ +/** @addtogroup dma2d_defines + * + * @version 1.0.0 + * + * @date 15 August 2016 + * + * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx + * series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * STM32F4xx/STM32F7xx DMA2D Register defines + * + * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com> + * + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <libopencm3/stm32/memorymap.h> +#include <stdint.h> + +#ifndef DMA2D_H +#define DMA2D_H + +/**@{*/ + +/** DMA2D Control Register */ +#define DMA2D_CR MMIO32(DMA2D_BASE + 0x0U) +#define DMA2D_CR_MODE_SHIFT 16 +#define DMA2D_CR_MODE_MASK 0x3 +#define DMA2D_CR_MODE_M2M 0 /* memory to memory */ +#define DMA2D_CR_MODE_M2MWPFC 1 /* memory to memory with pix convert */ +#define DMA2D_CR_MODE_M2MWB 2 /* memory to memory with blend */ +#define DMA2D_CR_MODE_R2M 3 /* register to memory */ +#define DMA2D_CR_CEIE (1 << 13) +#define DMA2D_CR_CTCIE (1 << 12) +#define DMA2D_CR_CAEIE (1 << 11) +#define DMA2D_CR_TWIE (1 << 10) +#define DMA2D_CR_TCIE (1 << 9) +#define DMA2D_CR_TEIE (1 << 8) +#define DMA2D_CR_ABORT (1 << 2) +#define DMA2D_CR_SUSP (1 << 1) +#define DMA2D_CR_START (1 << 0) + +/** DMA2D Interrupt Status Register */ +#define DMA2D_ISR MMIO32(DMA2D_BASE + 0x4U) +#define DMA2D_ISR_CEIF (1 << 5) +#define DMA2D_ISR_CTCIF (1 << 4) +#define DMA2D_ISR_CAEIF (1 << 3) +#define DMA2D_ISR_TWIF (1 << 2) +#define DMA2D_ISR_TCIF (1 << 1) +#define DMA2D_ISR_TEIF (1 << 0) + +/** DMA2D Interrupt Flag Clear Register */ +#define DMA2D_IFCR MMIO32(DMA2D_BASE + 0x8U) +#define DMA2D_IFCR_CCEIF (1 << 5) +#define DMA2D_IFCR_CCTCIF (1 << 4) +#define DMA2D_IFCR_CCAEIF (1 << 3) +#define DMA2D_IFCR_CTWIF (1 << 2) +#define DMA2D_IFCR_CTCIF (1 << 1) +#define DMA2D_IFCR_CTEIF (1 << 0) + +/** DMA2D Foreground Memory Address Register */ +#define DMA2D_FGMAR MMIO32(DMA2D_BASE + 0xCU) + +/** DMA2D Foreground Offset Register */ +#define DMA2D_FGOR MMIO32(DMA2D_BASE + 0x10U) +#define DMA2D_FGOR_LO_SHIFT 0 +#define DMA2D_FGOR_LO_MASK 0x3fff + +/** DMA2D Background Memory Address Register */ +#define DMA2D_BGMAR MMIO32(DMA2D_BASE + 0x14U) + +/** DMA2D Background Offset Register */ +#define DMA2D_BGOR MMIO32(DMA2D_BASE + 0x18U) +#define DMA2D_BGOR_LO_SHIFT 0 +#define DMA2D_BGOR_LO_MASK 0x3fff + +/** DMA2D Foreground and Background PFC Control Register */ +#define DMA2D_FGPFCCR MMIO32(DMA2D_BASE + 0x1cU) +#define DMA2D_BGPFCCR MMIO32(DMA2D_BASE + 0x24U) + +#define DMA2D_xPFCCR_ALPHA_SHIFT 24 +#define DMA2D_xPFCCR_ALPHA_MASK 0xff +#define DMA2D_xPFCCR_AM_SHIFT 16 +#define DMA2D_xPFCCR_AM_MASK 0x3 +#define DMA2D_xPFCCR_AM_NONE 0 +#define DMA2D_xPFCCR_AM_FORCE 1 +#define DMA2D_xPFCCR_AM_PRODUCT 2 +#define DMA2D_xPFCCR_CS_SHIFT 8 +#define DMA2D_xPFCCR_CS_MASK 0xff +#define DMA2D_xPFCCR_START (1 << 5) +#define DMA2D_xPFCCR_CCM_ARGB8888 (0 << 4) +#define DMA2D_xPFCCR_CCM_RGB888 (1 << 4) +#define DMA2D_xPFCCR_CM_SHIFT 0 +#define DMA2D_xPFCCR_CM_MASK 0xf +#define DMA2D_xPFCCR_CM_ARGB8888 0 +#define DMA2D_xPFCCR_CM_RGB888 1 +#define DMA2D_xPFCCR_CM_RGB565 2 +#define DMA2D_xPFCCR_CM_ARGB1555 3 +#define DMA2D_xPFCCR_CM_ARGB4444 4 +#define DMA2D_xPFCCR_CM_L8 5 +#define DMA2D_xPFCCR_CM_AL44 6 +#define DMA2D_xPFCCR_CM_AL88 7 +#define DMA2D_xPFCCR_CM_L4 8 +#define DMA2D_xPFCCR_CM_A8 9 +#define DMA2D_xPFCCR_CM_A4 10 + +/** DMA2D Foreground and Background Color Register */ +#define DMA2D_FGCOLR MMIO32(DMA2D_BASE + 0x20U) +#define DMA2D_BGCOLR MMIO32(DMA2D_BASE + 0x28U) +#define DMA2D_xCOLR_RED_SHIFT 16 +#define DMA2D_xCOLR_RED_MASK 0xff +#define DMA2D_xCOLR_GREEN_SHIFT 8 +#define DMA2D_xCOLR_GREEN_MASK 0xff +#define DMA2D_xCOLR_BLUE_SHIFT 0 +#define DMA2D_xCOLR_BLUE_MASK 0xff + +/** DMA2D Foreground CLUT Memory Address Register */ +#define DMA2D_FGCMAR MMIO32(DMA2D_BASE + 0x2CU) + +/** DMA2D Background CLUT Memory Address Register */ +#define DMA2D_BGCMAR MMIO32(DMA2D_BASE + 0x30U) + +/** DMA2D Output PFC Control Register */ +#define DMA2D_OPFCCR MMIO32(DMA2D_BASE + 0x34U) +#define DMA2D_OPFCCR_CM_SHIFT 0 +#define DMA2D_OPFCCR_CM_MASK 0x3 +#define DMA2D_OPFCCR_CM_ARGB8888 0 +#define DMA2D_OPFCCR_CM_RGB888 1 +#define DMA2D_OPFCCR_CM_RGB565 2 +#define DMA2D_OPFCCR_CM_ARGB1555 3 +#define DMA2D_OPFCCR_CM_ARGB4444 4 + +/** DMA2D Output Color Register */ +/* The format of this register depends on PFC control above */ +#define DMA2D_OCOLR MMIO32(DMA2D_BASE + 0x38U) + +/** DMA2D Output Memory Address Register */ +#define DMA2D_OMAR MMIO32(DMA2D_BASE + 0x3CU) + +/** DMA2D Output offset Register */ +#define DMA2D_OOR MMIO32(DMA2D_BASE + 0x40U) +#define DMA2D_OOR_LO_SHIFT 0 +#define DMA2D_OOR_LO_MASK 0x3fff + +/** DMA2D Number of Lines Register */ +#define DMA2D_NLR MMIO32(DMA2D_BASE + 0x44U) +#define DMA2D_NLR_PL_SHIFT 16 +#define DMA2D_NLR_PL_MASK 0x3fff +#define DMA2D_NLR_NL_SHIFT 0 +#define DMA2D_NLR_NL_MASK 0xffff + +/** DMA2D Line Watermark Register */ +#define DMA2D_LWR MMIO32(DMA2D_BASE + 0x48U) +#define DMA2D_LWR_LW_SHIFT 0 +#define DMA2D_LWR_LW_MASK 0xffff + +/** DMA2D AHB Master Timer Config Register */ +#define DMA2D_AMTCR MMIO32(DMA2D_BASE + 0x4CU) +#define DMA2D_AMTCR_DT_SHIFT 8 +#define DMA2D_AMTCR_DT_MASK 0xff +#define DMA2D_AMTCR_EN (1 << 0) + +/** DMA2D Foreground Color Lookup table */ +#define DMA2D_FG_CLUT (uint32_t *)(DMA2D_BASE + 0x400U) + +/** DMA2D Background Color Lookup table */ +#define DMA2D_BG_CLUT (uint32_t *)(DMA2D_BASE + 0x800U) + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/common/dma_common_csel.h b/include/libopencm3/stm32/common/dma_common_csel.h new file mode 100644 index 00000000..755bb1df --- /dev/null +++ b/include/libopencm3/stm32/common/dma_common_csel.h @@ -0,0 +1,56 @@ +/** @addtogroup dma_defines +*/ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +The order of header inclusion is important. dma.h includes the device +specific memorymap.h header before including this header file.*/ + +/**@{*/ + +/** @cond */ +#ifdef LIBOPENCM3_DMA_H +/** @endcond */ +#pragma once + + +/* DMA channel selection register (DMAx_CSELR) */ +#define DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8) +#define DMA1_CSELR DMA_CSELR(DMA1) +#define DMA2_CSELR DMA_CSELR(DMA2) + +/* --- DMA_CSELR values -------------------------------------------- */ + +#define DMA_CSELR_CxS_SHIFT(channel) (4 * ((channel) - 1)) +#define DMA_CSELR_CxS_MASK (0x0f) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dma_set_channel_request(uint32_t dma, uint8_t channel, uint8_t request); + +END_DECLS + +/** @cond */ +#else +#warning "dma_common_csel.h should not be included explicitly, only via dma.h" +#endif +/** @endcond */ + +/**@}*/ diff --git a/include/libopencm3/stm32/common/dsi_common_f47.h b/include/libopencm3/stm32/common/dsi_common_f47.h new file mode 100644 index 00000000..963c3dc0 --- /dev/null +++ b/include/libopencm3/stm32/common/dsi_common_f47.h @@ -0,0 +1,824 @@ +/** @addtogroup dsi_defines + * + * @version 1.0.0 + * + * @date 7 July 2016 + * + * @author @htmlonly © @endhtmlonly 2016 + * Chuck McManis <cmcmanis@mcmanis.com> + * + * This library supports the Display Serial Interface Host and Wrapper in + * the STM32F4xx and STM32F7xx series of ARM Cortex Microcontrollers by + * ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * STM32F4/7 DSI Host Defines + * + * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com> + * + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/stm32/memorymap.h> + +/** @cond */ +#ifndef DSI_H +/** @endcond */ +#define DSI_H + +/**@{*/ + + +/** + * DSI Host Version Register + */ +#define DSI_VR MMIO32(DSI_BASE + 0x0U) + +/** + * DSI Host Control Register + */ +#define DSI_CR MMIO32(DSI_BASE + 0x4U) +#define DSI_CR_EN (1 << 0) + +/** + * DSI Host Clock Control Register + */ +#define DSI_CCR MMIO32(DSI_BASE + 0x8U) +#define DSI_CCR_TOCKDIV_SHIFT 8 +#define DSI_CCR_TOCKDIV_MASK 0xff +#define DSI_CCR_TXECKDIV_SHIFT 0 +#define DSI_CCR_TXECKDIV_MASK 0xff + +/** + * DSI Host LTDC VCID Register + */ +#define DSI_LVCIDR MMIO32(DSI_BASE + 0xcU) +#define DSI_LVCIDR_VCID_SHIFT 0 +#define DSI_LVCIDR_VCID_MASK 0x3 + +/** + * DSI Host LTDC Color Coding Register + */ +#define DSI_LCOLCR MMIO32(DSI_BASE + 0x10U) +#define DSI_LCOLCR_LPE (1 << 8) +#define DSI_LCOLCR_COLC_SHIFT 0 +#define DSI_LCOLCR_COLC_MASK 0xf + +/** + * DSI Host LTDC Polarity Configuration Register + */ +#define DSI_LPCR MMIO32(DSI_BASE + 0x14U) +#define DSI_LPCR_HSP (1 << 2) +#define DSI_LPCR_VSP (1 << 1) +#define DSI_LPCR_DEP (1 << 0) + +/** + * DSI Host Low-power Configuration Register + */ +#define DSI_LPMCR MMIO32(DSI_BASE + 0x18U) +#define DSI_LPMCR_LPSIZE_SHIFT 16 +#define DSI_LPMCR_LPSIZE_MASK 0xff +#define DSI_LPMCR_VLPSIZE_SHIFT 0 +#define DSI_LPMCR_VLPSIZE_MASK 0xff + +/** + * DSI Host Protocol Configuration Register + */ +#define DSI_PCR MMIO32(DSI_BASE + 0x2cU) +#define DSI_PCR_CRCRXE (1 << 4) +#define DSI_PCR_ECCRXE (1 << 3) +#define DSI_PCR_BTAE (1 << 2) +#define DSI_PCR_ETRXE (1 << 1) +#define DSI_PCR_ETTXE (1 << 0) + +/** + * DSI Host Generic VCID Register + */ +#define DSI_GVCIDR MMIO32(DSI_BASE + 0x30U) +#define DSI_GVCIDR_VCID_SHIFT 0 +#define DSI_GVCIDR_VCID_MASK 0x3 + +/** + * DSI Host mode Configuration Register + */ +#define DSI_MCR MMIO32(DSI_BASE + 0x34U) +#define DSI_MCR_CMDM (1 << 0) + +/** + * DSI Host Video mode Configuration Register + */ +#define DSI_VMCR MMIO32(DSI_BASE + 0x38U) +#define DSI_VMCR_PGO (1 << 24) +#define DSI_VMCR_PGM (1 << 20) +#define DSI_VMCR_PGE (1 << 16) +#define DSI_VMCR_LPCE (1 << 15) +#define DSI_VMCR_FBTAAE (1 << 14) +#define DSI_VMCR_LPHFPE (1 << 13) +#define DSI_VMCR_LPHBPE (1 << 12) +#define DSI_VMCR_LPVAE (1 << 11) +#define DSI_VMCR_LPVFPE (1 << 10) +#define DSI_VMCR_LPVBPE (1 << 9) +#define DSI_VMCR_LPVSAE (1 << 8) +#define DSI_VMCR_VMT_SHIFT 0 +#define DSI_VMCR_VMT_MASK 0x3 +#define DSI_VMCR_VMT_NON_BURST_PULSE 0x0 +#define DSI_VMCR_VMT_NON_BURSE_EVENT 0x1 +#define DSI_VMCR_VMT_BURST 0x2 + +/** + * DSI Host Video Packet Configuration Register + */ +#define DSI_VPCR MMIO32(DSI_BASE + 0x3CU) +#define DSI_VPCR_VPSIZE_SHIFT 0 +#define DSI_VPCR_VPSIZE_MASK 0x3fff + +/** + * DSI Host Video Chunks Configuration Register + */ +#define DSI_VCCR MMIO32(DSI_BASE + 0x40U) +#define DSI_VCCR_NUMC_SHIFT 0 +#define DSI_VCCR_NUMC_MASK 0x1fff + +/** + * DSI Host Video Null Packet Configuration Register + */ +#define DSI_VNPCR MMIO32(DSI_BASE + 0x44U) +#define DSI_VNPCR_NPSIZE_SHIFT 0 +#define DSI_VNPCR_NPSIZE_MASK 0x1fff + +/** + * DSI Host Video HSA Configuration Register + */ +#define DSI_VHSACR MMIO32(DSI_BASE + 0x48U) +#define DSI_VHSACR_HSA_SHIFT 0 +#define DSI_VHSACR_HSA_MASK 0xfff + +/** + * DSI Host Video HBP Configuration Register + */ +#define DSI_VHBPCR MMIO32(DSI_BASE + 0x4CU) +#define DSI_VHBPCR_HBP_SHIFT 0 +#define DSI_VHBPCR_HBP_MASK 0xfff + +/** + * DSI Host Video Line Configuration Register + */ +#define DSI_VLCR MMIO32(DSI_BASE + 0x50U) +#define DSI_VLCR_HLINE_SHIFT 0 +#define DSI_VLCR_HLINE_MASK 0x7fff + +/** + * DSI Host Video VSA Configuration Register + */ +#define DSI_VVSACR MMIO32(DSI_BASE + 0x54U) +#define DSI_VVSACR_VSA_SHIFT 0 +#define DSI_VVSACR_VSA_MASK 0x3ff + +/** + * DSI Host Video VBP Configuration Register + */ +#define DSI_VVBPCR MMIO32(DSI_BASE + 0x58U) +#define DSI_VVBPCR_VBP_SHIFT 0 +#define DSI_VVBPCR_VBP_MASK 0x3ff + +/** + * DSI Host Video VFP Configuration Register + */ +#define DSI_VVFPCR MMIO32(DSI_BASE + 0x5CU) +#define DSI_VVFPCR_VFP_SHIFT 0 +#define DSI_VVFPCR_VFP_MASK 0x3ff + +/** + * DSI Host Video VA Configuration Register + */ +#define DSI_VVACR MMIO32(DSI_BASE + 0x60U) +#define DSI_VVACR_VA_SHIFT 0 +#define DSI_VVACR_VA_MASK 0x3fff + +/** + * DSI Host LTDC Command Configuration Register + */ +#define DSI_LCCR MMIO32(DSI_BASE + 0x64U) +#define DSI_LCCR_CMDSIZE_SHIFT 0 +#define DSI_LCCR_CMDSIZE_MASK 0xffff + +/** + * DSI Host Command mode Configuration Register + */ +#define DSI_CMCR MMIO32(DSI_BASE + 0x68U) +#define DSI_CMCR_MRDPS (1 << 24) +#define DSI_CMCR_DLWTX (1 << 19) +#define DSI_CMCR_DSR0TX (1 << 18) +#define DSI_CMCR_DSW1TX (1 << 17) +#define DSI_CMCR_DSW0TX (1 << 16) +/* Bit 15 reserved */ +#define DSI_CMCR_GLWTX (1 << 14) +#define DSI_CMCR_GSR2TX (1 << 13) +#define DSI_CMCR_GSR1TX (1 << 12) +#define DSI_CMCR_GSR0TX (1 << 11) +#define DSI_CMCR_GSW2TX (1 << 10) +#define DSI_CMCR_GSW1TX (1 << 9) +#define DSI_CMCR_GSW0TX (1 << 8) +/* Bits 7:2 Reserved */ +#define DSI_CMCR_ARE (1 << 1) +#define DSI_CMCR_TEARE (1 << 0) + +/** + * DSI Host Generic Header Configuration Register + */ +#define DSI_GHCR MMIO32(DSI_BASE + 0x6CU) +#define DSI_GHCR_WCMSB_SHIFT 16 +#define DSI_GHCR_WCMSB_MASK 0xff +#define DSI_GHCR_WCLSB_SHIFT 8 +#define DSI_GHCR_WCLSB_MASK 0xff +#define DSI_GHCR_DATA1_SHIFT 16 /* data 1 in 'short' mode */ +#define DSI_GHCR_DATA1_MASK 0xff +#define DSI_GHCR_DATA0_SHIFT 8 /* data 0 in 'short' mode */ +#define DSI_GHCR_DATA0_MASK 0xff +#define DSI_GHCR_VCID_SHIFT 6 +#define DSI_GHCR_VCID_MASK 0x3 +#define DSI_GHCR_DT_SHIFT 0 +#define DSI_GHCR_DT_MASK 0x3f + +/** + * DSI Host Generic Payload Data Register + */ +#define DSI_GPDR MMIO32(DSI_BASE + 0x70U) +#define DSI_GPDR_BYTE4_SHIFT 24 +#define DSI_GPDR_BYTE4_MASK 0xff +#define DSI_GPDR_BYTE3_SHIFT 16 +#define DSI_GPDR_BYTE3_MASK 0xff +#define DSI_GPDR_BYTE2_SHIFT 8 +#define DSI_GPDR_BYTE2_MASK 0xff +#define DSI_GPDR_BYTE1_SHIFT 0 +#define DSI_GPDR_BYTE1_MASK 0xff + +/** + * DSI Host Generate Packet Status Register + */ +#define DSI_GPSR MMIO32(DSI_BASE + 0x74U) +/* Reserved 31:7 */ +#define DSI_GPSR_RCB (1 << 6) +#define DSI_GPSR_PRDFF (1 << 5) +#define DSI_GPSR_PRDFE (1 << 4) +#define DSI_GPSR_PWRFF (1 << 3) +#define DSI_GPSR_PWRFE (1 << 2) +#define DSI_GPSR_CMDFF (1 << 1) +#define DSI_GPSR_CMDFE (1 << 0) + +/** + * DSI Host Timeout Counter Configuration Register + */ +#define DSI_TCCR0 MMIO32(DSI_BASE + 0x78U) +#define DSI_TCCR0_HSTX_TOCNT_SHIFT 16 +#define DSI_TCCR0_HSTX_TOCNT_MASK 0xffff +#define DSI_TCCR0_LPRX_TOCNT_SHIFT 0 +#define DSI_TCCR0_LPRX_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 1 + */ +#define DSI_TCCR1 MMIO32(DSI_BASE + 0x7CU) +#define DSI_TCCR1_HSRD_TOCNT_SHIFT 0 +#define DSI_TCCR1_HSRD_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 2 + */ +#define DSI_TCCR2 MMIO32(DSI_BASE + 0x80U) +#define DSI_TCCR2_LPRD_TOCNT_SHIFT 0 +#define DSI_TCCR2_LPRD_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 3 + */ +#define DSI_TCCR3 MMIO32(DSI_BASE + 0x84U) +#define DSI_TCCR3_PM (1 << 24) +#define DSI_TCCR3_HSWR_TOCNT_SHIFT 0 +#define DSI_TCCR3_HSWR_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 4 + */ +#define DSI_TCCR4 MMIO32(DSI_BASE + 0x88U) +#define DSI_TCCR4_LPWR_TOCNT_SHIFT 0 +#define DSI_TCCR4_LPWR_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 5 + */ +#define DSI_TCCR5 MMIO32(DSI_BASE + 0x8CU) +#define DSI_TCCR5_BTA_TOCNT_SHIFT 0 +#define DSI_TCCR5_BTA_TOCNT_MASK 0xffff + +/** + * DSI Host Clock Lane Configuration Register + */ +#define DSI_CLCR MMIO32(DSI_BASE + 0x94U) +#define DSI_CLCR_ACR (1 << 1) +#define DSI_CLCR_DPCC (1 << 0) + +/** + * DSI Host Clock Lane Timer Configuration Register + */ +#define DSI_CLTCR MMIO32(DSI_BASE + 0x98U) +#define DSI_CLTCR_HS2LP_TIME_SHIFT 16 +#define DSI_CLTCR_HS2LP_TIME_MASK 0x3ff +#define DSI_CLTCR_LP2HS_TIME_SHIFT 0 +#define DSI_CLTCR_LP2HS_TIME_MASK 0x3ff + +/** + * DSI Host Data Lane Time Configuration Register + */ +#define DSI_DLTCR MMIO32(DSI_BASE + 0x9CU) +#define DSI_DLTCR_HS2LP_TIME_SHIFT 24 +#define DSI_DLTCR_HS2LP_TIME_MASK 0xff +#define DSI_DLTCR_LP2HS_TIME_SHIFT 16 +#define DSI_DLTCR_LP2HS_TIME_MASK 0xff +#define DSI_DLTCR_MRD_TIME_SHIFT 0 +#define DSI_DLTCR_MRD_TIME_MASK 0x7fff + +/** + * DSI Host PHY Control Register + */ +#define DSI_PCTLR MMIO32(DSI_BASE + 0xA0U) +#define DSI_PCTLR_CKE (1 << 2) +#define DSI_PCTLR_DEN (1 << 1) + +/** + * DSI Host PHY Configuration Register + */ +#define DSI_PCONFR MMIO32(DSI_BASE + 0xA4U) +#define DSI_PCONFR_SW_TIME_SHIFT 8 +#define DSI_PCONFR_SW_TIME_MASK 0xff +#define DSI_PCONFR_NL_SHIFT 0 +#define DSI_PCONFR_NL_MASK 0x3 +#define DSI_PCONFR_NL_1LANE 0 +#define DSI_PCONFR_NL_2LANE 1 + +/** + * DSI Host PHY ULPS Control Register + */ +#define DSI_PUCR MMIO32(DSI_BASE + 0xA8U) +#define DSI_PUCR_UEDL (1 << 3) +#define DSI_PUCR_URDL (1 << 2) +#define DSI_PUCR_UECL (1 << 1) +#define DSI_PUCR_URCL (1 << 0) + +/** + * DSI Host PHY TX Triggers Configuration Register + */ +#define DSI_PTTCR MMIO32(DSI_BASE + 0xACU) +#define DSI_PTTCR_TX_TRIG_SHIFT 0 +#define DSI_PTTCR_TX_TRIG_MASK 0xf +#define DSI_PTTCR_TX_TRIG_1 0x1 +#define DSI_PTTCR_TX_TRIG_2 0x2 +#define DSI_PTTCR_TX_TRIG_3 0x4 +#define DSI_PTTCR_TX_TRIG_4 0x8 + +/** + * DSI Host PHY Status Register + */ +#define DSI_PSR MMIO32(DSI_BASE + 0xB0U) +#define DSI_PSR_UAN1 (1 << 8) +#define DSI_PSR_PSS1 (1 << 7) +#define DSI_PSR_RUE0 (1 << 6) +#define DSI_PSR_UAN0 (1 << 5) +#define DSI_PSR_PSS0 (1 << 4) +#define DSI_PSR_UANC (1 << 3) +#define DSI_PSR_PSSC (1 << 2) +#define DSI_PSR_PD (1 << 1) + +/** + * DSI Host Interrupt & Status Register 0 + */ +#define DSI_ISR0 MMIO32(DSI_BASE + 0xBCU) +#define DSI_ISR0_PE4 (1 << 20) +#define DSI_ISR0_PE3 (1 << 19) +#define DSI_ISR0_PE2 (1 << 18) +#define DSI_ISR0_PE1 (1 << 17) +#define DSI_ISR0_PE0 (1 << 16) +#define DSI_ISR0_AE15 (1 << 15) +#define DSI_ISR0_AE14 (1 << 14) +#define DSI_ISR0_AE13 (1 << 13) +#define DSI_ISR0_AE12 (1 << 12) +#define DSI_ISR0_AE11 (1 << 11) +#define DSI_ISR0_AE10 (1 << 10) +#define DSI_ISR0_AE9 (1 << 9) +#define DSI_ISR0_AE8 (1 << 8) +#define DSI_ISR0_AE7 (1 << 7) +#define DSI_ISR0_AE6 (1 << 6) +#define DSI_ISR0_AE5 (1 << 5) +#define DSI_ISR0_AE4 (1 << 4) +#define DSI_ISR0_AE3 (1 << 3) +#define DSI_ISR0_AE2 (1 << 2) +#define DSI_ISR0_AE1 (1 << 1) +#define DSI_ISR0_AE0 (1 << 0) + +/** + * DSI Host Interrupt & Status Register 1 + */ +#define DSI_ISR1 MMIO32(DSI_BASE + 0xC0U) +#define DSI_ISR1_GPRXE (1 << 12) +#define DSI_ISR1_GPRDE (1 << 11) +#define DSI_ISR1_GPTXE (1 << 10) +#define DSI_ISR1_GPWRE (1 << 9) +#define DSI_ISR1_GCWRE (1 << 8) +#define DSI_ISR1_LPWRE (1 << 7) +#define DSI_ISR1_EOTPE (1 << 6) +#define DSI_ISR1_PSE (1 << 5) +#define DSI_ISR1_CRCE (1 << 4) +#define DSI_ISR1_ECCME (1 << 3) +#define DSI_ISR1_ECCSE (1 << 2) +#define DSI_ISR1_TOLPRX (1 << 1) +#define DSI_ISR1_TOHSTX (1 << 0) + +/** + * DSI Host Interrupt Enable Register 0 + */ +#define DSI_IER0 MMIO32(DSI_BASE + 0xC4U) +#define DSI_IER0_PE4IE (1 << 20) +#define DSI_IER0_PE3IE (1 << 19) +#define DSI_IER0_PE2IE (1 << 18) +#define DSI_IER0_PE1IE (1 << 17) +#define DSI_IER0_PE0IE (1 << 16) +#define DSI_IER0_AE15IE (1 << 15) +#define DSI_IER0_AE14IE (1 << 14) +#define DSI_IER0_AE13IE (1 << 13) +#define DSI_IER0_AE12IE (1 << 12) +#define DSI_IER0_AE11IE (1 << 11) +#define DSI_IER0_AE10IE (1 << 10) +#define DSI_IER0_AE9IE (1 << 9) +#define DSI_IER0_AE8IE (1 << 8) +#define DSI_IER0_AE7IE (1 << 7) +#define DSI_IER0_AE6IE (1 << 6) +#define DSI_IER0_AE5IE (1 << 5) +#define DSI_IER0_AE4IE (1 << 4) +#define DSI_IER0_AE3IE (1 << 3) +#define DSI_IER0_AE2IE (1 << 2) +#define DSI_IER0_AE1IE (1 << 1) +#define DSI_IER0_AE0IE (1 << 0) + +/** + * DSI Host Interrupt Enable Register 1 + */ +#define DSI_IER1 MMIO32(DSI_BASE + 0xC8U) +#define DSI_IER1_GPRXEIE (1 << 12) +#define DSI_IER1_GPRDEIE (1 << 11) +#define DSI_IER1_GPTXEIE (1 << 10) +#define DSI_IER1_GPWREIE (1 << 9) +#define DSI_IER1_GCWREIE (1 << 8) +#define DSI_IER1_LPWREIE (1 << 7) +#define DSI_IER1_EOTPEIE (1 << 6) +#define DSI_IER1_PSEIE (1 << 5) +#define DSI_IER1_CRCEIE (1 << 4) +#define DSI_IER1_ECCMEIE (1 << 3) +#define DSI_IER1_ECCSEIE (1 << 2) +#define DSI_IER1_TOLPRXIE (1 << 1) +#define DSI_IER1_TOHSTXIE (1 << 0) + +/** + * DSI Host Force Interrupt Register 0 + */ +#define DSI_FIR0 MMIO32(DSI_BASE + 0xD8U) +#define DSI_FIR0_FPE4 (1 << 20) +#define DSI_FIR0_FPE3 (1 << 19) +#define DSI_FIR0_FPE2 (1 << 18) +#define DSI_FIR0_FPE1 (1 << 17) +#define DSI_FIR0_FPE0 (1 << 16) +#define DSI_FIR0_FAE15 (1 << 15) +#define DSI_FIR0_FAE14 (1 << 14) +#define DSI_FIR0_FAE13 (1 << 13) +#define DSI_FIR0_FAE12 (1 << 12) +#define DSI_FIR0_FAE11 (1 << 11) +#define DSI_FIR0_FAE10 (1 << 10) +#define DSI_FIR0_FAE9 (1 << 9) +#define DSI_FIR0_FAE8 (1 << 8) +#define DSI_FIR0_FAE7 (1 << 7) +#define DSI_FIR0_FAE6 (1 << 6) +#define DSI_FIR0_FAE5 (1 << 5) +#define DSI_FIR0_FAE4 (1 << 4) +#define DSI_FIR0_FAE3 (1 << 3) +#define DSI_FIR0_FAE2 (1 << 2) +#define DSI_FIR0_FAE1 (1 << 1) +#define DSI_FIR0_FAE0 (1 << 0) + +/** + * DSI Host Force Interrupt Register 1 + */ +#define DSI_FIR1 MMIO32(DSI_BASE + 0xDCU) +#define DSI_FIR1_FGPRXE (1 << 12) +#define DSI_FIR1_FGPRDE (1 << 11) +#define DSI_FIR1_FGPTXE (1 << 10) +#define DSI_FIR1_FGPWRE (1 << 9) +#define DSI_FIR1_FGCWRE (1 << 8) +#define DSI_FIR1_FLPWRE (1 << 7) +#define DSI_FIR1_FEOTPE (1 << 6) +#define DSI_FIR1_FPSE (1 << 5) +#define DSI_FIR1_FCRCE (1 << 4) +#define DSI_FIR1_FECCME (1 << 3) +#define DSI_FIR1_FECCSE (1 << 2) +#define DSI_FIR1_FTOLPRX (1 << 1) +#define DSI_FIR1_FTOHSTX (1 << 0) + +/** + * DSI Host Video Shadow Control Register + */ +#define DSI_VSCR MMIO32(DSI_BASE + 0x100U) +#define DSI_VSCR_UR (1 << 8) +#define DSI_VSCR_EN (1 << 0) + +/** + * DSI Host LTDC Current VCID Register + */ +#define DSI_LCVCIDR MMIO32(DSI_BASE + 0x10CU) +#define DSI_LCVCIDR_VCID_SHIFT 0 +#define DSI_LCVCIDR_VCID_MASK 0x3 + +/** + * DSI Host LTCD Current Color Coding Register + */ +#define DSI_LCCCR MMIO32(DSI_BASE + 0x110U) +#define DSI_LCCR_LPE (1 << 8) +#define DSI_LCCR_COLC_SHIFT 0 +#define DSI_LCCR_COLC_MASK 0xf + +/** + * DSI Host Low-power mode Current Configuration Register + */ +#define DSI_LPMCCR MMIO32(DSI_BASE + 0x118U) +#define DSI_LPMCCR_LPSIZE_SHIFT 16 +#define DSI_LPMCCR_LPSIZE_MASK 0xff +#define DSI_LPMCCR_VLPSIZE_SHIFT 0 +#define DSI_LPMCCR_VLPSIZE_MASK 0xff + +/** + * DSI Host Video mode Current Configuration Register + */ +#define DSI_VMCCR MMIO32(DSI_BASE + 0x138U) +#define DSI_VMCCR_LPCE (1 << 9) +#define DSI_VMCCR_FBTAAE (1 << 8) +#define DSI_VMCCR_LPHFE (1 << 7) +#define DSI_VMCCR_LPHBPE (1 << 6) +#define DSI_VMCCR_LPVAE (1 << 5) +#define DSI_VMCCR_LPVFPE (1 << 4) +#define DSI_VMCCR_LPVBPE (1 << 3) +#define DSI_VMCCR_LPVSAE (1 << 2) +#define DSI_VMCCR_VMT_SHIFT 0 +#define DSI_VMCCR_VMT_MASK 0x3 + +/** + * DSI Host Video Packet Current Configuration Register + */ +#define DSI_VPCCR MMIO32(DSI_BASE + 0x13CU) +#define DSI_VPCCR_VPSIZE_SHIFT 0 +#define DSI_VPCCR_VPSIZE_MASK 0x3fff + +/** + * DSI Host Video Chunks Current Configuration Register + */ +#define DSI_VCCCR MMIO32(DSI_BASE + 0x140U) +#define DSI_VCCCR_NUMC_SHIFT 0 +#define DSI_VCCCR_NUMC_MASK 0x1fff + +/** + * DSI Host Video Null Packet Current Configuration Register + */ +#define DSI_VNPCCR MMIO32(DSI_BASE + 0x144U) +#define DSI_VNPCCR_NPSIZE_SHIFT 0 +#define DSI_VNPCCR_NPSIZE_MASK 0x1fff + +/** + * DSI Host Video HSA Current Configuration Register + */ +#define DSI_VHSACCR MMIO32(DSI_BASE + 0x148U) +#define DSI_VHSACCR_HSA_SHIFT 0 +#define DSI_VHSACCR_HSA_MASK 0xfff + +/** + * DSI Host Video HBP Current Configuration Register + */ +#define DSI_VHBPCCR MMIO32(DSI_BASE + 0x14CU) +#define DSI_VHBPCCR_HBP_SHIFT 0 +#define DSI_VHBPCCR_HBP_MASK 0xfff + +/** + * DSI Host Video Line Current Configuration Register + */ +#define DSI_VLCCR MMIO32(DSI_BASE + 0x150U) +#define DSI_VLCCR_HLINE_SHIFT 0 +#define DSI_VLCCR_HLINE_MASK 0x7fff + +/** + * DSI Host Video VSA Current Configuration Register + */ +#define DSI_VVSACCR MMIO32(DSI_BASE + 0x154U) +#define DSI_VVSACCR_VSA_SHIFT 0 +#define DSI_VVSACCR_VSA_MASK 0x3ff + +/** + * DSI Host Video VBP Current Configuration Register + */ +#define DSI_VVBPCCR MMIO32(DSI_BASE + 0x0158U) +#define DSI_VVBPCCR_VBP_SHIFT 0 +#define DSI_VVBPCCR_VBP_MAST 0x3ff + +/** + * DSI Host Video VFP Current Configuration Register + */ +#define DSI_VVFPCCR MMIO32(DSI_BASE + 0x15CU) +#define DSI_VVFPCCR_VFP_SHIFT 0 +#define DSI_VVFPCCR_VFP_MASK 0x3ff + +/** + * DSI Host Video VA Current Configuration Register + */ +#define DSI_VVACCR MMIO32(DSI_BASE + 0x160U) +#define DSI_VVACCR_VA_SHIFT 0 +#define DSI_VVACCR_VA_MASK 0x3fff + +/** + * DSI Wrapper Configuration Register + */ +#define DSI_WCFGR MMIO32(DSI_BASE + 0x400U) +#define DSI_WCFGR_VSPOL (1 << 7) +#define DSI_WCFGR_AR (1 << 6) +#define DSI_WCFGR_TEPOL (1 << 5) +#define DSI_WCFGR_TESRC (1 << 4) +#define DSI_WCFGR_COLMUX_SHIFT 1 +#define DSI_WCFGR_COLMUX_MASK 7 +#define DSI_WCFGR_DSIM (1 << 0) + +/** + * DSI Wrapper Control Register + */ +#define DSI_WCR MMIO32(DSI_BASE + 0x404U) +#define DSI_WCR_DSIEN (1 << 3) +#define DSI_WCR_LTDCEN (1 << 2) +#define DSI_WCR_SHTDN (1 << 1) +#define DSI_WCR_COLM (1 << 0) + +/** + * DSI Wrapper Interrupt Enable Register + */ +#define DSI_WIER MMIO32(DSI_BASE + 0x408U) +#define DSI_WIER_RRIE (1 << 13) +#define DSI_WIER_PLLUIE (1 << 10) +#define DSI_WIER_PLLLIE (1 << 9) +#define DSI_WIER_ERIE (1 << 1) +#define DSI_WIER_TEIE (1 << 0) + +/** + * DSI Wrapper Interrupt & Status Register + */ +#define DSI_WISR MMIO32(DSI_BASE + 0x40CU) +/* reserved 31:14 */ +#define DSI_WISR_RRIF (1 << 13) +#define DSI_WISR_RRS (1 << 12) +#define DSI_WISR_PLLUIF (1 << 10) +#define DSI_WISR_PLLLIF (1 << 9) +#define DSI_WISR_PLLLS (1 << 8) +/* reserved 7:3 */ +#define DSI_WISR_BUSY (1 << 2) +#define DSI_WISR_ERIF (1 << 1) +#define DSI_WISR_TEIF (1 << 0) + +/** + * DSI Wrapper Interrupt Flag Clear Register + */ +#define DSI_WIFCR MMIO32(DSI_BASE + 0x410U) +/* reserved 31:14 */ +#define DSI_WIFCR_CRRIF (1 << 13) +/* reserved 12:11 */ +#define DSI_WIFCR_CPLLUIF (1 << 10) +#define DSI_WIFCR_CPLLLIF (1 << 9) +/* reserved 8:2 */ +#define DSI_WIFCR_CERIF (1 << 1) +#define DSI_WIFCR_CTEIF (1 << 0) + +/** + * DSI Wrapper PHY Configuration Register 0 + */ +#define DSI_WPCR0 MMIO32(DSI_BASE + 0x418U) +#define DSI_WPCR0_TCLKPOSTEN (1 << 27) +#define DSI_WPCR0_TLPXCEN (1 << 26) +#define DSI_WPCR0_THSEXITEN (1 << 25) +#define DSI_WPCR0_TLPXDEN (1 << 24) +#define DSI_WPCR0_THSZEROEN (1 << 23) +#define DSI_WPCR0_THSTRAILEN (1 << 22) +#define DSI_WPCR0_THSPREPEN (1 << 21) +#define DSI_WPCR0_TCLKZEROEN (1 << 20) +#define DSI_WPCR0_TCLKPREPEN (1 << 19) +#define DSI_WPCR0_PDEN (1 << 18) +#define DSI_WPCR0_TDDL (1 << 16) +#define DSI_WPCR0_CDOFFDL (1 << 14) +#define DSI_WPCR0_FTXSMDL (1 << 13) +#define DSI_WPCR0_FTXSMCL (1 << 12) +#define DSI_WPCR0_HSIDL1 (1 << 11) +#define DSI_WPCR0_HSIDL0 (1 << 10) +#define DSI_WPCR0_HSICL (1 << 9) +#define DSI_WPCR0_SWDL1 (1 << 8) +#define DSI_WPCR0_SWDL0 (1 << 7) +#define DSI_WPCR0_SWCL (1 << 6) +#define DSI_WPCR0_UIX4_SHIFT 0 +#define DSI_WPCR0_UIX4_MASK 0x3f + +/** + * DSI Wrapper PHY Configration Register 1 + */ +#define DSI_WPCR1 MMIO32(DSI_BASE + 0x41CU) +#define DSI_WPCR1_LPRXFT_SHIFT 25 +#define DSI_WPCR1_LPRXFT_MASK 0x3 +#define DSI_WPCR1_FLPRXLPM (1 << 22) +#define DSI_WPCR1_HSTXSRCDL_SHIFT 18 +#define DSI_WPCR1_HSTXSRCDL_MASK 0x3 +#define DSI_WPCR1_HSTXSRCCL_SHIFT 16 +#define DSI_WPCR1_HSTXSRCCL_MASK 0x3 +#define DSI_WPCR1_SDDC (1 << 12) +#define DSI_WPCR1_LPSRCDL_SHIFT 8 +#define DSI_WPCR1_LPSRCDL_MASK 0x3 +#define DSI_WPCR1_HSTXDDL_SHIFT 2 +#define DSI_WPCR1_HSTXDDL_MASK 0x3 +#define DSI_WPCR1_HSTXDCL_SHIFT 0 +#define DSI_WPCR1_HSTXDCL_MASK 0x3 + +/** + * DSI Wrapper PHY Configuration Register 2 + */ +#define DSI_WPCR2 MMIO32(DSI_BASE + 0x420U) +#define DSI_WPCR2_THSTRAIL_SHIFT 24 +#define DSI_WPCR2_THSTRAIL_MASK 0xff +#define DSI_WPCR2_THSPREP_SHIFT 16 +#define DSI_WPCR2_THSPREP_MASK 0xff +#define DSI_WPCR2_TCLKZERO_SHIFT 8 +#define DSI_WPCR2_TCLKZERO_MASK 0xff +#define DSI_WPCR2_TCLKPREP_SHIFT 0 +#define DSI_WPCR2_TCLKPREP_MASK 0xff + +/** + * DSI Wrapper PHY Configuration Register 3 + */ +#define DSI_WPCR3 MMIO32(DSI_BASE + 0x424U) +#define DSI_WPCR3_TLPXC_SHIFT 24 +#define DSI_WPCR3_TLPXC_MASK 0xff +#define DSI_WPCR3_THSEXIT_SHIFT 16 +#define DSI_WPCR3_THSEXIT_MASK 0xff +#define DSI_WPCR3_TLPXD_SHIFT 8 +#define DSI_WPCR3_TLPXD_MASK 0xff +#define DSI_WPCR3_THSZERO_SHIFT 0 +#define DSI_WPCR3_THSZERO_MASK 0xff + +/** + * DSI Wrapper PHY Configuration Register 4 + */ +#define DSI_WPCR4 MMIO32(DSI_BASE + 0x428U) +#define DSI_WPCR4_TCLKPOST_SHIFT 0 +#define DSI_WPCR4_TCLKPOST_MASK 0xff + +/** + * DSI Wrapper Regulator and PLL Control Register + */ +#define DSI_WRPCR MMIO32(DSI_BASE + 0x430U) +#define DSI_WRPCR_REGEN (1 << 24) +#define DSI_WRPCR_ODF_SHIFT 16 +#define DSI_WRPCR_ODF_MASK 0x3 +#define DSI_WRPCR_ODF_DIV_1 0 +#define DSI_WRPCR_ODF_DIV_2 1 +#define DSI_WRPCR_ODF_DIV_4 2 +#define DSI_WRPCR_ODF_DIV_8 3 +#define DSI_WRPCR_IDF_SHIFT 11 +#define DSI_WRPCR_IDF_MASK 0xf +#define DSI_WRPCR_IDF_DIV_1 1 +#define DSI_WRPCR_IDF_DIV_2 2 +#define DSI_WRPCR_IDF_DIV_3 3 +#define DSI_WRPCR_IDF_DIV_4 4 +#define DSI_WRPCR_IDF_DIV_5 5 +#define DSI_WRPCR_IDF_DIV_6 6 +#define DSI_WRPCR_IDF_DIV_7 7 +/* valid NDIV values 10 - 125 all other reserved */ +#define DSI_WRPCR_NDIV_SHIFT 2 +#define DSI_WRPCR_NDIV_MASK 0x7f +#define DSI_WRPCR_PLLEN (1 << 0) + +/** @cond */ +#endif +/** @endcond */ +/**@}*/ diff --git a/include/libopencm3/stm32/common/exti_common_all.h b/include/libopencm3/stm32/common/exti_common_all.h index 18596ad4..61753618 100644 --- a/include/libopencm3/stm32/common/exti_common_all.h +++ b/include/libopencm3/stm32/common/exti_common_all.h @@ -29,15 +29,6 @@ #define LIBOPENCM3_EXTI_COMMON_ALL_H /**@{*/ -/* --- EXTI registers ------------------------------------------------------ */ - -#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) -#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) -#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) -#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) -#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) -#define EXTI_PR MMIO32(EXTI_BASE + 0x14) - /* EXTI number definitions */ #define EXTI0 (1 << 0) #define EXTI1 (1 << 1) diff --git a/include/libopencm3/stm32/common/exti_common_v1.h b/include/libopencm3/stm32/common/exti_common_v1.h new file mode 100644 index 00000000..9b091edb --- /dev/null +++ b/include/libopencm3/stm32/common/exti_common_v1.h @@ -0,0 +1,55 @@ +/** @addtogroup exti_defines */ +#pragma once + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @cond */ +#if defined(LIBOPENCM3_EXTI_H) +/** @endcond */ + +/**@{*/ + +/* --- EXTI registers ------------------------------------------------------ */ + +/** @defgroup exti_registers EXTI Registers +@{*/ +/** EXTI Interrupt Mask Registers */ +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +/** EXTI Event Mask Register */ +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +/** EXTI Rising Trigger Selection Register */ +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +/** EXTI Falling Triger Selection Register */ +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +/** EXTI Software Interrupt Event Register */ +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +/** EXTI Pending Register */ +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ + +/** @cond */ +#else +#warning "exti_common_v1.h should not be included directly, only via exti.h" +#endif +/** @endcond */ diff --git a/include/libopencm3/stm32/common/flash_common_l01.h b/include/libopencm3/stm32/common/flash_common_l01.h index 64f2f6a5..442c000f 100644 --- a/include/libopencm3/stm32/common/flash_common_l01.h +++ b/include/libopencm3/stm32/common/flash_common_l01.h @@ -119,6 +119,7 @@ void flash_lock_pecr(void); void flash_unlock_progmem(void); void flash_lock_progmem(void); void flash_lock_option_bytes(void); +void flash_unlock_acr(void); void eeprom_program_word(uint32_t address, uint32_t data); void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words); diff --git a/include/libopencm3/stm32/common/fmc_common_f47.h b/include/libopencm3/stm32/common/fmc_common_f47.h new file mode 100644 index 00000000..91fe410e --- /dev/null +++ b/include/libopencm3/stm32/common/fmc_common_f47.h @@ -0,0 +1,269 @@ +/** @addtogroup fmc_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Chuck McManis <cmcmanis@mcmanis.com> + * + * @date 2013 + * + * This library supports the Flexible Memory Controller (FMC) in the STM32F4xx + * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_FMC_COMMON_F47_H +#define LIBOPENCM3_FMC_COMMON_F47_H + +#ifndef LIBOPENCM3_FSMC_H +#error "This file should not be included directly, it is included with fsmc.h" +#endif + +/* --- Convenience macros -------------------------------------------------- */ +#define FMC_BANK5_BASE 0xa0000000U +#define FMC_BANK6_BASE 0xb0000000U +#define FMC_BANK7_BASE 0xc0000000U +#define FMC_BANK8_BASE 0xd0000000U + +/* --- FMC registers ------------------------------------------------------ */ + +/* SDRAM Control Registers 1 .. 2 */ +#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x)) +#define FMC_SDCR1 FMC_SDCR(0) +#define FMC_SDCR2 FMC_SDCR(1) + + +/* SDRAM Timing Registers 1 .. 2 */ +#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x)) +#define FMC_SDTR1 FMC_SDTR(0) +#define FMC_SDTR2 FMC_SDTR(1) + +/* SDRAM Command Mode Register */ +#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150) + +/* SDRAM Refresh Timer Register */ +#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154) + +/* SDRAM Status Register */ +#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158) + +/* --- FMC_SDCRx values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* RPIPE: Read Pipe */ +#define FMC_SDCR_RPIPE_SHIFT 13 +#define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT) +#define FMC_SDCR_RPIPE_NONE (0 << FMC_SDCR_RPIPE_SHIFT) +#define FMC_SDCR_RPIPE_1CLK (1 << FMC_SDCR_RPIPE_SHIFT) +#define FMC_SDCR_RPIPE_2CLK (2 << FMC_SDCR_RPIPE_SHIFT) + +/* RBURST: Burst Read */ +#define FMC_SDCR_RBURST (1 << 12) + +/* SDCLK: SDRAM Clock Configuration */ +#define FMC_SDCR_SDCLK_SHIFT 10 +#define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT) +#define FMC_SDCR_SDCLK_DISABLE (0 << FMC_SDCR_SDCLK_SHIFT) +#define FMC_SDCR_SDCLK_2HCLK (2 << FMC_SDCR_SDCLK_SHIFT) +#define FMC_SDCR_SDCLK_3HCLK (3 << FMC_SDCR_SDCLK_SHIFT) + +/* WP: Write Protect */ +#define FMC_SDCR_WP_ENABLE (1 << 9) + +/* CAS: CAS Latency */ +#define FMC_SDCR_CAS_SHIFT 7 +#define FMC_SDCR_CAS_1CYC (1 << FMC_SDCR_CAS_SHIFT) +#define FMC_SDCR_CAS_2CYC (2 << FMC_SDCR_CAS_SHIFT) +#define FMC_SDCR_CAS_3CYC (3 << FMC_SDCR_CAS_SHIFT) + +/* NB: Number of Internal banks */ +#define FMC_SDCR_NB2 0 +#define FMC_SDCR_NB4 (1 << 6) + +/* MWID: Memory width */ +#define FMC_SDCR_MWID_SHIFT 4 +#define FMC_SDCR_MWID_8b (0 << FMC_SDCR_MWID_SHIFT) +#define FMC_SDCR_MWID_16b (1 << FMC_SDCR_MWID_SHIFT) +#define FMC_SDCR_MWID_32b (2 << FMC_SDCR_MWID_SHIFT) + +/* NR: Number of rows */ +#define FMC_SDCR_NR_SHIFT 2 +#define FMC_SDCR_NR_11 (0 << FMC_SDCR_NR_SHIFT) +#define FMC_SDCR_NR_12 (1 << FMC_SDCR_NR_SHIFT) +#define FMC_SDCR_NR_13 (2 << FMC_SDCR_NR_SHIFT) + +/* NC: Number of Columns */ +#define FMC_SDCR_NC_SHIFT 0 +#define FMC_SDCR_NC_8 (0 << FMC_SDCR_NC_SHIFT) +#define FMC_SDCR_NC_9 (1 << FMC_SDCR_NC_SHIFT) +#define FMC_SDCR_NC_10 (2 << FMC_SDCR_NC_SHIFT) +#define FMC_SDCR_NC_11 (3 << FMC_SDCR_NC_SHIFT) + +/* --- FMC_SDTRx values --------------------------------------------------- */ + +/* Bits [31:28]: Reserved. */ + +/* TRCD: Row to Column Delay */ +#define FMC_SDTR_TRCD_SHIFT 24 +#define FMC_SDTR_TRCD_MASK (15 << FMC_SDTR_TRCD_SHIFT) + +/* TRP: Row Precharge Delay */ +#define FMC_SDTR_TRP_SHIFT 20 +#define FMC_SDTR_TRP_MASK (15 << FMC_SDTR_TRP_SHIFT) + +/* TWR: Recovery Delay */ +#define FMC_SDTR_TWR_SHIFT 16 +#define FMC_SDTR_TWR_MASK (15 << FMC_SDTR_TWR_SHIFT) + +/* TRC: Row Cycle Delay */ +#define FMC_SDTR_TRC_SHIFT 12 +#define FMC_SDTR_TRC_MASK (15 << FMC_SDTR_TRC_SHIFT) + +/* TRAS: Self Refresh Time */ +#define FMC_SDTR_TRAS_SHIFT 8 +#define FMC_SDTR_TRAS_MASK (15 << FMC_SDTR_TRAS_SHIFT) + +/* TXSR: Exit Self-refresh Delay */ +#define FMC_SDTR_TXSR_SHIFT 4 +#define FMC_SDTR_TXSR_MASK (15 << FMC_SDTR_TXSR_SHIFT) + +/* TRMD: Load Mode Register to Active */ +#define FMC_SDTR_TMRD_SHIFT 0 +#define FMC_SDTR_TMRD_MASK (15 << FMC_SDTR_TMRD_SHIFT) + +/* + * Some config bits only count in CR1 or TR1, even if you + * are just configuring bank 2, so these masks let you copy + * out those bits after you have computed values for CR2 and + * TR2 and put them into CR1 and TR1 + */ +#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK) +#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \ + FMC_SDCR_RPIPE_MASK | \ + FMC_SDCR_RBURST) + +/* --- FMC_SDCMR values --------------------------------------------------- */ + +/* Bits [31:22]: Reserved. */ + +/* MRD: Mode Register Definition */ +#define FMC_SDCMR_MRD_SHIFT 9 +#define FMC_SDCMR_MRD_MASK (0x1fff << FMC_SDCMR_MRD_SHIFT) + +/* NRFS: Number of Auto-refresh */ +#define FMC_SDCMR_NRFS_SHIFT 5 +#define FMC_SDCMR_NRFS_MASK (15 << FMC_SDCMR_NRFS_SHIFT) + +/* CTB1: Command Target Bank 1 */ +#define FMC_SDCMR_CTB1 (1 << 4) + +/* CTB2: Command Target Bank 2 */ +#define FMC_SDCMR_CTB2 (1 << 3) + +/* MODE: Command Mode */ +#define FMC_SDCMR_MODE_SHIFT 0 +#define FMC_SDCMR_MODE_MASK 7 +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1 +#define FMC_SDCMR_MODE_PALL 2 +#define FMC_SDCMR_MODE_AUTO_REFRESH 3 +#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4 +#define FMC_SDCMR_MODE_SELF_REFRESH 5 +#define FMC_SDCMR_MODE_POWER_DOWN 6 + +/* --- FMC_SDRTR values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* REIE: Refresh Error Interrupt Enable */ +#define FMC_SDRTR_REIE (1 << 14) + +/* COUNT: Refresh Timer Count */ +#define FMC_SDRTR_COUNT_SHIFT 1 +#define FMC_SDRTR_COUNT_MASK (0x1fff << FMC_SDRTR_COUNT_SHIFT) + +/* CRE: Clear Refresh Error Flag */ +#define FMC_SDRTR_CRE (1 << 0) + +/* --- FMC_SDSR values ---------------------------------------------------- */ + +/* Bits [31:6]: Reserved. */ + +/* BUSY: Set if the SDRAM is working on the command */ +#define FMC_SDSR_BUSY (1 << 5) + +/* MODES: Status modes */ +#define FMC_SDSR_MODE_NORMAL 0 +#define FMC_SDSR_MODE_SELF_REFRESH 1 +#define FMC_SDSR_MODE_POWER_DOWN 2 + +/* Mode shift */ +#define FMC_SDSR_MODE2_SHIFT 3 +#define FMC_SDSR_MODE1_SHIFT 1 + +/* RE: Refresh Error */ +#define FMC_SDSR_RE (1 << 0) + +/* Helper function for setting the timing parameters */ +struct sdram_timing { + int trcd; /* RCD Delay */ + int trp; /* RP Delay */ + int twr; /* Write Recovery Time */ + int trc; /* Row Cycle Delay */ + int tras; /* Self Refresh TIme */ + int txsr; /* Exit Self Refresh Time */ + int tmrd; /* Load to Active delay */ +}; + +/* Mode register parameters */ +#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS }; +enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL, + SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE, + SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN }; + +/* Send an array of timing parameters (indices above) to create SDTR register + * value + */ +BEGIN_DECLS + +uint32_t sdram_timing(struct sdram_timing *t); +void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd, + int autorefresh, int modereg); + +END_DECLS + +#endif +/**@}*/ diff --git a/include/libopencm3/stm32/common/i2c_common_v2.h b/include/libopencm3/stm32/common/i2c_common_v2.h index cd311064..ad4846b9 100644 --- a/include/libopencm3/stm32/common/i2c_common_v2.h +++ b/include/libopencm3/stm32/common/i2c_common_v2.h @@ -46,6 +46,9 @@ specific memorymap.h header before including this header file.*/ #ifdef I2C3_BASE #define I2C3 I2C3_BASE #endif +#ifdef I2C4_BASE +#define I2C4 I2C4_BASE +#endif /**@}*/ /* --- I2C registers ------------------------------------------------------- */ diff --git a/include/libopencm3/stm32/common/lptimer_common_all.h b/include/libopencm3/stm32/common/lptimer_common_all.h new file mode 100644 index 00000000..37ea10f1 --- /dev/null +++ b/include/libopencm3/stm32/common/lptimer_common_all.h @@ -0,0 +1,296 @@ +/** @addtogroup lptimer_defines + * + * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net> + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net> + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/** @cond */ +#if defined(LIBOPENCM3_LPTIMER_H) +/** @endcond */ +#ifndef LIBOPENCM3_LPTIMER_COMMON_H +#define LIBOPENCM3_LPTIMER_COMMON_H + +/* --- LPTIM (low power timer) ------------------------------------------- */ + +#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) +#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) +#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) +#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) +#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) +#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) +#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) +#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) + +#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) +#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) +#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE) +#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) +#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE) +#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) +#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) +#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) + +#if defined(LPTIM2_BASE) +#define LPTIM2_ISR LPTIM_ISR(LPTIM2_BASE) +#define LPTIM2_ICR LPTIM_ICR(LPTIM2_BASE) +#define LPTIM2_IER LPTIM_IER(LPTIM2_BASE) +#define LPTIM2_CFGR LPTIM_CFGR(LPTIM2_BASE) +#define LPTIM2_CR LPTIM_CR(LPTIM2_BASE) +#define LPTIM2_CMP LPTIM_CMP(LPTIM2_BASE) +#define LPTIM2_ARR LPTIM_ARR(LPTIM2_BASE) +#define LPTIM2_CNT LPTIM_CNT(LPTIM2_BASE) +#endif + +/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register +@{*/ + +/** LPTIM_ISR_CMPM Compare match */ +#define LPTIM_ISR_CMPM (1 << 0) + +/** LPTIM_ISR_ARRM Autoreload match */ +#define LPTIM_ISR_ARRM (1 << 1) + +/** LPTIM_ISR_EXTTRIG External trigger edge event */ +#define LPTIM_ISR_EXTTRIG (1 << 2) + +/** LPTIM_ISR_CMPOK Compare register update OK */ +#define LPTIM_ISR_CMPOK (1 << 3) + +/** LPTIM_ISR_ARROK Autoreload register update OK */ +#define LPTIM_ISR_ARROK (1 << 4) + +/** LPTIM_ISR_UP Counter direction change down to up */ +#define LPTIM_ISR_UP (1 << 5) + +/** LPTIM_ISR_DOWN Counter direction change up to down */ +#define LPTIM_ISR_DOWN (1 << 6) + +/**@}*/ + +/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register +@{*/ + +/** LPTIM_ICR_CMPMCF compare match Clear Flag */ +#define LPTIM_ICR_CMPMCF (1 << 0) + +/** LPTIM_ICR_ARRMCF Autoreload match Clear Flag */ +#define LPTIM_ICR_ARRMCF (1 << 1) + +/** LPTIM_ICR_EXTTRIGCF External trigger valid edge Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF (1 << 2) + +/** LPTIM_ICR_CMPOKCF Compare register update OK Clear Flag */ +#define LPTIM_ICR_CMPOKCF (1 << 3) + +/** LPTIM_ICR_ARROKCF Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF (1 << 4) + +/** LPTIM_ICR_UPCF Direction change to UP Clear Flag */ +#define LPTIM_ICR_UPCF (1 << 5) + +/** LPTIM_ICR_DOWNCF Direction change to down Clear Flag */ +#define LPTIM_ICR_DOWNCF (1 << 6) + +/**@}*/ + +/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register +@{*/ + +/** LPTIM_IER_CMPMIE Compare match Interrupt Enable */ +#define LPTIM_IER_CMPMIE (1 << 0) + +/** LPTIM_IER_ARRMIE Autoreload match Interrupt Enable */ +#define LPTIM_IER_ARRMIE (1 << 1) + +/** LPTIM_IER_EXTTRIGIE External trigger valid edge Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE (1 << 2) + +/** LPTIM_IER_CMPOKIE Compare register update OK Interrupt Enable */ +#define LPTIM_IER_CMPOKIE (1 << 3) + +/** LPTIM_IER_ARROKIE Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE (1 << 4) + +/** LPTIM_IER_UPIE Direction change to UP Interrupt Enable */ +#define LPTIM_IER_UPIE (1 << 5) + +/** LPTIM_IER_DOWNIE Direction change to down Interrupt Enable */ +#define LPTIM_IER_DOWNIE (1 << 6) + +/**@}*/ + +/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register +@{*/ + +/** CKSEL: Select internal (0) or external clock source (1) */ +#define LPTIM_CFGR_CKSEL (1 << 0) + +#define LPTIM_CFGR_CKPOL_SHIFT 1 +#define LPTIM_CFGR_CKPOL_MASK 0x03 +#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) +/** @defgroup lptim_cfgr_ckpol LPTIM_CFGR CKPOL Clock Polarity +@{*/ +#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_CKFLT_SHIFT 3 +#define LPTIM_CFGR_CKFLT_MASK 0x03 +#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) +/** @defgroup lptim_cfgr_ckflt LPTIM_CFGR CKFLT Configurable digital filter for external clock +@{*/ +#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) +#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) +#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_TRGFLT_SHIFT 6 +#define LPTIM_CFGR_TRGFLT_MASK 0x03 +#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) +/** @defgroup lptim_cfgr_trgflt LPTIM_CFGR TRGFLT Configurable digital filter for trigger +@{*/ +#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) +#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) +#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_PRESC_SHIFT 9 +#define LPTIM_CFGR_PRESC_MASK 0x07 +#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) +/** @defgroup lptim_cfgr_presc LPTIM_CFGR PRESC Clock prescaler +@{*/ +#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_TRIGSEL_SHIFT 13 +#define LPTIM_CFGR_TRIGSEL_MASK 0x07 +#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) +/** @defgroup lptim_cfgr_trigsel LPTIM_CFGR TRIGSEL Trigger selector +@{*/ +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) +/* 5 is reserved */ +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_TRIGEN_SHIFT 17 +#define LPTIM_CFGR_TRIGEN_MASK 0x07 +#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) +/** @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity +@{*/ +#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) +/**@}*/ + +/** TIMOUT: Timeout enable */ +#define LPTIM_CFGR_TIMOUT (1 << 19) + +/** WAVE: Waveform shape */ +#define LPTIM_CFGR_WAVE (1 << 20) + +/** WAVPOL: Waveform shape polarity */ +#define LPTIM_CFGR_WAVPOL (1 << 21) + +/** PRELOAD: Register update mode */ +#define LPTIM_CFGR_PRELOAD (1 << 22) + +/** COUNTMODE: Counter mode enable */ +#define LPTIM_CFGR_COUNTMODE (1 << 23) + +/** ENC: Encoder mode enable */ +#define LPTIM_CFGR_ENC (1 << 24) + +/**@}*/ + +/** @defgroup lptim_cr LPTIM_CR Control Register +@{*/ + +/** ENABLE: LPTIM Enable */ +#define LPTIM_CR_ENABLE (1 << 0) + +/** SNGSTRT: Start in Single Mode */ +#define LPTIM_CR_SNGSTRT (1 << 1) + +/** CNGSTRT: Start in Continuous Mode */ +#define LPTIM_CR_CNTSTRT (1 << 2) + +/**@}*/ + +/* --- LPTIM function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void lptimer_enable(uint32_t timer_peripheral); +void lptimer_disable(uint32_t timer_peripheral); + +void lptimer_start_counter(uint32_t timer_peripheral, uint32_t mode); +void lptimer_set_counter(uint32_t timer_peripheral, uint16_t count); +uint16_t lptimer_get_counter(uint32_t timer_peripheral); +void lptimer_set_compare(uint32_t timer_peripheral, uint16_t compare_value); +void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value); +void lptimer_enable_preload(uint32_t lptimer_peripheral); +void lptimer_disable_preload(uint32_t lptimer_peripheral); +void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral); +void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral); + +void lptimer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); +void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen); +void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source); +void lptimer_set_internal_clock_source(uint32_t timer_peripheral); +void lptimer_set_external_clock_source(uint32_t timer_peripheral); + +void lptimer_clear_flag(uint32_t timer_peripheral, uint32_t flag); +bool lptimer_get_flag(uint32_t timer_peripheral, uint32_t flag); +void lptimer_enable_irq(uint32_t timer_peripheral, uint32_t irq); +void lptimer_disable_irq(uint32_t timer_peripheral, uint32_t irq); + + +END_DECLS + +#endif +/** @cond */ +#else +#warning "lptimer_common_all.h should not be included directly, only via lptimer.h" +#endif +/** @endcond */ + +/**@}*/ diff --git a/include/libopencm3/stm32/common/ltdc_common_f47.h b/include/libopencm3/stm32/common/ltdc_common_f47.h new file mode 100644 index 00000000..d938d6cc --- /dev/null +++ b/include/libopencm3/stm32/common/ltdc_common_f47.h @@ -0,0 +1,535 @@ +/** @addtogroup ltdc_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2014 + * Oliver Meier <h2obrain@gmail.com> + * + * @date 5 December 2014 + * + * This library supports the LCD TFT display controller (LTDC) in the STM32F4xx + * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Oliver Meier <h2obrain@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ +/** @cond */ +#ifndef LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ +/** @endcond */ +#define LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ + + +#include <stdint.h> +#include <libopencm3/stm32/rcc.h> + +/** + * LTDC + */ + + +#define LTDC_SSCR (MMIO32(LTDC_BASE + 0x08)) +#define LTDC_BPCR (MMIO32(LTDC_BASE + 0x0C)) +#define LTDC_AWCR (MMIO32(LTDC_BASE + 0x10)) +#define LTDC_TWCR (MMIO32(LTDC_BASE + 0x14)) +#define LTDC_GCR (MMIO32(LTDC_BASE + 0x18)) +#define LTDC_SRCR (MMIO32(LTDC_BASE + 0x24)) +#define LTDC_BCCR (MMIO32(LTDC_BASE + 0x2C)) +#define LTDC_IER (MMIO32(LTDC_BASE + 0x34)) +#define LTDC_ISR (MMIO32(LTDC_BASE + 0x38)) +#define LTDC_ICR (MMIO32(LTDC_BASE + 0x3C)) +#define LTDC_LIPCR (MMIO32(LTDC_BASE + 0x40)) +#define LTDC_CPSR (MMIO32(LTDC_BASE + 0x44)) +#define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) + +/* x == LTDC_LAYER_x */ +#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) +#define LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) +#define LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) + +#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) +#define LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) +#define LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) + +#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) +#define LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) +#define LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) + +#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) +#define LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) +#define LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) + +#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) +#define LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) +#define LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) + +#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) +#define LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) +#define LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) + +#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) +#define LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) +#define LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) + +#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) +#define LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) +#define LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) + +#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) +#define LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) +#define LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) + +#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) +#define LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) +#define LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) + +#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) +#define LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) +#define LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) + +#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) +#define LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) +#define LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) + + +#define LTDC_LAYER_1 1 +#define LTDC_LAYER_2 2 + +/* --- LTDC_SSCR values ---------------------------------------------------- */ + +/* Horizontal Synchronization Width */ +#define LTDC_SSCR_HSW_SHIFT 16 +#define LTDC_SSCR_HSW_MASK 0xfff + +/* Vertical Synchronization Height */ +#define LTDC_SSCR_VSH_SHIFT 0 +#define LTDC_SSCR_VSH_MASK 0x7ff + +/* --- LTDC_BPCR values ---------------------------------------------------- */ + +/* Accumulated Horizontal Back Porch */ +#define LTDC_BPCR_AHBP_SHIFT 16 +#define LTDC_BPCR_AHBP_MASK 0xfff + +/* Accumulated Vertical Back Porch */ +#define LTDC_BPCR_AVBP_SHIFT 0 +#define LTDC_BPCR_AVBP_MASK 0x7FF + +/* --- LTDC_AWCR values ---------------------------------------------------- */ + +/* Accumulated Active Width */ +#define LTDC_AWCR_AAW_SHIFT 16 +#define LTDC_AWCR_AAW_MASK 0xfff + +/* Accumulated Active Height */ +#define LTDC_AWCR_AAH_SHIFT 0 +#define LTDC_AWCR_AAH_MASK 0x7ff + +/* --- LTDC_TWCR values ---------------------------------------------------- */ + +/* Total Width */ +#define LTDC_TWCR_TOTALW_SHIFT 16 +#define LTDC_TWCR_TOTALW_MASK 0xfff + +/* Total Height */ +#define LTDC_TWCR_TOTALH_SHIFT 0 +#define LTDC_TWCR_TOTALH_MASK 0x7ff + +/* GCR - control register */ +#define LTDC_GCR_LTDC_ENABLE (1<<0) +#define LTDC_GCR_DITHER_ENABLE (1<<16) + +#define LTDC_GCR_PCPOL_ACTIVE_LOW (0<<28) +#define LTDC_GCR_PCPOL_ACTIVE_HIGH (1<<28) + +#define LTDC_GCR_DEPOL_ACTIVE_LOW (0<<29) +#define LTDC_GCR_DEPOL_ACTIVE_HIGH (1<<29) + +#define LTDC_GCR_VSPOL_ACTIVE_LOW (0<<30) +#define LTDC_GCR_VSPOL_ACTIVE_HIGH (1<<30) + +#define LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31) +#define LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31) + +/* GCR - register bit defines (no semantics) */ +#define LTDC_GCR_HSPOL (1 << 31) +#define LTDC_GCR_VSPOL (1 << 30) +#define LTDC_GCR_DEPOL (1 << 29) +#define LTDC_GCR_PCPOL (1 << 28) +#define LTDC_GCR_DITHER (1 << 16) +#define LTDC_GCR_LTDCEN (1 << 0) + +/* --- LTDC_SRCR values ---------------------------------------------------- */ + +/* Vertical Blanking Reload */ +#define LTDC_SRCR_VBR (1 << 1) + +/* Immediate Reload */ +#define LTDC_SRCR_IMR (1 << 0) + +/* LTDC_BCCR - reload control */ +#define LTDC_SRCR_RELOAD_IMR (1<<0) +#define LTDC_SRCR_RELOAD_VBR (1<<1) + +/* --- LTDC_IER values ----------------------------------------------------- */ + +/* Register Reload Interrupt Enable */ +#define LTDC_IER_RRIE (1 << 3) + +/* Transfer Error Interrupt Enable */ +#define LTDC_IER_TERRIE (1 << 2) + +/* FIFO Underrun Interrupt Enable */ +#define LTDC_IER_FUIE (1 << 1) + +/* Line Interrupt Enable */ +#define LTDC_IER_LIE (1 << 0) + +/* --- LTDC_ISR values ----------------------------------------------------- */ + +/* Register Reload Interrupt Flag */ +#define LTDC_ISR_RRIF (1 << 3) + +/* Transfer Error Interrupt Flag */ +#define LTDC_ISR_TERRIF (1 << 2) + +/* FIFO Underrun Interrupt Flag */ +#define LTDC_ISR_FUIF (1 << 1) + +/* Line Interrupt Flag */ +#define LTDC_ISR_LIF (1 << 0) + +/* --- LTDC_ICR values ----------------------------------------------------- */ + +/* Clears Register Reload Interrupt Flag */ +#define LTDC_ICR_CRRIF (1 << 3) + +/* Clears Transfer Error Interrupt Flag */ +#define LTDC_ICR_CTERRIF (1 << 2) + +/* Clears FIFO Underrun Interrupt Flag */ +#define LTDC_ICR_CFUIF (1 << 1) + +/* Clears Line Interrupt Flag */ +#define LTDC_ICR_CLIF (1 << 0) + +/* --- LTDC_LIPCR values --------------------------------------------------- */ + +/* Line Interrupt Position */ +#define LTDC_LIPCR_LIPOS_SHIFT 0 +#define LTDC_LIPCR_LIPOS_MASK 0x7ff + +/* --- LTDC_CPSR values ---------------------------------------------------- */ + +/* Current X Position */ +#define LTDC_CPSR_CXPOS_SHIFT 16 +#define LTDC_CPSR_CXPOS_MASK 0xffff + +/* Current Y Position */ +#define LTDC_CPSR_CYPOS_SHIFT 0 +#define LTDC_CPSR_CYPOS_MASK 0xffff + +/* LTDC_CDSR - display status register */ +#define LTDC_CDSR_VDES (1<<0) +#define LTDC_CDSR_HDES (1<<1) +#define LTDC_CDSR_VSYNCS (1<<2) +#define LTDC_CDSR_HSYNCS (1<<3) + +/* LTDC_LxCR - layer control */ +#define LTDC_LxCR_LAYER_ENABLE (1<<0) +#define LTDC_LxCR_COLKEY_ENABLE (1<<1) +#define LTDC_LxCR_COLTAB_ENABLE (1<<4) + +/* --- LTDC_LxWHPCR values ------------------------------------------------- */ + +/* Window Horizontal Stop Position */ +#define LTDC_LxWHPCR_WHSPPOS_SHIFT 16 +#define LTDC_LxWHPCR_WHSPPOS_MASK 0xfff + +/* Window Horizontal Start Position */ +#define LTDC_LxWHPCR_WHSTPOS_SHIFT 0 +#define LTDC_LxWHPCR_WHSTPOS_MASK 0xfff + +/* --- LTDC_LxWVPCR values ------------------------------------------------- */ + +/* Window Vertical Stop Position */ +#define LTDC_LxWVPCR_WVSPPOS_SHIFT 16 +#define LTDC_LxWVPCR_WVSPPOS_MASK 0x7ff + +/* Window Vertical Start Position */ +#define LTDC_LxWVPCR_WVSTPOS_SHIFT 0 +#define LTDC_LxWVPCR_WVSTPOS_MASK 0x7ff + +/* --- LTDC_LxCKCR values -------------------------------------------------- */ + +/* Color Key Red */ +#define LTDC_LxCKCR_CKRED_SHIFT 16 +#define LTDC_LxCKCR_CKRED_MASK 0xff + +/* Color Key Green */ +#define LTDC_LxCKCR_CKGREEN_SHIFT 16 +#define LTDC_LxCKCR_CKGREEN_MASK 0xff + +/* Color Key Blue */ +#define LTDC_LxCKCR_CKBLUE_SHIFT 16 +#define LTDC_LxCKCR_CKBLUE_MASK 0xff + +/* LTDC_LxPFCR - Pixel formats */ +#define LTDC_LxPFCR_ARGB8888 (0b000) +#define LTDC_LxPFCR_RGB888 (0b001) +#define LTDC_LxPFCR_RGB565 (0b010) +#define LTDC_LxPFCR_ARGB1555 (0b011) +#define LTDC_LxPFCR_ARGB4444 (0b100) +#define LTDC_LxPFCR_L8 (0b101) +#define LTDC_LxPFCR_AL44 (0b110) +#define LTDC_LxPFCR_AL88 (0b111) + +/* --- LTDC_LxCACR values -------------------------------------------------- */ + +/* Constant Alpha */ +#define LTDC_LxCACR_CONSTA_SHIFT 0 +#define LTDC_LxCACR_CONSTA_MASK 0xff + +/* --- LTDC_LxDCCR values -------------------------------------------------- */ + +/* Default Color Alpha */ +#define LTDC_LxDCCR_DCALPHA_SHIFT 24 +#define LTDC_LxDCCR_DCALPHA_MASK 1 + +/* Default Color Red */ +#define LTDC_LxDCCR_DCRED_SHIFT 16 +#define LTDC_LxDCCR_DCRED_MASK 1 + +/* Default Color Green */ +#define LTDC_LxDCCR_DCGREEN_SHIFT 8 +#define LTDC_LxDCCR_DCGREEN_MASK 1 + +/* Default Color Blue */ +#define LTDC_LxDCCR_DCBLUE_SHIFT 0 +#define LTDC_LxDCCR_DCBLUE_MASK 1 + +/* LTDC_LxBFCR - Blending factors - BF1 */ +#define LTDC_LxBFCR_BF1_CONST_ALPHA (0b100) +#define LTDC_LxBFCR_BF1_PIXEL_ALPHA_x_CONST_ALPHA (0b110) +/* LTDC_LxBFCR - Blending factors - BF2 */ +#define LTDC_LxBFCR_BF2_CONST_ALPHA (0b101) +#define LTDC_LxBFCR_BF2_PIXEL_ALPHA_x_CONST_ALPHA (0b111) + +/* --- LTDC_LxCFBAR values ------------------------------------------------- */ + +/* Color Frame Buffer Start Address */ +#define LTDC_LxCFBAR_CFBAR_SHIFT 0 +#define LTDC_LxCFBAR_CFBAR_MASK 0xffffffff + +/* --- LTDC_LxCFBLR values ------------------------------------------------- */ + +/* Color Frame Buffer Pitch */ +#define LTDC_LxCFBLR_CFBP_SHIFT 16 +#define LTDC_LxCFBLR_CFBP_MASK 0x1fff + +/* Color Frame Buffer Line Length */ +#define LTDC_LxCFBLR_CFBLL_SHIFT 0 +#define LTDC_LxCFBLR_CFBLL_MASK 0x1fff + +/* --- LTDC_LxCFBLNR values ------------------------------------------------ */ + +/* Frame Buffer Line Number */ +#define LTDC_LxCFBLNR_CFBLNBR_SHIFT 0 +#define LTDC_LxCFBLNR_CFBLNBR_MASK 0x3ff + +/* --- LTDC_LxCLUTWR values ------------------------------------------------ */ + +/* CLUT Address */ +#define LTDC_LxCLUTWR_CLUTADD_SHIFT 24 +#define LTDC_LxCLUTWR_CLUTADD_MASK 0xff + +/* Red */ +#define LTDC_LxCLUTWR_RED_SHIFT 16 +#define LTDC_LxCLUTWR_RED_MASK 0xff + +/* Green */ +#define LTDC_LxCLUTWR_GREEN_SHIFT 8 +#define LTDC_LxCLUTWR_GREEN_MASK 0xff + +/* Blue */ +#define LTDC_LxCLUTWR_BLUE_SHIFT 0 +#define LTDC_LxCLUTWR_BLUE_MASK 0xff + +/** + * simple helper macros + */ + +/* global */ +static inline void ltdc_ctrl_enable(uint32_t ctrl_flags) +{ + LTDC_GCR |= ctrl_flags; +} + +static inline void ltdc_ctrl_disable(uint32_t ctrl_flags) +{ + LTDC_GCR &= ~(ctrl_flags); +} + +static inline void ltdc_reload(uint32_t reload_flags) +{ + LTDC_SRCR = reload_flags; +} + +static inline void ltdc_set_background_color(uint8_t r, uint8_t g, uint8_t b) +{ + LTDC_BCCR = (((r)&255)<<16) | + (((g)&255)<<8) | + (((b)&255)<<0); +} + +static inline void ltdc_get_current_position(uint16_t *x, uint16_t *y) +{ + uint32_t tmp = LTDC_CPSR; + *x = tmp >> 16; + *y = tmp &= 0xFFFF; +} + +static inline uint16_t ltdc_get_current_position_x(void) +{ + return LTDC_CPSR >> 16; +} + +static inline uint16_t ltdc_get_current_position_y(void) +{ + return LTDC_CPSR & 0xffff; +} + +static inline uint32_t ltdc_get_display_status(uint32_t status_flags) +{ + return LTDC_CDSR & status_flags; +} + +/* layers */ +static inline void ltdc_layer_ctrl_enable(uint32_t layer, uint32_t ctrl_flags) +{ + LTDC_LxCR(layer) |= ctrl_flags; +} + +static inline void ltdc_layer_ctrl_disable(uint32_t layer, uint32_t ctrl_flags) +{ + LTDC_LxCR(layer) &= ~(ctrl_flags); +} + +static inline void ltdc_set_color_key(uint32_t layer, + uint8_t r, uint8_t g, uint8_t b) +{ + LTDC_LxCKCR(layer) = ((((r)&255)<<16) | + (((g)&255)<<8) | + (((b)&255)<<0)); +} + +static inline void ltdc_set_pixel_format(uint32_t layer, uint32_t format) +{ + LTDC_LxPFCR(layer) = format; +} + +static inline void ltdc_set_constant_alpha(uint32_t layer, uint8_t alpha) +{ + LTDC_LxCACR(layer) = ((alpha)&255); +} + +static inline void ltdc_set_default_colors(uint32_t layer, + uint8_t a, + uint8_t r, uint8_t g, uint8_t b) +{ + LTDC_LxDCCR(layer) = ((((a)&255)<<24) | + (((r)&255)<<16) | + (((g)&255)<<8) | + (((b)&255)<<0)); +} + +static inline void ltdc_set_blending_factors(uint32_t layer, + uint8_t bf1, uint8_t bf2) +{ + LTDC_LxBFCR(layer) = ((bf1)<<8) | ((bf2)<<0); +} + +static inline void ltdc_set_fbuffer_address(uint32_t layer, uint32_t address) +{ + LTDC_LxCFBAR(layer) = (uint32_t)address; +} + +static inline uint32_t ltdc_get_fbuffer_address(uint32_t layer) +{ + return LTDC_LxCFBAR(layer); +} + +static inline void ltdc_set_fb_line_length(uint32_t layer, + uint16_t len, uint16_t pitch) +{ + LTDC_LxCFBLR(layer) = ((((pitch)&0x1FFF)<<16) | (((len)&0x1FFF)<<0)); +} + +static inline void ltdc_set_fb_line_count(uint32_t layer, uint16_t linecount) +{ + LTDC_LxCFBLNR(layer) = (((linecount)&0x3FF)<<0); +} + +/** + * more complicated helper functions + */ +void ltdc_set_tft_sync_timings( + uint16_t sync_width, uint16_t sync_height, + uint16_t h_back_porch, uint16_t v_back_porch, + uint16_t active_width, uint16_t active_height, + uint16_t h_front_porch, uint16_t v_front_porch +); +void ltdc_setup_windowing( + uint8_t layer_number, + uint16_t h_back_porch, uint16_t v_back_porch, + uint16_t active_width, uint16_t active_height +); + + + +/** + * Helper function to wait for SRCR reload to complete or so + */ + +static inline bool LTDC_SRCR_IS_RELOADING(void) +{ + return (LTDC_SRCR & (LTDC_SRCR_RELOAD_VBR | + LTDC_SRCR_RELOAD_IMR)) != 0; +} + +/** + * color conversion helper function + * (simulate the ltdc color conversion) + */ + +static inline uint32_t ltdc_get_rgb888_from_rgb565(uint16_t rgb565) +{ + uint32_t rgb565_32 = (uint32_t)rgb565; + return ((((rgb565_32) & 0xF800) >> (11-8))/31)<<16 + | ((((rgb565_32) & 0x07E0) << (8-5))/63)<<8 + | ((((rgb565_32) & 0x001F) << (8-0))/31)<<0; +} + +/** @cond */ +#endif /* LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ */ +/** @endcond */ +/**@}*/ + diff --git a/include/libopencm3/stm32/common/rtc_common_l1f024.h b/include/libopencm3/stm32/common/rtc_common_l1f024.h index 9d577f36..0de52e8c 100644 --- a/include/libopencm3/stm32/common/rtc_common_l1f024.h +++ b/include/libopencm3/stm32/common/rtc_common_l1f024.h @@ -152,9 +152,9 @@ specific memorymap.h header before including this header file.*/ /** Weekday units mask */ #define RTC_DR_WDU_MASK (0x7) /** Month tens in BCD format shift */ -#define RTC_DR_MT (1<<12) -/** Month tens in BCD format mask */ #define RTC_DR_MT_SHIFT (12) +/** Month tens in BCD format mask */ +#define RTC_DR_MT_MASK (1<<12) /** Month units in BCD format shift */ #define RTC_DR_MU_SHIFT (8) /** Month units in BCD format mask */ diff --git a/include/libopencm3/stm32/common/spi_common_v2.h b/include/libopencm3/stm32/common/spi_common_v2.h index 2f2e204b..dd81b6cb 100644 --- a/include/libopencm3/stm32/common/spi_common_v2.h +++ b/include/libopencm3/stm32/common/spi_common_v2.h @@ -59,6 +59,12 @@ specific memorymap.h header before including this header file.*/ /* FRXTH: FIFO reception threshold */ #define SPI_CR2_FRXTH (1 << 12) +/* FRF: Frame format */ +/* Note: Not used in I2S mode. */ +#define SPI_CR2_FRF (1 << 4) +#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) +#define SPI_CR2_FRF_TI_MODE (1 << 4) + /* DS: Data size */ /****************************************************************************/ /** @defgroup spi_ds SPI data size @@ -98,6 +104,9 @@ specific memorymap.h header before including this header file.*/ #define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) #define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) +/* FRE : TI frame format error */ +#define SPI_SR_FRE (1 << 8) + /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS diff --git a/include/libopencm3/stm32/common/syscfg_common_l1f234.h b/include/libopencm3/stm32/common/syscfg_common_l1f234.h index 776e12da..5e7f2d42 100644 --- a/include/libopencm3/stm32/common/syscfg_common_l1f234.h +++ b/include/libopencm3/stm32/common/syscfg_common_l1f234.h @@ -50,6 +50,10 @@ specific memorymap.h header before including this header file.*/ #define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) +/* --- SYSCFG_EXTICR Values -------------------------------------------------*/ + +#define SYSCFG_EXTICR_FIELDSIZE 4 + #endif /**@}*/ diff --git a/include/libopencm3/stm32/common/timer_common_all.h b/include/libopencm3/stm32/common/timer_common_all.h index f3f21158..4dbfcc4f 100644 --- a/include/libopencm3/stm32/common/timer_common_all.h +++ b/include/libopencm3/stm32/common/timer_common_all.h @@ -39,8 +39,6 @@ specific memorymap.h header before including this header file.*/ /* Timer register base addresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses -@ingroup timer_defines - @{*/ #define TIM1 TIM1_BASE #define TIM2 TIM2_BASE @@ -81,6 +79,12 @@ specific memorymap.h header before including this header file.*/ #if defined(TIM17_BASE) # define TIM17 TIM17_BASE #endif +#if defined(TIM21_BASE) +# define TIM21 TIM21_BASE +#endif +#if defined(TIM22_BASE) +# define TIM22 TIM22_BASE +#endif /**@}*/ /* --- Timer registers ----------------------------------------------------- */ @@ -388,8 +392,6 @@ specific memorymap.h header before including this header file.*/ /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@ingroup timer_defines - @{*/ /* CKD[1:0]: Clock division */ #define TIM_CR1_CKD_CK_INT (0x0 << 8) @@ -404,8 +406,6 @@ specific memorymap.h header before including this header file.*/ /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@ingroup timer_defines - @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) #define TIM_CR1_CMS_CENTER_1 (0x1 << 5) @@ -417,8 +417,6 @@ specific memorymap.h header before including this header file.*/ /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@ingroup timer_defines - @{*/ #define TIM_CR1_DIR_UP (0 << 4) #define TIM_CR1_DIR_DOWN (1 << 4) @@ -440,8 +438,6 @@ specific memorymap.h header before including this header file.*/ /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@ingroup timer_defines - @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ #define TIM_CR2_OIS4 (1 << 14) @@ -472,8 +468,6 @@ specific memorymap.h header before including this header file.*/ /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@ingroup timer_defines - @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) #define TIM_CR2_MMS_ENABLE (0x1 << 4) @@ -533,9 +527,7 @@ specific memorymap.h header before including this header file.*/ #define TIM_SMCR_MSM (1 << 7) /* TS[2:0]: Trigger selection */ -/** @defgroup tim_ts TS Trigger selection -@ingroup timer_defines - +/** @defgroup tim_ts TIMx_SMCR TS Trigger selection @{*/ /** Internal Trigger 0 (ITR0) */ #define TIM_SMCR_TS_ITR0 (0x0 << 4) @@ -557,9 +549,7 @@ specific memorymap.h header before including this header file.*/ /**@}*/ /* SMS[2:0]: Slave mode selection */ -/** @defgroup tim_sms SMS Slave mode selection -@ingroup timer_defines - +/** @defgroup tim_sms TIMx_SMCR SMS Slave mode selection @{*/ /** Slave mode disabled */ #define TIM_SMCR_SMS_OFF (0x0 << 0) @@ -593,8 +583,6 @@ depending on the level of the complementary input. */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@ingroup timer_defines - @{*/ /* TDE:*//** Trigger DMA request enable */ #define TIM_DIER_TDE (1 << 14) @@ -645,8 +633,6 @@ depending on the level of the complementary input. */ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@ingroup timer_defines - @{*/ /* CC4OF:*//** Capture/compare 4 overcapture flag */ @@ -690,8 +676,6 @@ depending on the level of the complementary input. */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@ingroup timer_defines - @{*/ /* BG:*//** Break generation */ @@ -1053,8 +1037,6 @@ depending on the level of the complementary input. */ /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@ingroup timer_defines - @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) #define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) diff --git a/include/libopencm3/stm32/common/usart_common_f124.h b/include/libopencm3/stm32/common/usart_common_f124.h index 41ce2999..cd5c7122 100644 --- a/include/libopencm3/stm32/common/usart_common_f124.h +++ b/include/libopencm3/stm32/common/usart_common_f124.h @@ -39,7 +39,6 @@ specific memorymap.h header before including this header file.*/ /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ diff --git a/include/libopencm3/stm32/common/usart_common_f24.h b/include/libopencm3/stm32/common/usart_common_f24.h index e8d9f7f0..9edb640b 100644 --- a/include/libopencm3/stm32/common/usart_common_f24.h +++ b/include/libopencm3/stm32/common/usart_common_f24.h @@ -38,9 +38,14 @@ specific memorymap.h header before including this header file.*/ /* --- Convenience macros -------------------------------------------------- */ +/** @addtogroup usart_reg_base USART register base addresses + * Holds all the U(S)ART peripherals supported. + * @{ + */ #define USART6 USART6_BASE #define UART7 UART7_BASE #define UART8 UART8_BASE +/**@}*/ /* --- USART registers ----------------------------------------------------- */ |