diff options
| author | D. Lisin <mrlisdim@gmail.com> | 2019-09-21 21:12:07 +0300 |
|---|---|---|
| committer | D. Lisin <mrlisdim@gmail.com> | 2019-09-21 21:12:21 +0300 |
| commit | decb98c6d434260a38f3f671554cd7234fc08849 (patch) | |
| tree | 59c69ef4718c65866349d38f5c5fdc31f88eb5f5 | |
| parent | 293cfebe971eaaee54d38b7e42def1194103d130 (diff) | |
| parent | b0c3de8d8516557f1f4ac85c5deb4fb45fb8a10b (diff) | |
Merge remote-tracking branch 'upstream/master'
# Conflicts:
# lib/stm32/f2/Makefile
# lib/stm32/f4/Makefile
520 files changed, 14815 insertions, 10667 deletions
@@ -25,8 +25,12 @@ include/libopencm3/**/nvic.h include/libopencm3/**/**/nvic.h lib/**/vector_nvic.c lib/**/**/vector_nvic.c -doxy.sourcelist +DoxygenLayout.xml +doc/*/Doxyfile +doc/*/DoxygenLayout_*.xml +doc/*/doxy.sourcelist include/libopencmsis/efm32/ +include/libopencmsis/gd32/ include/libopencmsis/lm3s/ include/libopencmsis/lpc13xx/ include/libopencmsis/lpc17xx/ @@ -34,6 +38,7 @@ include/libopencmsis/lpc43xx/ include/libopencmsis/msp432/ include/libopencmsis/sam/ include/libopencmsis/stm32/ +include/libopencmsis/swm050/ include/libopencmsis/vf6xx/ # Editor/IDE config files @@ -41,6 +46,8 @@ nbproject/ .idea/ .project locm3.sublime-workspace +.cproject +.settings # cscope databases cscope.out @@ -6,7 +6,7 @@ Coding style ------------ The whole library is programmed using the Linux kernel coding style, see -http://lxr.linux.no/linux/Documentation/CodingStyle for details. +https://www.kernel.org/doc/html/latest/process/coding-style.html for details. Please use the same style for any code contributions, thanks! @@ -17,8 +17,7 @@ ## along with this library. If not, see <http://www.gnu.org/licenses/>. ## -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf +PREFIX ?= arm-none-eabi- STYLECHECK := scripts/checkpatch.pl STYLECHECKFLAGS := --no-tree -f --terse --mailback @@ -29,13 +28,16 @@ SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib)) TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ stm32/l0 stm32/l1 stm32/l4 \ + stm32/g0 \ + gd32/f1x0 \ lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 \ lm3s lm4f msp432/e4 \ efm32/tg efm32/g efm32/lg efm32/gg efm32/hg efm32/wg \ efm32/ezr32wg \ sam/3a sam/3n sam/3s sam/3u sam/3x sam/4l \ sam/d \ - vf6xx + vf6xx \ + swm050 # Be silent per default, but 'make V=1' will show all compiler calls. ifneq ($(V),1) @@ -56,17 +58,17 @@ build: lib %.genhdr: @printf " GENHDR $*\n"; - @./scripts/irq2nvic_h ./$*; + $(Q)./scripts/irq2nvic_h ./$*; %.cleanhdr: @printf " CLNHDR $*\n"; - @./scripts/irq2nvic_h --remove ./$* + $(Q)./scripts/irq2nvic_h --remove ./$* LIB_DIRS:=$(wildcard $(addprefix lib/,$(TARGETS))) $(LIB_DIRS): $(IRQ_DEFN_FILES:=.genhdr) $(Q)$(RM) .stamp_failure_$(subst /,_,$@) @printf " BUILD $@\n"; - $(Q)$(MAKE) --directory=$@ SRCLIBDIR="$(SRCLIBDIR)" || \ + $(Q)$(MAKE) --directory=$@ SRCLIBDIR="$(SRCLIBDIR)" PREFIX="$(PREFIX)" || \ echo "Failure building: $@: code: $$?" > .stamp_failure_$(subst /,_,$@) lib: $(LIB_DIRS) @@ -77,7 +79,7 @@ lib: $(LIB_DIRS) $(Q)[ -f .stamp_failure_tld ] && cat .stamp_failure_tld && exit 1 || true; html doc: - $(Q)$(MAKE) -C doc html + $(Q)$(MAKE) -C doc html TARGETS="$(TARGETS)" clean: $(IRQ_DEFN_FILES:=.cleanhdr) $(LIB_DIRS:=.clean) $(EXAMPLE_DIRS:=.clean) doc.clean styleclean genlinktests.clean @@ -145,7 +145,7 @@ Installation ------------ Simply pass -I and -L flags to your own project. See the -[libopencm3-template](https://github.com/libopencm3/libopencm3-miniblink) +[libopencm3-template](https://github.com/libopencm3/libopencm3-template) repository for a template repository using this library as a Git submodule, the most popular method of use. The libopencm3-examples is another example of this. diff --git a/doc/Makefile b/doc/Makefile index 731bf2b6..b35e2f2c 100644 --- a/doc/Makefile +++ b/doc/Makefile @@ -3,52 +3,59 @@ # 14 September 2012 # (C) Ken Sarkies <ksarkies@internode.on.net> -ARCHS := stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 -ARCHS += stm32l0 stm32l1 stm32l4 -ARCHS += efm32g efm32gg efm32hg efm32lg efm32tg -ARCHS += lm3s lm4f msp432e4 -ARCHS += lpc13xx lpc17xx lpc43xx -ARCHS += sam3a sam3n sam3s sam3u sam3x -ARCHS += vf6xx +# setup TARGETS if not set for legacy and ease of debug. +TARGETS ?= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \ + stm32/l0 stm32/l1 stm32/l4 \ + stm32/g0 \ + gd32/f1x0 \ + efm32/g efm32/gg efm32/hg efm32/lg efm32/tg \ + efm32/wg efm32/ezr32wg \ + lm3s lm4f \ + msp432/e4 \ + lpc13xx lpc17xx lpc43xx \ + sam/3a sam/3n sam/3s sam/3u sam/3x \ + vf6xx \ + swm050 + +TARGETS_DIRS = $(subst /,,$(TARGETS)) doc: html -html: rebuildsources $(ARCHS) + +DoxygenLayout.xml: templates/DoxygenLayout_Root.xml + ../scripts/gendoxylayout.py --template $< --out $@ $(TARGETS_DIRS) + +define gen_DOC_TARGET +DOC_TARGETS += doc_$(1) +CLEAN_TARGETS += clean_$(1) + +$(1)/: + @mkdir -p $$@ + +$(1)/doxy.sourcelist: $(1)/ + @../scripts/gendoxylist ../lib/$(TARGET_SRC_DIR) $(1) + +$(1)/Doxyfile: templates/Doxyfile_Device | $(1)/ + @cat $$< | sed s/#device#/$(1)/g > $$@ + +$(1)/DoxygenLayout_$(1).xml: templates/DoxygenLayout_Device.xml | $(1)/ + @../scripts/gendoxylayout.py --template $$< --out $$@ --target $(1) $$(TARGETS_DIRS) + +doc_$(1): $(1)/doxy.sourcelist $(1)/Doxyfile $(1)/DoxygenLayout_$(1).xml + @(cd $(1); doxygen) + +clean_$(1): + @$(RM) -rf $(1)/doxy.sourcelist $(1)/Doxyfile $(1)/DoxygenLayout_$1.xml $(1)/doxygen_$(1).log $(1)/html $(1)/$(1).tag + +endef + +$(foreach TARGET_SRC_DIR, $(TARGETS), $(eval $(call gen_DOC_TARGET,$(subst /,,$(TARGET_SRC_DIR))))) + +html: $(DOC_TARGETS) DoxygenLayout.xml doxygen -$(ARCHS): - cd $@/; doxygen - -clean: - @rm -rf html/ */html/ */*.tag */doxy.sourcelist */doxygen_*.log - -rebuildsources: - @printf "Manually regenerating source lists from build deps\n" - ../scripts/gendoxylist ../lib/stm32/f0 stm32f0 - ../scripts/gendoxylist ../lib/stm32/f1 stm32f1 - ../scripts/gendoxylist ../lib/stm32/f2 stm32f2 - ../scripts/gendoxylist ../lib/stm32/f3 stm32f3 - ../scripts/gendoxylist ../lib/stm32/f4 stm32f4 - ../scripts/gendoxylist ../lib/stm32/f7 stm32f7 - ../scripts/gendoxylist ../lib/stm32/l0 stm32l0 - ../scripts/gendoxylist ../lib/stm32/l1 stm32l1 - ../scripts/gendoxylist ../lib/stm32/l4 stm32l4 - ../scripts/gendoxylist ../lib/efm32/g efm32g - ../scripts/gendoxylist ../lib/efm32/gg efm32gg - ../scripts/gendoxylist ../lib/efm32/hg efm32hg - ../scripts/gendoxylist ../lib/efm32/lg efm32lg - ../scripts/gendoxylist ../lib/efm32/tg efm32tg - ../scripts/gendoxylist ../lib/lm3s lm3s - ../scripts/gendoxylist ../lib/lm4f lm4f - ../scripts/gendoxylist ../lib/msp432/e4 msp432e4 - ../scripts/gendoxylist ../lib/lpc13xx lpc13xx - ../scripts/gendoxylist ../lib/lpc17xx lpc17xx - ../scripts/gendoxylist ../lib/sam/3a sam3a - ../scripts/gendoxylist ../lib/sam/3n sam3n - ../scripts/gendoxylist ../lib/sam/3s sam3s - ../scripts/gendoxylist ../lib/sam/3u sam3u - ../scripts/gendoxylist ../lib/sam/3x sam3x - ../scripts/gendoxylist ../lib/vf6xx vf6xx - -.PHONY: doc html $(ARCHS) rebuildsources +clean: $(CLEAN_TARGETS) + @rm -rf html/ DoxygenLayout.xml doxygen.log + +.PHONY: doc html $(DOC_TARGETS) $(CLEAN_TARGETS) diff --git a/doc/efm32ezr32wg/doxy.custom b/doc/efm32ezr32wg/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/efm32ezr32wg/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/efm32g/Doxyfile b/doc/efm32g/Doxyfile deleted file mode 100644 index 566d50e8..00000000 --- a/doc/efm32g/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for efm32 code level - -# 11 November 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_efm32g.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_efm32g.xml - -GENERATE_TAGFILE = efm32g.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/efm32g/DoxygenLayout_efm32g.xml b/doc/efm32g/DoxygenLayout_efm32g.xml deleted file mode 100644 index a82bb078..00000000 --- a/doc/efm32g/DoxygenLayout_efm32g.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="modules" visible="yes" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/efm32g/doxy.custom b/doc/efm32g/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/efm32g/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/efm32gg/Doxyfile b/doc/efm32gg/Doxyfile deleted file mode 100644 index 7b9cda5b..00000000 --- a/doc/efm32gg/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for efm32 code level - -# 11 November 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_efm32gg.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_efm32gg.xml - -GENERATE_TAGFILE = efm32gg.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/efm32gg/DoxygenLayout_efm32gg.xml b/doc/efm32gg/DoxygenLayout_efm32gg.xml deleted file mode 100644 index 770b4012..00000000 --- a/doc/efm32gg/DoxygenLayout_efm32gg.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="modules" visible="yes" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/efm32gg/doxy.custom b/doc/efm32gg/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/efm32gg/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/efm32hg/Doxyfile b/doc/efm32hg/Doxyfile deleted file mode 100644 index db164da4..00000000 --- a/doc/efm32hg/Doxyfile +++ /dev/null @@ -1,25 +0,0 @@ -# HTML Documentation for efm32 code level - -# 11 November 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_efm32hg.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_efm32hg.xml - -GENERATE_TAGFILE = efm32hg.tag - -ENABLE_PREPROCESSING = YES diff --git a/doc/efm32hg/DoxygenLayout_efm32hg.xml b/doc/efm32hg/DoxygenLayout_efm32hg.xml deleted file mode 100644 index d047bf33..00000000 --- a/doc/efm32hg/DoxygenLayout_efm32hg.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - 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<tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - 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<groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/efm32hg/doxy.custom b/doc/efm32hg/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/efm32hg/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/efm32lg/Doxyfile b/doc/efm32lg/Doxyfile deleted file mode 100644 index 7d5269fa..00000000 --- a/doc/efm32lg/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for efm32 code level - -# 11 November 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_efm32lg.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_efm32lg.xml - -GENERATE_TAGFILE = efm32lg.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/efm32lg/DoxygenLayout_efm32lg.xml b/doc/efm32lg/DoxygenLayout_efm32lg.xml deleted file mode 100644 index a280caed..00000000 --- a/doc/efm32lg/DoxygenLayout_efm32lg.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - 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<inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - 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</memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/efm32lg/doxy.custom b/doc/efm32lg/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/efm32lg/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/efm32tg/Doxyfile b/doc/efm32tg/Doxyfile deleted file mode 100644 index 6ea2b79c..00000000 --- a/doc/efm32tg/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for efm32 code level - -# 11 November 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_efm32tg.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_efm32tg.xml - -GENERATE_TAGFILE = efm32tg.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/efm32tg/DoxygenLayout_efm32tg.xml b/doc/efm32tg/DoxygenLayout_efm32tg.xml deleted file mode 100644 index 82f95cc7..00000000 --- a/doc/efm32tg/DoxygenLayout_efm32tg.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - 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<related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/efm32tg/doxy.custom b/doc/efm32tg/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/efm32tg/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/efm32wg/doxy.custom b/doc/efm32wg/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/efm32wg/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/gd32f1x0/doxy.custom b/doc/gd32f1x0/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/gd32f1x0/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/lm3s/Doxyfile b/doc/lm3s/Doxyfile deleted file mode 100644 index 07a62966..00000000 --- a/doc/lm3s/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for LM3S code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_lm3s.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_lm3s.xml - -GENERATE_TAGFILE = lm3s.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/lm3s/DoxygenLayout_lm3s.xml b/doc/lm3s/DoxygenLayout_lm3s.xml deleted file mode 100644 index 9b929c1d..00000000 --- a/doc/lm3s/DoxygenLayout_lm3s.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="modules" visible="yes" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/lm3s/doxy.custom b/doc/lm3s/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/lm3s/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/lm4f/Doxyfile b/doc/lm4f/Doxyfile deleted file mode 100644 index 16164ce2..00000000 --- a/doc/lm4f/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for LM3S code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_lm4f.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_lm4f.xml - -GENERATE_TAGFILE = lm4f.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/lm4f/DoxygenLayout_lm4f.xml b/doc/lm4f/DoxygenLayout_lm4f.xml deleted file mode 100644 index 28020aa7..00000000 --- a/doc/lm4f/DoxygenLayout_lm4f.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="modules" visible="yes" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/lm4f/doxy.custom b/doc/lm4f/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/lm4f/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/lpc13xx/Doxyfile b/doc/lpc13xx/Doxyfile deleted file mode 100644 index 4ed9d5f8..00000000 --- a/doc/lpc13xx/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for LPC13xx code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_lpc13xx.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_lpc13xx.xml - -GENERATE_TAGFILE = lpc13xx.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/lpc13xx/DoxygenLayout_lpc13xx.xml b/doc/lpc13xx/DoxygenLayout_lpc13xx.xml deleted file mode 100644 index 021885a4..00000000 --- a/doc/lpc13xx/DoxygenLayout_lpc13xx.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="modules" visible="yes" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/lpc13xx/doxy.custom b/doc/lpc13xx/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/lpc13xx/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/lpc17xx/Doxyfile b/doc/lpc17xx/Doxyfile deleted file mode 100644 index 0dba6631..00000000 --- a/doc/lpc17xx/Doxyfile +++ /dev/null @@ -1,28 +0,0 @@ -# HTML Documentation for LPC17xx code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_lpc17xx.log - -INPUT = ../../include/libopencm3/license.dox \ - ../../include/libopencm3/lpc17xx \ - ../../lib/lpc17xx - -LAYOUT_FILE = DoxygenLayout_lpc17xx.xml - -GENERATE_TAGFILE = lpc17xx.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/lpc17xx/doxy.custom b/doc/lpc17xx/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/lpc17xx/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/lpc43xx/Doxyfile b/doc/lpc43xx/Doxyfile deleted file mode 100644 index 52be8d6e..00000000 --- a/doc/lpc43xx/Doxyfile +++ /dev/null @@ -1,28 +0,0 @@ -# HTML Documentation for LPC43xx code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_lpc43xx.log - -INPUT = ../../include/libopencm3/license.dox -INPUT += ../../include/libopencm3/lpc43xx -INPUT += ../../lib/lpc43xx - -LAYOUT_FILE = DoxygenLayout_lpc43xx.xml - -GENERATE_TAGFILE = lpc43xx.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/lpc43xx/DoxygenLayout_lpc43xx.xml b/doc/lpc43xx/DoxygenLayout_lpc43xx.xml deleted file mode 100644 index 747e90fd..00000000 --- a/doc/lpc43xx/DoxygenLayout_lpc43xx.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="modules" visible="yes" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/lpc43xx/doxy.custom b/doc/lpc43xx/doxy.custom new file mode 100644 index 00000000..8b161c91 --- /dev/null +++ b/doc/lpc43xx/doxy.custom @@ -0,0 +1,3 @@ +# Empty file to satisfy doxygen include. +# this directory is for shared code between m3 and m4 cores of lpc43xx +# So needs no predefined arch macros diff --git a/doc/lpc43xxm0/doxy.custom b/doc/lpc43xxm0/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/lpc43xxm0/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/lpc43xxm4/doxy.custom b/doc/lpc43xxm4/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/lpc43xxm4/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/msp432e4/Doxyfile b/doc/msp432e4/Doxyfile deleted file mode 100644 index 889faad5..00000000 --- a/doc/msp432e4/Doxyfile +++ /dev/null @@ -1,11 +0,0 @@ - -# Common settings, you shouldn't have to change these... -@INCLUDE = ../Doxyfile_common -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist -ENABLE_PREPROCESSING = YES - -# Target settings, should only need name changes -WARN_LOGFILE = doxygen_msp432e4.log -LAYOUT_FILE = DoxygenLayout_msp432e4.xml -GENERATE_TAGFILE = msp432e4.tag diff --git a/doc/msp432e4/DoxygenLayout_msp432e4.xml b/doc/msp432e4/DoxygenLayout_msp432e4.xml deleted file mode 100644 index 781fb1e5..00000000 --- a/doc/msp432e4/DoxygenLayout_msp432e4.xml +++ /dev/null @@ -1,210 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="modules" visible="yes" title="MSP432E4" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - 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<memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/msp432e4/doxy.custom b/doc/msp432e4/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/msp432e4/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/sam3a/Doxyfile b/doc/sam3a/Doxyfile deleted file mode 100644 index ea06caee..00000000 --- a/doc/sam3a/Doxyfile +++ /dev/null @@ -1,29 +0,0 @@ -# HTML Documentation for SAM3A code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> -# 09 February 2014 -# (C) Felix Held <felix-libopencm3@felixheld.de> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_sam3a.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_sam3a.xml - -GENERATE_TAGFILE = sam3a.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/sam3a/DoxygenLayout_sam3a.xml b/doc/sam3a/DoxygenLayout_sam3a.xml deleted file mode 100644 index b805baab..00000000 --- a/doc/sam3a/DoxygenLayout_sam3a.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - 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<tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - 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<functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/sam3a/doxy.custom b/doc/sam3a/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/sam3a/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/sam3n/Doxyfile b/doc/sam3n/Doxyfile deleted file mode 100644 index a2dd4612..00000000 --- a/doc/sam3n/Doxyfile +++ /dev/null @@ -1,29 +0,0 @@ -# HTML Documentation for SAM3N code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> -# 09 February 2014 -# (C) Felix Held <felix-libopencm3@felixheld.de> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_sam3n.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_sam3n.xml - -GENERATE_TAGFILE = sam3n.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/sam3n/DoxygenLayout_sam3n.xml b/doc/sam3n/DoxygenLayout_sam3n.xml deleted file mode 100644 index 90c4ccaf..00000000 --- a/doc/sam3n/DoxygenLayout_sam3n.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="modules" visible="yes" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/sam3n/doxy.custom b/doc/sam3n/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/sam3n/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/sam3s/Doxyfile b/doc/sam3s/Doxyfile deleted file mode 100644 index 66a966fa..00000000 --- a/doc/sam3s/Doxyfile +++ /dev/null @@ -1,29 +0,0 @@ -# HTML Documentation for SAM3S code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> -# 09 February 2014 -# (C) Felix Held <felix-libopencm3@felixheld.de> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_sam3s.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_sam3s.xml - -GENERATE_TAGFILE = sam3s.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/sam3s/DoxygenLayout_sam3s.xml b/doc/sam3s/DoxygenLayout_sam3s.xml deleted file mode 100644 index a4501193..00000000 --- a/doc/sam3s/DoxygenLayout_sam3s.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - 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-# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> -# 09 February 2014 -# (C) Felix Held <felix-libopencm3@felixheld.de> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_sam3u.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_sam3u.xml - -GENERATE_TAGFILE = sam3u.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/sam3u/DoxygenLayout_sam3u.xml b/doc/sam3u/DoxygenLayout_sam3u.xml deleted file mode 100644 index 02bfed6e..00000000 --- a/doc/sam3u/DoxygenLayout_sam3u.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - 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-#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_sam3x.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_sam3x.xml - -GENERATE_TAGFILE = sam3x.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/sam3x/DoxygenLayout_sam3x.xml b/doc/sam3x/DoxygenLayout_sam3x.xml deleted file mode 100644 index b8e8bcd0..00000000 --- a/doc/sam3x/DoxygenLayout_sam3x.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - 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<detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/sam3x/doxy.custom b/doc/sam3x/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/sam3x/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/sam4l/doxy.custom b/doc/sam4l/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/sam4l/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/samd/doxy.custom b/doc/samd/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/samd/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/stm32f0/Doxyfile b/doc/stm32f0/Doxyfile deleted file mode 100644 index 3c1d999a..00000000 --- a/doc/stm32f0/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32F0 code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32f0.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32f0.xml - -GENERATE_TAGFILE = stm32f0.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32f0/DoxygenLayout_stm32f0.xml b/doc/stm32f0/DoxygenLayout_stm32f0.xml deleted file mode 100644 index f655f8e1..00000000 --- a/doc/stm32f0/DoxygenLayout_stm32f0.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="modules" visible="yes" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32f0/doxy.custom b/doc/stm32f0/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/stm32f0/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/stm32f0/index.html b/doc/stm32f0/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32f0/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32f1/Doxyfile b/doc/stm32f1/Doxyfile deleted file mode 100644 index 65432dee..00000000 --- a/doc/stm32f1/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32F1 code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32f1.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32f1.xml - -GENERATE_TAGFILE = stm32f1.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32f1/DoxygenLayout_stm32f1.xml b/doc/stm32f1/DoxygenLayout_stm32f1.xml deleted file mode 100644 index a80af394..00000000 --- a/doc/stm32f1/DoxygenLayout_stm32f1.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="modules" visible="yes" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32f1/doxy.custom b/doc/stm32f1/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/stm32f1/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/stm32f1/index.html b/doc/stm32f1/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32f1/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32f2/Doxyfile b/doc/stm32f2/Doxyfile deleted file mode 100644 index 88eb906f..00000000 --- a/doc/stm32f2/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32F2 code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32f2.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32f2.xml - -GENERATE_TAGFILE = stm32f2.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32f2/DoxygenLayout_stm32f2.xml b/doc/stm32f2/DoxygenLayout_stm32f2.xml deleted file mode 100644 index 3eaa835e..00000000 --- a/doc/stm32f2/DoxygenLayout_stm32f2.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="modules" visible="yes" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - 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<typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - 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-#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32f3.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32f3.xml - -GENERATE_TAGFILE = stm32f3.tag - -ENABLE_PREPROCESSING = YES diff --git a/doc/stm32f3/DoxygenLayout_stm32f3.xml b/doc/stm32f3/DoxygenLayout_stm32f3.xml deleted file mode 100644 index 5a582bef..00000000 --- a/doc/stm32f3/DoxygenLayout_stm32f3.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="modules" visible="yes" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - 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<tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32f3/doxy.custom b/doc/stm32f3/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/stm32f3/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/stm32f3/index.html b/doc/stm32f3/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32f3/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32f4/Doxyfile b/doc/stm32f4/Doxyfile deleted file mode 100644 index 67f4ed8f..00000000 --- a/doc/stm32f4/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32F4 code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32f4.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32f4.xml - -GENERATE_TAGFILE = stm32f4.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32f4/DoxygenLayout_stm32f4.xml b/doc/stm32f4/DoxygenLayout_stm32f4.xml deleted file mode 100644 index acb0cbbe..00000000 --- a/doc/stm32f4/DoxygenLayout_stm32f4.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="modules" visible="yes" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - 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<tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32f4/doxy.custom b/doc/stm32f4/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/stm32f4/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/stm32f4/index.html b/doc/stm32f4/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32f4/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32f7/Doxyfile b/doc/stm32f7/Doxyfile deleted file mode 100644 index 3d2c9e45..00000000 --- a/doc/stm32f7/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32F7 code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32f7.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32f7.xml - -GENERATE_TAGFILE = stm32f7.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32f7/DoxygenLayout_stm32f7.xml b/doc/stm32f7/DoxygenLayout_stm32f7.xml deleted file mode 100644 index ca2647e0..00000000 --- a/doc/stm32f7/DoxygenLayout_stm32f7.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="modules" visible="yes" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32f7/doxy.custom b/doc/stm32f7/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/stm32f7/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/stm32f7/index.html b/doc/stm32f7/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32f7/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32g0/doxy.custom b/doc/stm32g0/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/stm32g0/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/stm32l0/Doxyfile b/doc/stm32l0/Doxyfile deleted file mode 100644 index 6a5f10b5..00000000 --- a/doc/stm32l0/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32L0 code level - -# 15 December 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32l0.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32l0.xml - -GENERATE_TAGFILE = stm32l0.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32l0/DoxygenLayout_stm32l0.xml b/doc/stm32l0/DoxygenLayout_stm32l0.xml deleted file mode 100644 index e2743deb..00000000 --- a/doc/stm32l0/DoxygenLayout_stm32l0.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="modules" visible="yes" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32l0/doxy.custom b/doc/stm32l0/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/stm32l0/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/stm32l0/index.html b/doc/stm32l0/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32l0/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32l1/Doxyfile b/doc/stm32l1/Doxyfile deleted file mode 100644 index 95820578..00000000 --- a/doc/stm32l1/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32L1 code level - -# 15 December 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32l1.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32l1.xml - -GENERATE_TAGFILE = stm32l1.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32l1/DoxygenLayout_stm32l1.xml b/doc/stm32l1/DoxygenLayout_stm32l1.xml deleted file mode 100644 index 31f00e6d..00000000 --- a/doc/stm32l1/DoxygenLayout_stm32l1.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="modules" visible="yes" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32l1/doxy.custom b/doc/stm32l1/doxy.custom new file mode 100644 index 00000000..54f3dc9e --- /dev/null +++ b/doc/stm32l1/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7M__ diff --git a/doc/stm32l1/index.html b/doc/stm32l1/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32l1/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/stm32l4/Doxyfile b/doc/stm32l4/Doxyfile deleted file mode 100644 index 153cec42..00000000 --- a/doc/stm32l4/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for STM32L4 code level - -# 15 December 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_stm32l4.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_stm32l4.xml - -GENERATE_TAGFILE = stm32l4.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/stm32l4/DoxygenLayout_stm32l4.xml b/doc/stm32l4/DoxygenLayout_stm32l4.xml deleted file mode 100644 index 59e9aea8..00000000 --- a/doc/stm32l4/DoxygenLayout_stm32l4.xml +++ /dev/null @@ -1,209 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="modules" visible="yes" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> - <tab type="namespaces" visible="yes" title=""> - <tab type="namespaces" visible="yes" title="" intro=""/> - <tab type="namespacemembers" visible="yes" title="" intro=""/> - </tab> - <tab type="classes" visible="yes" title=""> - <tab type="classes" visible="yes" title="" intro=""/> - <tab type="classindex" visible="$ALPHABETICAL_INDEX" title=""/> - <tab type="hierarchy" visible="yes" title="" intro=""/> - <tab type="classmembers" visible="yes" title="" intro=""/> - </tab> - <tab type="files" visible="yes" title=""> - <tab type="files" visible="yes" title="" intro=""/> - <tab type="globals" visible="yes" title="" intro=""/> - </tab> - <tab type="examples" visible="yes" title="" intro=""/> - </navindex> - - <!-- Layout definition for a class page --> - <class> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <inheritancegraph visible="$CLASS_GRAPH"/> - <collaborationgraph visible="$COLLABORATION_GRAPH"/> - <allmemberslink visible="yes"/> - <memberdecl> - <nestedclasses visible="yes" title=""/> - <publictypes title=""/> - <publicslots title=""/> - <signals title=""/> - <publicmethods title=""/> - <publicstaticmethods title=""/> - <publicattributes title=""/> - <publicstaticattributes title=""/> - <protectedtypes title=""/> - <protectedslots title=""/> - <protectedmethods title=""/> - <protectedstaticmethods title=""/> - <protectedattributes title=""/> - <protectedstaticattributes title=""/> - <packagetypes title=""/> - <packagemethods title=""/> - <packagestaticmethods title=""/> - <packageattributes title=""/> - <packagestaticattributes title=""/> - <properties title=""/> - <events title=""/> - <privatetypes title=""/> - <privateslots title=""/> - <privatemethods title=""/> - <privatestaticmethods title=""/> - <privateattributes title=""/> - <privatestaticattributes title=""/> - <friends title=""/> - <related title="" subtitle=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <constructors title=""/> - <functions title=""/> - <related title=""/> - <variables title=""/> - <properties title=""/> - <events title=""/> - </memberdef> - <usedfiles visible="$SHOW_USED_FILES"/> - <authorsection visible="yes"/> - </class> - - <!-- Layout definition for a namespace page --> - <namespace> - <briefdescription visible="yes"/> - <memberdecl> - <nestednamespaces visible="yes" title=""/> - <classes visible="yes" title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection visible="yes"/> - </namespace> - - <!-- Layout definition for a file page --> - <file> - <briefdescription visible="yes"/> - <includes visible="$SHOW_INCLUDE_FILES"/> - <includegraph visible="$INCLUDE_GRAPH"/> - <includedbygraph visible="$INCLUDED_BY_GRAPH"/> - <sourcelink visible="yes"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <functions title=""/> - <variables title=""/> - </memberdef> - <authorsection/> - </file> - - <!-- Layout definition for a group page --> - <group> - <briefdescription visible="yes"/> - <groupgraph visible="$GROUP_GRAPHS"/> - <memberdecl> - <classes visible="yes" title=""/> - <namespaces visible="yes" title=""/> - <dirs visible="yes" title=""/> - <nestedgroups visible="yes" title=""/> - <files visible="yes" title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - <membergroups visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - <memberdef> - <pagedocs/> - <inlineclasses title=""/> - <defines title=""/> - <typedefs title=""/> - <enums title=""/> - <enumvalues title=""/> - <functions title=""/> - <variables title=""/> - <signals title=""/> - <publicslots title=""/> - <protectedslots title=""/> - <privateslots title=""/> - <events title=""/> - <properties title=""/> - <friends title=""/> - </memberdef> - <authorsection visible="yes"/> - </group> - - <!-- Layout definition for a directory page --> - <directory> - <briefdescription visible="yes"/> - <directorygraph visible="yes"/> - <memberdecl> - <dirs visible="yes"/> - <files visible="yes"/> - </memberdecl> - <detaileddescription title=""/> - </directory> -</doxygenlayout> diff --git a/doc/stm32l4/doxy.custom b/doc/stm32l4/doxy.custom new file mode 100644 index 00000000..4789a761 --- /dev/null +++ b/doc/stm32l4/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_7EM__ diff --git a/doc/stm32l4/index.html b/doc/stm32l4/index.html deleted file mode 100644 index 7715877a..00000000 --- a/doc/stm32l4/index.html +++ /dev/null @@ -1,8 +0,0 @@ -<html xmlns="http://www.w3.org/1999/xhtml"> -<head> - <meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/doc/swm050/doxy.custom b/doc/swm050/doxy.custom new file mode 100644 index 00000000..56f73ff9 --- /dev/null +++ b/doc/swm050/doxy.custom @@ -0,0 +1 @@ +PREDEFINED += __ARM_ARCH_6M__ diff --git a/doc/templates/Doxyfile_Device b/doc/templates/Doxyfile_Device new file mode 100644 index 00000000..4efe6f5a --- /dev/null +++ b/doc/templates/Doxyfile_Device @@ -0,0 +1,8 @@ +@INCLUDE = ../Doxyfile_common +INPUT = ../../include/libopencm3/license.dox +@INCLUDE = doxy.sourcelist +@INCLUDE = doxy.custom +WARN_LOGFILE = doxygen_#device#.log +LAYOUT_FILE = DoxygenLayout_#device#.xml +GENERATE_TAGFILE = #device#.tag +ENABLE_PREPROCESSING = YES diff --git a/doc/lpc17xx/DoxygenLayout_lpc17xx.xml b/doc/templates/DoxygenLayout_Device.xml index 122b8c57..853301b3 100644 --- a/doc/lpc17xx/DoxygenLayout_lpc17xx.xml +++ b/doc/templates/DoxygenLayout_Device.xml @@ -4,30 +4,7 @@ <tab type="mainpage" visible="yes" title="libopencm3"/> <tab type="pages" visible="yes" title="General Information" intro=""/> <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="modules" visible="yes" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../../vf6xx/html/modules.html" title="VF6XX" intro=""/> + <!-- #devices# --> <tab type="namespaces" visible="yes" title=""> <tab type="namespaces" visible="yes" title="" intro=""/> <tab type="namespacemembers" visible="yes" title="" intro=""/> diff --git a/doc/DoxygenLayout.xml b/doc/templates/DoxygenLayout_Root.xml index de27fa5d..e39594f8 100644 --- a/doc/DoxygenLayout.xml +++ b/doc/templates/DoxygenLayout_Root.xml @@ -4,32 +4,7 @@ <tab type="mainpage" visible="yes" title="libopencm3"/> <tab type="pages" visible="yes" title="General Information" intro=""/> <tab type="user" visible="yes" url="../html/index.html" title="Top Level" intro=""/> - <tab type="user" visible="yes" url="../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../stm32f3/html/modules.html" title="STM32F3" intro=""/> - <tab type="user" visible="yes" url="../stm32f4/html/modules.html" title="STM32F4" intro=""/> - <tab type="user" visible="yes" url="../stm32f7/html/modules.html" title="STM32F7" intro=""/> - <tab type="user" visible="yes" url="../stm32l0/html/modules.html" title="STM32L0" intro=""/> - <tab type="user" visible="yes" url="../stm32l1/html/modules.html" title="STM32L1" intro=""/> - <tab type="user" visible="yes" url="../stm32l4/html/modules.html" title="STM32L4" intro=""/> - <tab type="user" visible="yes" url="../lm3s/html/modules.html" title="LM3S" intro=""/> - <tab type="user" visible="yes" url="../lm4f/html/modules.html" title="LM4F" intro=""/> - <tab type="user" visible="yes" url="../msp432e4/html/modules.html" title="MSP432E4" intro=""/> - <tab type="user" visible="yes" url="../lpc13xx/html/modules.html" title="LPC13" intro=""/> - <tab type="user" visible="yes" url="../lpc17xx/html/modules.html" title="LPC17" intro=""/> - <tab type="user" visible="yes" url="../lpc43xx/html/modules.html" title="LPC43" intro=""/> - <tab type="user" visible="yes" url="../efm32g/html/modules.html" title="EFM32 Gecko" intro=""/> - <tab type="user" visible="yes" url="../efm32gg/html/modules.html" title="EFM32 Giant Gecko" intro=""/> - <tab type="user" visible="yes" url="../efm32hg/html/modules.html" title="EFM32 Happy Gecko" intro=""/> - <tab type="user" visible="yes" url="../efm32lg/html/modules.html" title="EFM32 Leopard Gecko" intro=""/> - <tab type="user" visible="yes" url="../efm32tg/html/modules.html" title="EFM32 Tiny Gecko" intro=""/> - <tab type="user" visible="yes" url="../sam3a/html/modules.html" title="SAM3A" intro=""/> - <tab type="user" visible="yes" url="../sam3n/html/modules.html" title="SAM3N" intro=""/> - <tab type="user" visible="yes" url="../sam3s/html/modules.html" title="SAM3S" intro=""/> - <tab type="user" visible="yes" url="../sam3u/html/modules.html" title="SAM3U" intro=""/> - <tab type="user" visible="yes" url="../sam3x/html/modules.html" title="SAM3X" intro=""/> - <tab type="user" visible="yes" url="../vf6xx/html/modules.html" title="VF6XX" intro=""/> + <!-- #devices# --> <tab type="namespaces" visible="yes" title=""> <tab type="namespaces" visible="yes" title="" intro=""/> <tab type="namespacemembers" visible="yes" title="" intro=""/> diff --git a/doc/vf6xx/Doxyfile b/doc/vf6xx/Doxyfile deleted file mode 100644 index 5041a4b3..00000000 --- a/doc/vf6xx/Doxyfile +++ /dev/null @@ -1,27 +0,0 @@ -# HTML Documentation for VF6XX code level - -# 14 September 2012 -# (C) Ken Sarkies <ksarkies@internode.on.net> - -#--------------------------------------------------------------------------- -# Common Include File -#--------------------------------------------------------------------------- - -@INCLUDE = ../Doxyfile_common - -#--------------------------------------------------------------------------- -# Local settings -#--------------------------------------------------------------------------- - -WARN_LOGFILE = doxygen_vf6xx.log - -INPUT = ../../include/libopencm3/license.dox -@INCLUDE = doxy.sourcelist - -LAYOUT_FILE = DoxygenLayout_vf6xx.xml - -GENERATE_TAGFILE = vf6xx.tag - -ENABLE_PREPROCESSING = YES - - diff --git a/doc/vf6xx/DoxygenLayout_vf6xx.xml b/doc/vf6xx/DoxygenLayout_vf6xx.xml deleted file mode 100644 index 5591d099..00000000 --- a/doc/vf6xx/DoxygenLayout_vf6xx.xml +++ /dev/null @@ -1,208 +0,0 @@ -<doxygenlayout version="1.0"> - <!-- Navigation index tabs for HTML output --> - <navindex> - <tab type="mainpage" visible="yes" title="libopencm3"/> - <tab type="pages" visible="yes" title="General Information" intro=""/> - <tab type="user" visible="yes" url="../../html/index.html" title="Back to Top" intro=""/> - <tab type="user" visible="yes" url="../../stm32f0/html/modules.html" title="STM32F0" intro=""/> - <tab type="user" visible="yes" url="../../stm32f1/html/modules.html" title="STM32F1" intro=""/> - <tab type="user" visible="yes" url="../../stm32f2/html/modules.html" title="STM32F2" intro=""/> - <tab type="user" visible="yes" url="../../stm32f3/html/modules.html" title="STM32F3" intro=""/> - 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<meta http-equiv="refresh" content="0;URL='html/index.html'" /> -</head> -<body> - <a href="html/index.html">Documentation index</a></p> -</body> -</html> diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h index a7a8df8d..04714e0a 100644 --- a/include/libopencm3/cm3/common.h +++ b/include/libopencm3/cm3/common.h @@ -20,15 +20,16 @@ #ifndef LIBOPENCM3_CM3_COMMON_H #define LIBOPENCM3_CM3_COMMON_H -#include <stdint.h> -#include <stdbool.h> - -/* This must be placed around external function declaration for C++ - * support. */ #ifdef __cplusplus +/* Declarations need wrapping for C++ */ # define BEGIN_DECLS extern "C" { # define END_DECLS } +#elif defined(__ASSEMBLER__) +/* skipping for assembly */ +#define BEGIN_DECLS .if 0 +#define END_DECLS .endif #else +/* And nothing for C */ # define BEGIN_DECLS # define END_DECLS #endif @@ -46,6 +47,22 @@ #endif +#if defined (__ASSEMBLER__) +#define MMIO8(addr) (addr) +#define MMIO16(addr) (addr) +#define MMIO32(addr) (addr) +#define MMIO64(addr) (addr) + +#define BBIO_SRAM(addr, bit) \ + (((addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4) + +#define BBIO_PERIPH(addr, bit) \ + (((addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4) +#else + +#include <stdint.h> +#include <stdbool.h> + /* Generic memory-mapped I/O accessor functions */ #define MMIO8(addr) (*(volatile uint8_t *)(addr)) #define MMIO16(addr) (*(volatile uint16_t *)(addr)) @@ -58,6 +75,7 @@ #define BBIO_PERIPH(addr, bit) \ MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4) +#endif /* Generic bit definition */ #define BIT0 (1<<0) diff --git a/include/libopencm3/cm3/cortex.h b/include/libopencm3/cm3/cortex.h index cca18b38..7065c2bd 100644 --- a/include/libopencm3/cm3/cortex.h +++ b/include/libopencm3/cm3/cortex.h @@ -186,7 +186,7 @@ static inline uint32_t __cm_atomic_set(uint32_t *val) * @note It is safe to use this block inside normal code and in interrupt * routine. * - * @example 1: Basic usage of atomic block + * Basic usage of atomic block * * @code * uint64_t value; // This value is used somewhere in interrupt @@ -198,7 +198,7 @@ static inline uint32_t __cm_atomic_set(uint32_t *val) * } // interrupts is restored automatically * @endcode * - * @example 2: Use of return inside block: + * Use of return inside block * * @code * uint64_t value; // This value is used somewhere in interrupt @@ -237,7 +237,7 @@ static inline uint32_t __cm_atomic_set(uint32_t *val) * @note It is safe to use this block inside normal code and in interrupt * routine. * - * @example 1: Basic usage of atomic context + * Basic usage of atomic context * * @code * uint64_t value; // This value is used somewhere in interrupt @@ -253,7 +253,7 @@ static inline uint32_t __cm_atomic_set(uint32_t *val) * } // interrupts is restored automatically * @endcode * - * @example 2: Usage of atomic context inside atomic reader fcn. + * Usage of atomic context inside atomic reader fcn. * * @code * uint64_t value; // This value is used somewhere in interrupt diff --git a/include/libopencm3/cm3/doc-cm3.h b/include/libopencm3/cm3/doc-cm3.h index 0f76370f..1924b178 100644 --- a/include/libopencm3/cm3/doc-cm3.h +++ b/include/libopencm3/cm3/doc-cm3.h @@ -20,3 +20,7 @@ LGPL License Terms @ref lgpl_license LGPL License Terms @ref lgpl_license */ +/** @defgroup CM3_files Cortex Core Peripheral APIs + * APIs for Cortex Core peripherals + */ + diff --git a/include/libopencm3/cm3/mpu.h b/include/libopencm3/cm3/mpu.h index 3d6960af..d47abc60 100644 --- a/include/libopencm3/cm3/mpu.h +++ b/include/libopencm3/cm3/mpu.h @@ -17,7 +17,7 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/** @defgroup CM3_mpu_defines MPU Defines +/** @defgroup CM3_mpu_defines Cortex-M MPU Defines * * @brief <b>libopencm3 Cortex Memory Protection Unit</b> * @@ -45,7 +45,7 @@ * @ingroup CM3_mpu_defines * *@{*/ -/** MPU_TYPE is alays available, even if the MPU is not implemented */ +/** MPU_TYPE is always available, even if the MPU is not implemented */ #define MPU_TYPE MMIO32(MPU_BASE + 0x00) #define MPU_CTRL MMIO32(MPU_BASE + 0x04) #define MPU_RNR MMIO32(MPU_BASE + 0x08) diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index 216833e3..0bd51340 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -18,7 +18,7 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/** @defgroup CM3_nvic_defines NVIC Defines +/** @defgroup CM3_nvic_defines Cortex-M NVIC Defines * * @brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b> * @@ -40,35 +40,41 @@ #include <libopencm3/cm3/common.h> #include <libopencm3/cm3/memorymap.h> -/* --- NVIC Registers ------------------------------------------------------ */ +/** @defgroup nvic_registers NVIC Registers + * @{ + */ -/* ISER: Interrupt Set Enable Registers */ -/* Note: 8 32bit Registers */ -/* Note: Single register on CM0 */ +/** ISER: Interrupt Set Enable Registers + * @note 8 32bit Registers + * @note Single register on CM0 + */ #define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \ ((iser_id) * 4)) /* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ -/* ICER: Interrupt Clear Enable Registers */ -/* Note: 8 32bit Registers */ -/* Note: Single register on CM0 */ +/** ICER: Interrupt Clear Enable Registers + * @note 8 32bit Registers + * @note Single register on CM0 + */ #define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \ ((icer_id) * 4)) /* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ -/* ISPR: Interrupt Set Pending Registers */ -/* Note: 8 32bit Registers */ -/* Note: Single register on CM0 */ +/** ISPR: Interrupt Set Pending Registers + * @note 8 32bit Registers + * @note Single register on CM0 + */ #define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \ ((ispr_id) * 4)) /* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ -/* ICPR: Interrupt Clear Pending Registers */ -/* Note: 8 32bit Registers */ -/* Note: Single register on CM0 */ +/** ICPR: Interrupt Clear Pending Registers + * @note 8 32bit Registers + * @note Single register on CM0 + */ #define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \ ((icpr_id) * 4)) @@ -76,25 +82,28 @@ /* Those defined only on ARMv7 and above */ #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* IABR: Interrupt Active Bit Register */ -/* Note: 8 32bit Registers */ +/** IABR: Interrupt Active Bit Register + * @note 8 32bit Registers */ #define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \ ((iabr_id) * 4)) #endif /* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ -/* IPR: Interrupt Priority Registers */ -/* Note: 240 8bit Registers */ -/* Note: 32 8bit Registers on CM0 */ +/** IPR: Interrupt Priority Registers + * @note 240 8bit Registers + * @@note 32 8bit Registers on CM0 + */ #define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \ (ipr_id)) #if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) -/* STIR: Software Trigger Interrupt Register */ +/** STIR: Software Trigger Interrupt Register */ #define NVIC_STIR MMIO32(STIR_BASE) #endif +/**@}*/ + /* --- IRQ channel numbers-------------------------------------------------- */ /* Cortex M0, M3 and M4 System Interrupts */ @@ -126,7 +135,7 @@ IRQ numbers -3 and -6 to -9 are reserved #define NVIC_SYSTICK_IRQ -1 /**@}*/ -/* Note: User interrupts are family specific and are defined in a family +/* @note User interrupts are family specific and are defined in a family * specific header file in the corresponding subfolder. */ diff --git a/include/libopencm3/cm3/systick.h b/include/libopencm3/cm3/systick.h index a355b0f8..0f620bf0 100644 --- a/include/libopencm3/cm3/systick.h +++ b/include/libopencm3/cm3/systick.h @@ -17,7 +17,7 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/** @defgroup CM3_systick_defines SysTick Defines +/** @defgroup CM3_systick_defines Cortex-M SysTick Defines * * @brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b> * diff --git a/include/libopencm3/dispatch/nvic.h b/include/libopencm3/dispatch/nvic.h index a71b6787..b7e2810b 100644 --- a/include/libopencm3/dispatch/nvic.h +++ b/include/libopencm3/dispatch/nvic.h @@ -20,6 +20,11 @@ # include <libopencm3/stm32/l1/nvic.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/nvic.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/nvic.h> + +#elif defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/nvic.h> #elif defined(EFM32TG) # include <libopencm3/efm32/tg/nvic.h> @@ -70,6 +75,9 @@ #elif defined(VF6XX) # include <libopencm3/vf6xx/nvic.h> +#elif defined(SWM050) +# include <libopencm3/swm050/nvic.h> + #else # warning"no interrupts defined for chipset; NVIC_IRQ_COUNT = 0" diff --git a/include/libopencm3/efm32/common/acmp_common.h b/include/libopencm3/efm32/common/acmp_common.h index 1377e663..e47a1ad7 100644 --- a/include/libopencm3/efm32/common/acmp_common.h +++ b/include/libopencm3/efm32/common/acmp_common.h @@ -1,3 +1,5 @@ +/** @addtogroup acmp_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,8 +19,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_ACMP_H -#define LIBOPENCM3_EFM32_ACMP_H +#pragma once + +/**@{*/ #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> @@ -181,5 +184,4 @@ #define ACMP1_IFC ACMP_IFC(ACMP1) #define ACMP1_ROUTE ACMP_ROUTE(ACMP1) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/adc_common.h b/include/libopencm3/efm32/common/adc_common.h index cc41c197..0ce80a41 100644 --- a/include/libopencm3/efm32/common/adc_common.h +++ b/include/libopencm3/efm32/common/adc_common.h @@ -1,3 +1,5 @@ +/** @addtogroup adc_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,8 +19,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_ADC_H -#define LIBOPENCM3_EFM32_ADC_H +/**@{*/ + +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> @@ -340,8 +343,6 @@ #define ADC0_BIASPROG ADC_BIASPROG(ADC0) /** @defgroup adc_ch ADC Channel Number -@ingroup adc_defines - @{*/ #define ADC_CH0 0 #define ADC_CH1 1 @@ -453,5 +454,4 @@ void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/burtc_common.h b/include/libopencm3/efm32/common/burtc_common.h index 73f78e1c..e2202a15 100644 --- a/include/libopencm3/efm32/common/burtc_common.h +++ b/include/libopencm3/efm32/common/burtc_common.h @@ -1,3 +1,5 @@ +/** @addtogroup burtc_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_BURTC_H -#define LIBOPENCM3_EFM32_BURTC_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define BURTC_CTRL MMIO32(BURTC_BASE + 0x000) #define BURTC_LPMODE MMIO32(BURTC_BASE + 0x004) #define BURTC_CNT MMIO32(BURTC_BASE + 0x008) @@ -166,5 +169,5 @@ #define BURTC_SYNCBUSY_COMP0 (1 << 1) #define BURTC_SYNCBUSY_LPMODE (1 << 0) -#endif +/**@}*/ diff --git a/include/libopencm3/efm32/common/cmu_common.h b/include/libopencm3/efm32/common/cmu_common.h index caac95de..e2005946 100644 --- a/include/libopencm3/efm32/common/cmu_common.h +++ b/include/libopencm3/efm32/common/cmu_common.h @@ -1,3 +1,5 @@ +/** @addtogroup cmu_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,8 +19,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_CMU_H -#define LIBOPENCM3_EFM32_CMU_H +#pragma once + +/**@{*/ #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> @@ -701,5 +704,4 @@ void cmu_clock_setup_in_hfxo_out_48mhz(void); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/dac_common.h b/include/libopencm3/efm32/common/dac_common.h index ff07d4fa..d77bd751 100644 --- a/include/libopencm3/efm32/common/dac_common.h +++ b/include/libopencm3/efm32/common/dac_common.h @@ -1,3 +1,5 @@ +/** @addtogroup dac_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,13 +19,14 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_DAC_H -#define LIBOPENCM3_EFM32_DAC_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> #include <libopencm3/efm32/prs.h> +/**@{*/ + #define DAC_CTRL(base) MMIO32((base) + 0x00) #define DAC_STATUS(base) MMIO32((base) + 0x04) #define DAC_CHx_CTRL(base, x) MMIO32((base) + 0x08 + (0x04 * (x))) @@ -508,5 +511,4 @@ void dac_disable_channel(uint32_t dac_base, enum dac_ch ch); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/dma_common.h b/include/libopencm3/efm32/common/dma_common.h index 6e46d9d0..d274979a 100644 --- a/include/libopencm3/efm32/common/dma_common.h +++ b/include/libopencm3/efm32/common/dma_common.h @@ -1,3 +1,5 @@ +/** @addtogroup dma_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_DMA_H -#define LIBOPENCM3_EFM32_DMA_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + /* * As per the datasheet, it is an PL230 (licenced from ARM) * note: but only implement 12 channel (PL230 can have upto 32 channels) @@ -908,5 +911,4 @@ void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/emu_common.h b/include/libopencm3/efm32/common/emu_common.h index 7d220c50..f33020bc 100644 --- a/include/libopencm3/efm32/common/emu_common.h +++ b/include/libopencm3/efm32/common/emu_common.h @@ -1,3 +1,5 @@ +/** @addtogroup emu_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EMU_H -#define LIBOPENCM3_EFM32_EMU_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define EMU_CTRL MMIO32(EMU_BASE + 0x000) #define EMU_LOCK MMIO32(EMU_BASE + 0x008) #define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) @@ -185,5 +188,4 @@ (((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \ EMU_BUBODUNREGCAL_THRES_MASK) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/gpio_common.h b/include/libopencm3/efm32/common/gpio_common.h index d8bce510..5099b997 100644 --- a/include/libopencm3/efm32/common/gpio_common.h +++ b/include/libopencm3/efm32/common/gpio_common.h @@ -1,3 +1,5 @@ +/** @addtogroup gpio_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_GPIO_H -#define LIBOPENCM3_EFM32_GPIO_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define GPIO_P(i) (GPIO_BASE + (0x24 * (i))) #define GPIO_PA GPIO_P(0) #define GPIO_PB GPIO_P(1) @@ -326,5 +329,4 @@ void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/gpio_common_hglg.h b/include/libopencm3/efm32/common/gpio_common_hglg.h index 7e141117..55744902 100644 --- a/include/libopencm3/efm32/common/gpio_common_hglg.h +++ b/include/libopencm3/efm32/common/gpio_common_hglg.h @@ -1,3 +1,5 @@ +/** @addtogroup gpio_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,15 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/** @cond */ -#if defined(LIBOPENCM3_GPIO_H) -/** @endcond */ -#ifndef LIBOPENCM3_EFM32_GPIO_COMMON_HGLG_H -#define LIBOPENCM3_EFM32_GPIO_COMMON_HGLG_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define GPIO_P(i) (GPIO_BASE + (0x24 * (i))) #define GPIO_PA GPIO_P(0) #define GPIO_PB GPIO_P(1) @@ -329,9 +329,4 @@ void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios); END_DECLS -#endif -/** @cond */ -#else -#warning "gpio_common_hglg.h should not be included explicitly, only via gpio.h" -#endif -/** @endcond */ +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/i2c_common.h b/include/libopencm3/efm32/common/i2c_common.h index 92f9d737..c9a53fe9 100644 --- a/include/libopencm3/efm32/common/i2c_common.h +++ b/include/libopencm3/efm32/common/i2c_common.h @@ -1,3 +1,5 @@ +/** @addtogroup i2c_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_I2C_H -#define LIBOPENCM3_EFM32_I2C_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define I2C_CTRL(base) MMIO32((base) + 0x000) #define I2C_CMD(base) MMIO32((base) + 0x004) #define I2C_STATE(base) MMIO32((base) + 0x008) @@ -231,39 +234,38 @@ /* I2C0 */ #define I2C0 I2C0_BASE -#define I2C0_CTRL I2C_CTRL(base) -#define I2C0_CMD I2C_CMD(base) -#define I2C0_STATE I2C_STATE(base) -#define I2C0_STATUS I2C_STATUS(base) -#define I2C0_CLKDIV I2C_CLKDIV(base) -#define I2C0_SADDR I2C_SADDR(base) -#define I2C0_SADDRMASK I2C_SADDRMASK(base) -#define I2C0_RXDATA I2C_RXDATA(base) -#define I2C0_RXDATAP I2C_RXDATAP(base) -#define I2C0_TXDATA I2C_TXDATA(base) -#define I2C0_IF I2C_IF(base) -#define I2C0_IFS I2C_IFS(base) -#define I2C0_IFC I2C_IFC(base) -#define I2C0_IEN I2C_IEN(base) -#define I2C0_ROUTE I2C_ROUTE(base) +#define I2C0_CTRL I2C_CTRL(I2C0) +#define I2C0_CMD I2C_CMD(I2C0) +#define I2C0_STATE I2C_STATE(I2C0) +#define I2C0_STATUS I2C_STATUS(I2C0) +#define I2C0_CLKDIV I2C_CLKDIV(I2C0) +#define I2C0_SADDR I2C_SADDR(I2C0) +#define I2C0_SADDRMASK I2C_SADDRMASK(I2C0) +#define I2C0_RXDATA I2C_RXDATA(I2C0) +#define I2C0_RXDATAP I2C_RXDATAP(I2C0) +#define I2C0_TXDATA I2C_TXDATA(I2C0) +#define I2C0_IF I2C_IF(I2C0) +#define I2C0_IFS I2C_IFS(I2C0) +#define I2C0_IFC I2C_IFC(I2C0) +#define I2C0_IEN I2C_IEN(I2C0) +#define I2C0_ROUTE I2C_ROUTE(I2C0) /* I2C1 */ #define I2C1 I2C1_BASE -#define I2C1_CTRL I2C_CTRL(base) -#define I2C1_CMD I2C_CMD(base) -#define I2C1_STATE I2C_STATE(base) -#define I2C1_STATUS I2C_STATUS(base) -#define I2C1_CLKDIV I2C_CLKDIV(base) -#define I2C1_SADDR I2C_SADDR(base) -#define I2C1_SADDRMASK I2C_SADDRMASK(base) -#define I2C1_RXDATA I2C_RXDATA(base) -#define I2C1_RXDATAP I2C_RXDATAP(base) -#define I2C1_TXDATA I2C_TXDATA(base) -#define I2C1_IF I2C_IF(base) -#define I2C1_IFS I2C_IFS(base) -#define I2C1_IFC I2C_IFC(base) -#define I2C1_IEN I2C_IEN(base) -#define I2C1_ROUTE I2C_ROUTE(base) - -#endif +#define I2C1_CTRL I2C_CTRL(I2C1) +#define I2C1_CMD I2C_CMD(I2C1) +#define I2C1_STATE I2C_STATE(I2C1) +#define I2C1_STATUS I2C_STATUS(I2C1) +#define I2C1_CLKDIV I2C_CLKDIV(I2C1) +#define I2C1_SADDR I2C_SADDR(I2C1) +#define I2C1_SADDRMASK I2C_SADDRMASK(I2C1) +#define I2C1_RXDATA I2C_RXDATA(I2C1) +#define I2C1_RXDATAP I2C_RXDATAP(I2C1) +#define I2C1_TXDATA I2C_TXDATA(I2C1) +#define I2C1_IF I2C_IF(I2C1) +#define I2C1_IFS I2C_IFS(I2C1) +#define I2C1_IFC I2C_IFC(I2C1) +#define I2C1_IEN I2C_IEN(I2C1) +#define I2C1_ROUTE I2C_ROUTE(I2C1) +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/letimer_common.h b/include/libopencm3/efm32/common/letimer_common.h index 40c2f9ff..a7826731 100644 --- a/include/libopencm3/efm32/common/letimer_common.h +++ b/include/libopencm3/efm32/common/letimer_common.h @@ -1,3 +1,5 @@ +/** @addtogroup letimer_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LETIMER_H -#define LIBOPENCM3_EFM32_LETIMER_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define LETIMER_CTRL(base) ((base) + 0x000) #define LETIMER_CMD(base) ((base) + 0x004) #define LETIMER_STATUS(base) ((base) + 0x008) @@ -161,5 +164,4 @@ #define LETIMER0_SYNCBUSY LETIMER_SYNCBUSY(LETIMER0) #define LETIMER0_ROUTE LETIMER_ROUTE(LETIMER0) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/msc_common.h b/include/libopencm3/efm32/common/msc_common.h index 0dd7a782..34932c63 100644 --- a/include/libopencm3/efm32/common/msc_common.h +++ b/include/libopencm3/efm32/common/msc_common.h @@ -1,3 +1,5 @@ +/** @addtogroup msc_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_MSC_H -#define LIBOPENCM3_EFM32_MSC_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define MSC_CTRL MMIO32(MSC_BASE + 0x000) #define MSC_READCTRL MMIO32(MSC_BASE + 0x004) #define MSC_WRITECTRL MMIO32(MSC_BASE + 0x008) @@ -150,5 +153,4 @@ #define MSC_MASSLOCK_LOCKKEY_LOCK MSC_MASSLOCK_LOCKKEY(0) #define MSC_MASSLOCK_LOCKKEY_UNLOCK MSC_MASSLOCK_LOCKKEY(0x631A) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/prs_common.h b/include/libopencm3/efm32/common/prs_common.h index 82fde156..fa8bad1b 100644 --- a/include/libopencm3/efm32/common/prs_common.h +++ b/include/libopencm3/efm32/common/prs_common.h @@ -1,3 +1,5 @@ +/** @addtogroup prs_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_PRS_H -#define LIBOPENCM3_EFM32_PRS_H +#pragma once #include <libopencm3/cm3/common.h> #include <libopencm3/efm32/memorymap.h> +/**@{*/ + #define PRS_SWPULSE MMIO32(PRS_BASE + 0x000) #define PRS_SWLEVEL MMIO32(PRS_BASE + 0x004) #define PRS_ROUTE MMIO32(PRS_BASE + 0x008) @@ -359,5 +362,4 @@ void prs_set_signal(enum prs_ch ch, uint32_t sig); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/rmu_common.h b/include/libopencm3/efm32/common/rmu_common.h index 4a7e721a..96723bb5 100644 --- a/include/libopencm3/efm32/common/rmu_common.h +++ b/include/libopencm3/efm32/common/rmu_common.h @@ -1,3 +1,5 @@ +/** @addtogroup rmu_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_RMU_H -#define LIBOPENCM3_EFM32_RMU_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define RMU_CTRL MMIO32(RMU_BASE + 0x00) #define RMU_RSTCAUSE MMIO32(RMU_BASE + 0x04) #define RMU_CMD MMIO32(RMU_BASE + 0x08) @@ -52,5 +55,4 @@ /* RMU_CMD */ #define RMU_CMD_RCCLR (1 << 0) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/rtc_common.h b/include/libopencm3/efm32/common/rtc_common.h index ad50bcbd..c7eea3e4 100644 --- a/include/libopencm3/efm32/common/rtc_common.h +++ b/include/libopencm3/efm32/common/rtc_common.h @@ -1,3 +1,5 @@ +/** @addtogroup rtc_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_RTC_H -#define LIBOPENCM3_EFM32_RTC_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define RTC_CTRL (RTC_BASE + 0x000) #define RTC_CNT (RTC_BASE + 0x004) #define RTC_COMP0 (RTC_BASE + 0x008) @@ -67,5 +70,4 @@ #define RTC_SYNCBUSY_COMP0 (1 << 1) #define RTC_SYNCBUSY_CTRL (1 << 0) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/timer_common.h b/include/libopencm3/efm32/common/timer_common.h index 4b05d128..a89d2e35 100644 --- a/include/libopencm3/efm32/common/timer_common.h +++ b/include/libopencm3/efm32/common/timer_common.h @@ -1,3 +1,5 @@ +/** @addtogroup timer_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_TIMER_H -#define LIBOPENCM3_EFM32_TIMER_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define TIMER_CTRL(base) MMIO32((base) + 0x000) #define TIMER_CMD(base) MMIO32((base) + 0x004) #define TIMER_STATUS(base) MMIO32((base) + 0x008) @@ -606,5 +609,4 @@ void timer_set_top(uint32_t timer, uint32_t top); END_DECLS -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/uart_common.h b/include/libopencm3/efm32/common/uart_common.h index b69617ba..58b65aac 100644 --- a/include/libopencm3/efm32/common/uart_common.h +++ b/include/libopencm3/efm32/common/uart_common.h @@ -1,3 +1,26 @@ +/** @addtogroup uart_defines + * + * @brief UART registers are mostly equivalent to USART registers. + * + * USART and UART registers are equivalent except [in UART registers]: + * + * * USART_CTRL: SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA + * (Synchronous operation not available) + * * USART_STATUS: MASTEREN (Synchronous operation not available) + * * USART_CTRL: MSBF (transmission LSB first only) + * * USART_CTRL: AUTOCS (chip-select not available) + * * USART_CTRL: SCMODE (SmartCard mode not available) + * * USART_FRAME: DATABITS (limited framesize. 8-9 databits only) + * * USART_IRCTRL: IREN (IrDA not available) + * (except DATABITS, all the above are 0) + * + * full text: (p495, "d0183_Rev1.10" EFM32LG-RM) + * - "18.3 Functional Description", + * - "18.4 Register Description" + * - "18.5 Register Map" + * + * use USART macro's to manipulate UART registers. + */ /* * This file is part of the libopencm3 project. * @@ -17,31 +40,12 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_UART_H -#define LIBOPENCM3_EFM32_UART_H +#pragma once -/** - * USART and UART registers are equivalent except [in UART registers]: - * - * USART_CTRL: SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA [1] - * USART_STATUS: MASTEREN [1] - * [1] Synchronous operation not available. - * USART_CTRL: MSBF (transmission LSB first only) - * USART_CTRL: AUTOCS (chip-select not available) - * USART_CTRL: SCMODE (SmartCard mode not available) - * USART_FRAME: DATABITS (limited framsize. 8-9 databits only) - * USART_IRCTRL: IREN (IrDA not available) - * (except DATABITS, all the above are 0) - * - * full text: (p495, "d0183_Rev1.10" EFM32LG-RM) - * - "18.3 Functional Description", - * - "18.4 Register Description" - * - "18.5 Register Map" - * - * use USART macro's to manipulate UART registers. - */ #include <libopencm3/efm32/memorymap.h> -#include <libopencm3/efm32/lg/usart.h> +#include <libopencm3/efm32/usart.h> + +/**@{*/ /* UART0 */ #define UART0 UART0_BASE @@ -97,4 +101,4 @@ #define UART1_INPUT USART_INPUT(UART1) #define UART1_I2SCTRL USART_I2SCTRL(UART1) -#endif +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/usart_common.h b/include/libopencm3/efm32/common/usart_common.h index b3b3f54b..84f88004 100644 --- a/include/libopencm3/efm32/common/usart_common.h +++ b/include/libopencm3/efm32/common/usart_common.h @@ -1,3 +1,5 @@ +/** @addtogroup usart_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_USART_H -#define LIBOPENCM3_EFM32_USART_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define USART_CTRL(base) MMIO32((base) + 0x000) #define USART_FRAME(base) MMIO32((base) + 0x004) #define USART_TRIGCTRL(base) MMIO32((base) + 0x008) @@ -508,5 +511,4 @@ #define USART2_INPUT USART_INPUT(USART2) #define USART2_I2SCTRL USART_I2SCTRL(USART2) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/usb_common.h b/include/libopencm3/efm32/common/usb_common.h index 891edbfb..e4e8e16f 100644 --- a/include/libopencm3/efm32/common/usb_common.h +++ b/include/libopencm3/efm32/common/usb_common.h @@ -1,3 +1,5 @@ +/** @addtogroup usb_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_USB_H -#define LIBOPENCM3_EFM32_USB_H +#pragma once #include <libopencm3/cm3/common.h> #include <libopencm3/usb/usbd.h> +/**@{*/ + #define USB_CTRL MMIO32(USB_BASE + 0x000) #define USB_STATUS MMIO32(USB_BASE + 0x004) #define USB_IF MMIO32(USB_BASE + 0x008) @@ -365,5 +368,4 @@ /* Bits 18:7 - Reserved */ #define USB_DIEP0TSIZ_XFRSIZ_MASK (0x7f << 0) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/wdog_common.h b/include/libopencm3/efm32/common/wdog_common.h index d4dad2da..1168d129 100644 --- a/include/libopencm3/efm32/common/wdog_common.h +++ b/include/libopencm3/efm32/common/wdog_common.h @@ -1,3 +1,5 @@ +/** @addtogroup wdog_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,12 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WDOG_H -#define LIBOPENCM3_EFM32_WDOG_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define WDOG_CTRL MMIO32(WDOG_BASE + 0x000) #define WDOG_CMD MMIO32(WDOG_BASE + 0x004) #define WDOG_SYNCBUSY MMIO32(WDOG_BASE + 0x008) @@ -72,5 +75,4 @@ #define WDOG_SYNCBUSY_CMD (1 << 1) #define WDOG_SYNCBUSY_CTRL (1 << 0) -#endif - +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/common/wdog_common_hglg.h b/include/libopencm3/efm32/common/wdog_common_hglg.h index 4c067184..700c48ba 100644 --- a/include/libopencm3/efm32/common/wdog_common_hglg.h +++ b/include/libopencm3/efm32/common/wdog_common_hglg.h @@ -1,3 +1,5 @@ +/** @addtogroup wdog_defines + */ /* * This file is part of the libopencm3 project. * @@ -17,15 +19,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/** @cond */ -#if defined(LIBOPENCM3_WDOG_H) -/** @endcond */ -#ifndef LIBOPENCM3_EFM32_WDOG_COMMON_HGLG_H -#define LIBOPENCM3_EFM32_WDOG_COMMON_HGLG_H +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> +/**@{*/ + #define WDOG_CTRL MMIO32(WDOG_BASE + 0x000) #define WDOG_CMD MMIO32(WDOG_BASE + 0x004) #define WDOG_SYNCBUSY MMIO32(WDOG_BASE + 0x008) @@ -75,9 +75,4 @@ #define WDOG_SYNCBUSY_CMD (1 << 1) #define WDOG_SYNCBUSY_CTRL (1 << 0) -#endif -/** @cond */ -#else -#warning "wdog_common_hglg.h should not be included explicitly, only via wdog.h" -#endif -/** @endcond */ +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/ezr32wg/acmp.h b/include/libopencm3/efm32/ezr32wg/acmp.h index c0c2b639..668eca59 100644 --- a/include/libopencm3/efm32/ezr32wg/acmp.h +++ b/include/libopencm3/efm32/ezr32wg/acmp.h @@ -1,3 +1,11 @@ +/** @defgroup acmp_defines ACMP Defines + * + * @brief <b>Defined Constants and Types for the Analog Comparator module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_ACMP_H -#define LIBOPENCM3_EFM32_EZR32WG_ACMP_H +#pragma once #include <libopencm3/efm32/common/acmp_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/adc.h b/include/libopencm3/efm32/ezr32wg/adc.h index f06b9492..16269311 100644 --- a/include/libopencm3/efm32/ezr32wg/adc.h +++ b/include/libopencm3/efm32/ezr32wg/adc.h @@ -1,3 +1,12 @@ +/** @defgroup adc_defines ADC Defines + * + * @brief <b>Defined Constants and Types for the EZR32WG Analog to Digital + * Converter</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +26,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_ADC_H -#define LIBOPENCM3_EFM32_EZR32WG_ADC_H +#pragma once #include <libopencm3/efm32/common/adc_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/burtc.h b/include/libopencm3/efm32/ezr32wg/burtc.h index b96789d2..3f5c55a5 100644 --- a/include/libopencm3/efm32/ezr32wg/burtc.h +++ b/include/libopencm3/efm32/ezr32wg/burtc.h @@ -1,3 +1,11 @@ +/** @defgroup burtc_defines BURTC Defines + * + * @brief <b>Defined Constants and Types for the Backup RTC</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_BURTC_H -#define LIBOPENCM3_EFM32_EZR32WG_BURTC_H +#pragma once #include <libopencm3/efm32/common/burtc_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/cmu.h b/include/libopencm3/efm32/ezr32wg/cmu.h index f292ab4f..dd293404 100644 --- a/include/libopencm3/efm32/ezr32wg/cmu.h +++ b/include/libopencm3/efm32/ezr32wg/cmu.h @@ -1,3 +1,11 @@ +/** @defgroup cmu_defines CMU Defines + * + * @brief <b>Defined Constants and Types for the EZR32WG Clock Management Unit</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,11 +25,12 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_CMU_H -#define LIBOPENCM3_EFM32_EZR32WG_CMU_H +#pragma once #include <libopencm3/efm32/common/cmu_common.h> +/**@{*/ + /* EZR32WG refers to USART0 as USART0RF * because it is connected to the radio MCU. */ @@ -29,4 +38,4 @@ #define CMU_HFPERCLKEN0_USARTRF0 CMU_HFPERCLKEN0_USART0 #define CMU_USARTRF0 CMU_USART0 -#endif +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/ezr32wg/dac.h b/include/libopencm3/efm32/ezr32wg/dac.h index aba83df2..8624e638 100644 --- a/include/libopencm3/efm32/ezr32wg/dac.h +++ b/include/libopencm3/efm32/ezr32wg/dac.h @@ -1,3 +1,11 @@ +/** @defgroup dac_defines DAC Defines + * + * @brief <b>Defined Constants and Types for the D/A Converter module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_DAC_H -#define LIBOPENCM3_EFM32_EZR32WG_DAC_H +#pragma once #include <libopencm3/efm32/common/dac_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/dma.h b/include/libopencm3/efm32/ezr32wg/dma.h index 4f47a448..4697186e 100644 --- a/include/libopencm3/efm32/ezr32wg/dma.h +++ b/include/libopencm3/efm32/ezr32wg/dma.h @@ -1,3 +1,11 @@ +/** @defgroup dma_defines DMA Defines + * + * @brief <b>Defined Constants and Types for the DMA module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_DMA_H -#define LIBOPENCM3_EFM32_EZR32WG_DMA_H +#pragma once #include <libopencm3/efm32/common/dma_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h b/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h index 3adbefa2..89075933 100644 --- a/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h +++ b/include/libopencm3/efm32/ezr32wg/doc-ezr32wg.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Wonder Gecko +/** @page libopencm3 EZR32 Wonder Gecko @version 1.0.0 @@ -19,7 +19,11 @@ Libraries for Silicon Laboratories EZR32 Wonder Gecko series. LGPL License Terms @ref lgpl_license */ -/** @defgroup EZR32LG_defines EZR32 Wonder Gecko Defines +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + +/** @defgroup EZR32WG_defines EZR32 Wonder Gecko Defines @brief Defined Constants and Types for the Silicon Laboratories EZR32 Wonder Gecko series diff --git a/include/libopencm3/efm32/ezr32wg/emu.h b/include/libopencm3/efm32/ezr32wg/emu.h index 054a748a..d0e532c2 100644 --- a/include/libopencm3/efm32/ezr32wg/emu.h +++ b/include/libopencm3/efm32/ezr32wg/emu.h @@ -1,3 +1,11 @@ +/** @defgroup emu_defines EMU Defines + * + * @brief <b>Defined Constants and Types for the Energy Management Unit</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_EMU_H -#define LIBOPENCM3_EFM32_EZR32WG_EMU_H +#pragma once #include <libopencm3/efm32/common/emu_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/gpio.h b/include/libopencm3/efm32/ezr32wg/gpio.h index 21cc6630..8332c851 100644 --- a/include/libopencm3/efm32/ezr32wg/gpio.h +++ b/include/libopencm3/efm32/ezr32wg/gpio.h @@ -1,3 +1,11 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief <b>Defined Constants and Types for the EZR32WG GPIO module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_GPIO_H -#define LIBOPENCM3_EFM32_EZR32WG_GPIO_H +#pragma once #include <libopencm3/efm32/common/gpio_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/i2c.h b/include/libopencm3/efm32/ezr32wg/i2c.h index e8a3a9c8..50ea556c 100644 --- a/include/libopencm3/efm32/ezr32wg/i2c.h +++ b/include/libopencm3/efm32/ezr32wg/i2c.h @@ -1,3 +1,11 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief <b>Defined Constants and Types for the I²C module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_I2C_H -#define LIBOPENCM3_EFM32_EZR32WG_I2C_H +#pragma once #include <libopencm3/efm32/common/i2c_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/letimer.h b/include/libopencm3/efm32/ezr32wg/letimer.h index 6fbfbc7f..dc8d4fd3 100644 --- a/include/libopencm3/efm32/ezr32wg/letimer.h +++ b/include/libopencm3/efm32/ezr32wg/letimer.h @@ -1,3 +1,11 @@ +/** @defgroup letimer_defines LETIMER Defines + * + * @brief <b>Defined Constants and Types for the Low Energy Timer</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_LETIMER_H -#define LIBOPENCM3_EFM32_EZR32WG_LETIMER_H +#pragma once #include <libopencm3/efm32/common/letimer_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/msc.h b/include/libopencm3/efm32/ezr32wg/msc.h index b8800ea8..2f8dd32a 100644 --- a/include/libopencm3/efm32/ezr32wg/msc.h +++ b/include/libopencm3/efm32/ezr32wg/msc.h @@ -1,3 +1,11 @@ +/** @defgroup msc_defines MSC Defines + * + * @brief <b>Defined Constants and Types for the Memory Systems Controller</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_MSC_H -#define LIBOPENCM3_EFM32_EZR32WG_MSC_H +#pragma once #include <libopencm3/efm32/common/msc_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/prs.h b/include/libopencm3/efm32/ezr32wg/prs.h index 6b58af82..6ce36335 100644 --- a/include/libopencm3/efm32/ezr32wg/prs.h +++ b/include/libopencm3/efm32/ezr32wg/prs.h @@ -1,3 +1,11 @@ +/** @defgroup prs_defines PRS Defines + * + * @brief <b>Defined Constants and Types for the Peripheral Reflex System</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_PRS_H -#define LIBOPENCM3_EFM32_EZR32WG_PRS_H +#pragma once #include <libopencm3/efm32/common/prs_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/rmu.h b/include/libopencm3/efm32/ezr32wg/rmu.h index f0eab3a9..cad039e4 100644 --- a/include/libopencm3/efm32/ezr32wg/rmu.h +++ b/include/libopencm3/efm32/ezr32wg/rmu.h @@ -1,3 +1,11 @@ +/** @defgroup rmu_defines RMU Defines + * + * @brief <b>Defined Constants and Types for the Reset Management Unit</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_RMU_H -#define LIBOPENCM3_EFM32_EZR32WG_RMU_H +#pragma once #include <libopencm3/efm32/common/rmu_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/rtc.h b/include/libopencm3/efm32/ezr32wg/rtc.h index 3c96410c..a45a5e72 100644 --- a/include/libopencm3/efm32/ezr32wg/rtc.h +++ b/include/libopencm3/efm32/ezr32wg/rtc.h @@ -1,3 +1,11 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief <b>Defined Constants and Types for the Real Time Clock</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_RTC_H -#define LIBOPENCM3_EFM32_EZR32WG_RTC_H +#pragma once #include <libopencm3/efm32/common/rtc_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/timer.h b/include/libopencm3/efm32/ezr32wg/timer.h index 848d4eaa..439a418e 100644 --- a/include/libopencm3/efm32/ezr32wg/timer.h +++ b/include/libopencm3/efm32/ezr32wg/timer.h @@ -1,3 +1,11 @@ +/** @defgroup timer_defines TIMER Defines + * + * @brief <b>Defined Constants and Types for the TIMER module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_TIMER_H -#define LIBOPENCM3_EFM32_EZR32WG_TIMER_H +#pragma once #include <libopencm3/efm32/common/timer_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/uart.h b/include/libopencm3/efm32/ezr32wg/uart.h index a012581b..6f4bf3e7 100644 --- a/include/libopencm3/efm32/ezr32wg/uart.h +++ b/include/libopencm3/efm32/ezr32wg/uart.h @@ -1,3 +1,11 @@ +/** @defgroup uart_defines UART Defines + * + * @brief <b>Defined Constants and Types for the UART module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_UART_H -#define LIBOPENCM3_EFM32_EZR32WG_UART_H +#pragma once #include <libopencm3/efm32/common/uart_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/usart.h b/include/libopencm3/efm32/ezr32wg/usart.h index 07a80415..5db0aae2 100644 --- a/include/libopencm3/efm32/ezr32wg/usart.h +++ b/include/libopencm3/efm32/ezr32wg/usart.h @@ -1,3 +1,11 @@ +/** @defgroup usart_defines USART Defines + * + * @brief <b>Defined Constants and Types for the USART module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_USART_H -#define LIBOPENCM3_EFM32_EZR32WG_USART_H +#pragma once #include <libopencm3/efm32/common/usart_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/usb.h b/include/libopencm3/efm32/ezr32wg/usb.h index 87be3234..2d980899 100644 --- a/include/libopencm3/efm32/ezr32wg/usb.h +++ b/include/libopencm3/efm32/ezr32wg/usb.h @@ -1,3 +1,11 @@ +/** @defgroup usb_defines USB Defines + * + * @brief <b>Defined Constants and Types for the USB module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_USB_H -#define LIBOPENCM3_EFM32_EZR32WG_USB_H +#pragma once #include <libopencm3/efm32/common/usb_common.h> - -#endif diff --git a/include/libopencm3/efm32/ezr32wg/wdog.h b/include/libopencm3/efm32/ezr32wg/wdog.h index 0446680c..e2c7fd93 100644 --- a/include/libopencm3/efm32/ezr32wg/wdog.h +++ b/include/libopencm3/efm32/ezr32wg/wdog.h @@ -1,3 +1,11 @@ +/** @defgroup wdog_defines WDOG Defines + * + * @brief <b>Defined Constants and Types for the Watchdog module</b> + * + * @ingroup EZR32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_EZR32WG_WDOG_H -#define LIBOPENCM3_EFM32_EZR32WG_WDOG_H +#pragma once #include <libopencm3/efm32/common/wdog_common.h> - -#endif diff --git a/include/libopencm3/efm32/g/doc-efm32g.h b/include/libopencm3/efm32/g/doc-efm32g.h index 747cb514..6630450d 100644 --- a/include/libopencm3/efm32/g/doc-efm32g.h +++ b/include/libopencm3/efm32/g/doc-efm32g.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Gecko +/** @page libopencm3 EFM32 Gecko @version 1.0.0 @@ -19,6 +19,10 @@ Libraries for Energy Micro EFM32 Gecko series. LGPL License Terms @ref lgpl_license */ +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + /** @defgroup EFM32G_defines EFM32 Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Gecko series diff --git a/include/libopencm3/efm32/gg/doc-efm32gg.h b/include/libopencm3/efm32/gg/doc-efm32gg.h index aacb17bc..14666774 100644 --- a/include/libopencm3/efm32/gg/doc-efm32gg.h +++ b/include/libopencm3/efm32/gg/doc-efm32gg.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Giant Gecko +/** @page libopencm3 EFM32 Giant Gecko @version 1.0.0 @@ -19,6 +19,10 @@ Libraries for Energy Micro EFM32 Giant Gecko series. LGPL License Terms @ref lgpl_license */ +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + /** @defgroup EFM32GG_defines EFM32 Giant Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Giant Gecko series diff --git a/include/libopencm3/efm32/hg/cmu.h b/include/libopencm3/efm32/hg/cmu.h index 5266af94..6d513bf8 100644 --- a/include/libopencm3/efm32/hg/cmu.h +++ b/include/libopencm3/efm32/hg/cmu.h @@ -1,3 +1,11 @@ +/** @defgroup cmu_defines CMU Defines + * + * @brief <b>Defined Constants and Types for the EFM32HG Clock Management Unit</b> + * + * @ingroup EFM32HG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -18,8 +26,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_CMU_H -#define LIBOPENCM3_EFM32_CMU_H +/**@{*/ + +#pragma once #include <libopencm3/efm32/memorymap.h> #include <libopencm3/cm3/common.h> @@ -352,6 +361,7 @@ #define CMU_CMD_HFCLKSEL_HFXO CMU_CMD_HFCLKSEL(2) #define CMU_CMD_HFCLKSEL_LFRCO CMU_CMD_HFCLKSEL(3) #define CMU_CMD_HFCLKSEL_LFXO CMU_CMD_HFCLKSEL(4) +#define CMU_CMD_HFCLKSEL_USHFRCODIV2 CMU_CMD_HFCLKSEL(5) /* CMU_LFCLKSEL */ /* Bits 31:21 - Reserved */ @@ -633,6 +643,7 @@ enum cmu_osc { LFXO, /**< External, 32.768kHz */ AUXHFRCO, /**< Internal, 1-28Mhz */ USHFRCO, /**< Internal, 48MHz */ + USHFRCODIV2, /**< Internal, 24MHz */ }; /* --- Function prototypes ------------------------------------------------- */ @@ -671,4 +682,4 @@ void cmu_wait_for_usbclk_selected(enum cmu_osc osc); END_DECLS -#endif +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/hg/doc-efm32hg.h b/include/libopencm3/efm32/hg/doc-efm32hg.h index c7f13c3b..e3de840c 100644 --- a/include/libopencm3/efm32/hg/doc-efm32hg.h +++ b/include/libopencm3/efm32/hg/doc-efm32hg.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Happy Gecko +/** @page libopencm3 EFM32 Happy Gecko @version 1.0.0 @@ -9,7 +9,7 @@ API documentation for Energy Micro EFM32 Happy Gecko Cortex M0+ series. LGPL License Terms @ref lgpl_license */ -/** @defgroup EFM32LG EFM32 HappyGecko +/** @defgroup EFM32HG EFM32 HappyGecko Libraries for Energy Micro EFM32 Happy Gecko series. @version 1.0.0 @@ -19,6 +19,10 @@ Libraries for Energy Micro EFM32 Happy Gecko series. LGPL License Terms @ref lgpl_license */ +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + /** @defgroup EFM32HG_defines EFM32 Happy Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Happy Gecko diff --git a/include/libopencm3/efm32/hg/gpio.h b/include/libopencm3/efm32/hg/gpio.h index 5218af66..5be1565e 100644 --- a/include/libopencm3/efm32/hg/gpio.h +++ b/include/libopencm3/efm32/hg/gpio.h @@ -1,3 +1,11 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief <b>Defined Constants and Types for the EFM32HG GPIO module</b> + * + * @ingroup EFM32HG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -15,9 +23,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H +#pragma once #include <libopencm3/efm32/common/gpio_common_hglg.h> - -#endif diff --git a/include/libopencm3/efm32/hg/timer.h b/include/libopencm3/efm32/hg/timer.h index 647abe85..9d88c2e2 100644 --- a/include/libopencm3/efm32/hg/timer.h +++ b/include/libopencm3/efm32/hg/timer.h @@ -1,3 +1,11 @@ +/** @defgroup timer_defines TIMER Defines + * + * @brief <b>Defined Constants and Types for the TIMER module</b> + * + * @ingroup EFM32HG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -15,8 +23,7 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H +#pragma once #include <libopencm3/efm32/common/timer_common.h> @@ -27,5 +34,3 @@ /* TIMER_CCx_CTRL */ #define TIMER_CC_CTRL_PRSCONF (1 << 28) - -#endif diff --git a/include/libopencm3/efm32/hg/usb.h b/include/libopencm3/efm32/hg/usb.h index f4096c27..b3b45baa 100644 --- a/include/libopencm3/efm32/hg/usb.h +++ b/include/libopencm3/efm32/hg/usb.h @@ -1,3 +1,11 @@ +/** @defgroup usb_defines USB Defines + * + * @brief <b>Defined Constants and Types for the USB module</b> + * + * @ingroup EFM32HG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -18,12 +26,13 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_USB_H -#define LIBOPENCM3_EFM32_USB_H +#pragma once #include <libopencm3/cm3/common.h> #include <libopencm3/usb/dwc/otg_fs.h> +/**@{*/ + #define USB_CTRL MMIO32(USB_BASE + 0x000) #define USB_STATUS MMIO32(USB_BASE + 0x004) #define USB_IF MMIO32(USB_BASE + 0x008) @@ -58,4 +67,4 @@ /* Bit 1 - Reserved */ #define USB_ROUTE_PHYPEN (1 << 0) -#endif +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/efm32/hg/wdog.h b/include/libopencm3/efm32/hg/wdog.h index 2eb8a478..949896b7 100644 --- a/include/libopencm3/efm32/hg/wdog.h +++ b/include/libopencm3/efm32/hg/wdog.h @@ -1,3 +1,11 @@ +/** @defgroup wdog_defines WDOG Defines + * + * @brief <b>Defined Constants and Types for the Watchdog module</b> + * + * @ingroup EFM32HG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -15,9 +23,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_WDOG_H -#define LIBOPENCM3_WDOG_H +#pragma once #include <libopencm3/efm32/common/wdog_common_hglg.h> - -#endif diff --git a/include/libopencm3/efm32/lg/acmp.h b/include/libopencm3/efm32/lg/acmp.h index 0df98c94..7b961299 100644 --- a/include/libopencm3/efm32/lg/acmp.h +++ b/include/libopencm3/efm32/lg/acmp.h @@ -1,3 +1,11 @@ +/** @defgroup acmp_defines ACMP Defines + * + * @brief <b>Defined Constants and Types for the Analog Comparator module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_ACMP_H -#define LIBOPENCM3_EFM32_LG_ACMP_H +#pragma once #include <libopencm3/efm32/common/acmp_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/adc.h b/include/libopencm3/efm32/lg/adc.h index 5432ce64..3e8d4f5e 100644 --- a/include/libopencm3/efm32/lg/adc.h +++ b/include/libopencm3/efm32/lg/adc.h @@ -1,3 +1,12 @@ +/** @defgroup adc_defines ADC Defines + * + * @brief <b>Defined Constants and Types for the EFM32LG Analog to Digital + * Converter</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +26,7 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_ADC_H -#define LIBOPENCM3_EFM32_LG_ADC_H +#pragma once #include <libopencm3/efm32/common/adc_common.h> -#endif diff --git a/include/libopencm3/efm32/lg/burtc.h b/include/libopencm3/efm32/lg/burtc.h index 132c3d02..fa580335 100644 --- a/include/libopencm3/efm32/lg/burtc.h +++ b/include/libopencm3/efm32/lg/burtc.h @@ -1,3 +1,11 @@ +/** @defgroup burtc_defines BURTC Defines + * + * @brief <b>Defined Constants and Types for the Backup RTC</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_BURTC_H -#define LIBOPENCM3_EFM32_LG_BURTC_H +#pragma once #include <libopencm3/efm32/common/burtc_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/cmu.h b/include/libopencm3/efm32/lg/cmu.h index a567a30c..93168705 100644 --- a/include/libopencm3/efm32/lg/cmu.h +++ b/include/libopencm3/efm32/lg/cmu.h @@ -1,3 +1,11 @@ +/** @defgroup cmu_defines CMU Defines + * + * @brief <b>Defined Constants and Types for the EFM32LG Clock Management Unit</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,10 +25,7 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_CMU_H -#define LIBOPENCM3_EFM32_LG_CMU_H +#pragma once #include <libopencm3/efm32/common/cmu_common.h> -#endif - diff --git a/include/libopencm3/efm32/lg/dac.h b/include/libopencm3/efm32/lg/dac.h index 5ad9dfe0..3611a248 100644 --- a/include/libopencm3/efm32/lg/dac.h +++ b/include/libopencm3/efm32/lg/dac.h @@ -1,3 +1,11 @@ +/** @defgroup dac_defines DAC Defines + * + * @brief <b>Defined Constants and Types for the D/A Converter module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_DAC_H -#define LIBOPENCM3_EFM32_LG_DAC_H +#pragma once #include <libopencm3/efm32/common/dac_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/dma.h b/include/libopencm3/efm32/lg/dma.h index f32149a1..57d4ddd0 100644 --- a/include/libopencm3/efm32/lg/dma.h +++ b/include/libopencm3/efm32/lg/dma.h @@ -1,3 +1,11 @@ +/** @defgroup dma_defines DMA Defines + * + * @brief <b>Defined Constants and Types for the DMA module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_DMA_H -#define LIBOPENCM3_EFM32_LG_DMA_H +#pragma once #include <libopencm3/efm32/common/dma_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/doc-efm32lg.h b/include/libopencm3/efm32/lg/doc-efm32lg.h index 7721239f..93f39ed9 100644 --- a/include/libopencm3/efm32/lg/doc-efm32lg.h +++ b/include/libopencm3/efm32/lg/doc-efm32lg.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Leopard Gecko +/** @page libopencm3 EFM32 Leopard Gecko @version 1.0.0 @@ -19,6 +19,10 @@ Libraries for Energy Micro EFM32 Leopard Gecko series. LGPL License Terms @ref lgpl_license */ +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + /** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko diff --git a/include/libopencm3/efm32/lg/emu.h b/include/libopencm3/efm32/lg/emu.h index d104663b..92b350c0 100644 --- a/include/libopencm3/efm32/lg/emu.h +++ b/include/libopencm3/efm32/lg/emu.h @@ -1,3 +1,11 @@ +/** @defgroup emu_defines EMU Defines + * + * @brief <b>Defined Constants and Types for the Energy Management Unit</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_EMU_H -#define LIBOPENCM3_EFM32_LG_EMU_H +#pragma once #include <libopencm3/efm32/common/emu_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/gpio.h b/include/libopencm3/efm32/lg/gpio.h index 71bd54f6..f0684bac 100644 --- a/include/libopencm3/efm32/lg/gpio.h +++ b/include/libopencm3/efm32/lg/gpio.h @@ -1,3 +1,11 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief <b>Defined Constants and Types for the EFM32LG GPIO module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -15,9 +23,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_GPIO_H -#define LIBOPENCM3_GPIO_H +#pragma once #include <libopencm3/efm32/common/gpio_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/i2c.h b/include/libopencm3/efm32/lg/i2c.h index 6d34803d..9ff55f9f 100644 --- a/include/libopencm3/efm32/lg/i2c.h +++ b/include/libopencm3/efm32/lg/i2c.h @@ -1,3 +1,11 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief <b>Defined Constants and Types for the I²C module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_I2C_H -#define LIBOPENCM3_EFM32_LG_I2C_H +#pragma once #include <libopencm3/efm32/common/i2c_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/letimer.h b/include/libopencm3/efm32/lg/letimer.h index 40c283f4..9a12151d 100644 --- a/include/libopencm3/efm32/lg/letimer.h +++ b/include/libopencm3/efm32/lg/letimer.h @@ -1,3 +1,11 @@ +/** @defgroup letimer_defines LETIMER Defines + * + * @brief <b>Defined Constants and Types for the Low Energy Timer</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_LETIMER_H -#define LIBOPENCM3_EFM32_LG_LETIMER_H +#pragma once #include <libopencm3/efm32/common/letimer_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/msc.h b/include/libopencm3/efm32/lg/msc.h index 83b99fdf..f4fed2b7 100644 --- a/include/libopencm3/efm32/lg/msc.h +++ b/include/libopencm3/efm32/lg/msc.h @@ -1,3 +1,11 @@ +/** @defgroup msc_defines MSC Defines + * + * @brief <b>Defined Constants and Types for the Memory Systems Controller</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_MSC_H -#define LIBOPENCM3_EFM32_LG_MSC_H +#pragma once #include <libopencm3/efm32/common/msc_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/prs.h b/include/libopencm3/efm32/lg/prs.h index a2469457..e059892e 100644 --- a/include/libopencm3/efm32/lg/prs.h +++ b/include/libopencm3/efm32/lg/prs.h @@ -1,3 +1,11 @@ +/** @defgroup prs_defines PRS Defines + * + * @brief <b>Defined Constants and Types for the Peripheral Reflex System</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_PRS_H -#define LIBOPENCM3_EFM32_LG_PRS_H +#pragma once #include <libopencm3/efm32/common/prs_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/rmu.h b/include/libopencm3/efm32/lg/rmu.h index 21415073..97c793f7 100644 --- a/include/libopencm3/efm32/lg/rmu.h +++ b/include/libopencm3/efm32/lg/rmu.h @@ -1,3 +1,11 @@ +/** @defgroup rmu_defines RMU Defines + * + * @brief <b>Defined Constants and Types for the Reset Management Unit</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_RMU_H -#define LIBOPENCM3_EFM32_LG_RMU_H +#pragma once #include <libopencm3/efm32/common/rmu_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/rtc.h b/include/libopencm3/efm32/lg/rtc.h index 49b2abaa..0aab324e 100644 --- a/include/libopencm3/efm32/lg/rtc.h +++ b/include/libopencm3/efm32/lg/rtc.h @@ -1,3 +1,11 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief <b>Defined Constants and Types for the Real Time Clock</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_RTC_H -#define LIBOPENCM3_EFM32_LG_RTC_H +#pragma once #include <libopencm3/efm32/common/rtc_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/timer.h b/include/libopencm3/efm32/lg/timer.h index 83c6b20d..aecd0e64 100644 --- a/include/libopencm3/efm32/lg/timer.h +++ b/include/libopencm3/efm32/lg/timer.h @@ -1,3 +1,11 @@ +/** @defgroup timer_defines TIMER Defines + * + * @brief <b>Defined Constants and Types for the TIMER module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -15,9 +23,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_TIMER_H -#define LIBOPENCM3_TIMER_H +#pragma once #include <libopencm3/efm32/common/timer_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/uart.h b/include/libopencm3/efm32/lg/uart.h index 86b493fd..301a0754 100644 --- a/include/libopencm3/efm32/lg/uart.h +++ b/include/libopencm3/efm32/lg/uart.h @@ -1,3 +1,11 @@ +/** @defgroup uart_defines UART Defines + * + * @brief <b>Defined Constants and Types for the UART module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_UART_H -#define LIBOPENCM3_EFM32_LG_UART_H +#pragma once #include <libopencm3/efm32/common/uart_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/usart.h b/include/libopencm3/efm32/lg/usart.h index 41c1ec1a..0a0a5254 100644 --- a/include/libopencm3/efm32/lg/usart.h +++ b/include/libopencm3/efm32/lg/usart.h @@ -1,3 +1,11 @@ +/** @defgroup usart_defines USART Defines + * + * @brief <b>Defined Constants and Types for the USART module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_USART_H -#define LIBOPENCM3_EFM32_LG_USART_H +#pragma once #include <libopencm3/efm32/common/usart_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/usb.h b/include/libopencm3/efm32/lg/usb.h index 1bb0a7b8..8c781b19 100644 --- a/include/libopencm3/efm32/lg/usb.h +++ b/include/libopencm3/efm32/lg/usb.h @@ -1,3 +1,11 @@ +/** @defgroup usb_defines USB Defines + * + * @brief <b>Defined Constants and Types for the USB module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_LG_USB_H -#define LIBOPENCM3_EFM32_LG_USB_H +#pragma once #include <libopencm3/efm32/common/usb_common.h> - -#endif diff --git a/include/libopencm3/efm32/lg/wdog.h b/include/libopencm3/efm32/lg/wdog.h index ea9a4812..ba657c2a 100644 --- a/include/libopencm3/efm32/lg/wdog.h +++ b/include/libopencm3/efm32/lg/wdog.h @@ -1,3 +1,11 @@ +/** @defgroup wdog_defines WDOG Defines + * + * @brief <b>Defined Constants and Types for the Watchdog module</b> + * + * @ingroup EFM32LG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -15,9 +23,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_WDOG_H -#define LIBOPENCM3_WDOG_H +#pragma once #include <libopencm3/efm32/common/wdog_common.h> - -#endif diff --git a/include/libopencm3/efm32/tg/doc-efm32tg.h b/include/libopencm3/efm32/tg/doc-efm32tg.h index 799048cd..722cc567 100644 --- a/include/libopencm3/efm32/tg/doc-efm32tg.h +++ b/include/libopencm3/efm32/tg/doc-efm32tg.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Tiny Gecko +/** @page libopencm3 EFM32 Tiny Gecko @version 1.0.0 @@ -19,6 +19,10 @@ Libraries for Energy Micro EFM32 Tiny Gecko series. LGPL License Terms @ref lgpl_license */ +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + /** @defgroup EFM32TG_defines EFM32 Tiny Gecko Defines @brief Defined Constants and Types for the Energy Micro EFM32 Tiny Gecko series diff --git a/include/libopencm3/efm32/wg/acmp.h b/include/libopencm3/efm32/wg/acmp.h index 4a468c89..6a4c10b5 100644 --- a/include/libopencm3/efm32/wg/acmp.h +++ b/include/libopencm3/efm32/wg/acmp.h @@ -1,3 +1,11 @@ +/** @defgroup acmp_defines ACMP Defines + * + * @brief <b>Defined Constants and Types for the Analog Comparator module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_ACMP_H -#define LIBOPENCM3_EFM32_WG_ACMP_H +#pragma once #include <libopencm3/efm32/common/acmp_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/adc.h b/include/libopencm3/efm32/wg/adc.h index 3d6e07f3..bdfadc37 100644 --- a/include/libopencm3/efm32/wg/adc.h +++ b/include/libopencm3/efm32/wg/adc.h @@ -1,3 +1,12 @@ +/** @defgroup adc_defines ADC Defines + * + * @brief <b>Defined Constants and Types for the EFM32WG Analog to Digital + * Converter</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +26,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_ADC_H -#define LIBOPENCM3_EFM32_WG_ADC_H +#pragma once #include <libopencm3/efm32/common/adc_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/burtc.h b/include/libopencm3/efm32/wg/burtc.h index 9246ea03..28e605ad 100644 --- a/include/libopencm3/efm32/wg/burtc.h +++ b/include/libopencm3/efm32/wg/burtc.h @@ -1,3 +1,11 @@ +/** @defgroup burtc_defines BURTC Defines + * + * @brief <b>Defined Constants and Types for the Backup RTC</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_BURTC_H -#define LIBOPENCM3_EFM32_WG_BURTC_H +#pragma once #include <libopencm3/efm32/common/burtc_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/cmu.h b/include/libopencm3/efm32/wg/cmu.h index 17701412..6b6b86c7 100644 --- a/include/libopencm3/efm32/wg/cmu.h +++ b/include/libopencm3/efm32/wg/cmu.h @@ -1,3 +1,11 @@ +/** @defgroup cmu_defines CMU Defines + * + * @brief <b>Defined Constants and Types for the EFM32WG Clock Management Unit</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_CMU_H -#define LIBOPENCM3_EFM32_WG_CMU_H +#pragma once #include <libopencm3/efm32/common/cmu_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/dac.h b/include/libopencm3/efm32/wg/dac.h index 5285c3ce..87538bf0 100644 --- a/include/libopencm3/efm32/wg/dac.h +++ b/include/libopencm3/efm32/wg/dac.h @@ -1,3 +1,11 @@ +/** @defgroup dac_defines DAC Defines + * + * @brief <b>Defined Constants and Types for the D/A Converter module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_DAC_H -#define LIBOPENCM3_EFM32_WG_DAC_H +#pragma once #include <libopencm3/efm32/common/dac_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/dma.h b/include/libopencm3/efm32/wg/dma.h index cb4e9fa4..803273f9 100644 --- a/include/libopencm3/efm32/wg/dma.h +++ b/include/libopencm3/efm32/wg/dma.h @@ -1,3 +1,11 @@ +/** @defgroup dma_defines DMA Defines + * + * @brief <b>Defined Constants and Types for the DMA module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_DMA_H -#define LIBOPENCM3_EFM32_WG_DMA_H +#pragma once #include <libopencm3/efm32/common/dma_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/doc-efm32wg.h b/include/libopencm3/efm32/wg/doc-efm32wg.h index 741b8b77..4f8b105f 100644 --- a/include/libopencm3/efm32/wg/doc-efm32wg.h +++ b/include/libopencm3/efm32/wg/doc-efm32wg.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 EFM32 Wonder Gecko +/** @page libopencm3 EFM32 Wonder Gecko @version 1.0.0 @@ -9,7 +9,7 @@ API documentation for Silicon Laboratories EFM32 Wonder Gecko Cortex M4 series. LGPL License Terms @ref lgpl_license */ -/** @defgroup EFM32WG EFM32 WonderGecko +/** @defgroup EFM32WG EFM32 Wonder Gecko Libraries for Silicon Laboratories EFM32 Wonder Gecko series. @version 1.0.0 @@ -19,7 +19,11 @@ Libraries for Silicon Laboratories EFM32 Wonder Gecko series. LGPL License Terms @ref lgpl_license */ -/** @defgroup EFM32LG_defines EFM32 Wonder Gecko Defines +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + +/** @defgroup EFM32WG_defines EFM32 Wonder Gecko Defines @brief Defined Constants and Types for the Silicon Laboratories EFM32 Wonder Gecko series diff --git a/include/libopencm3/efm32/wg/emu.h b/include/libopencm3/efm32/wg/emu.h index a1a6d318..11f38c41 100644 --- a/include/libopencm3/efm32/wg/emu.h +++ b/include/libopencm3/efm32/wg/emu.h @@ -1,3 +1,11 @@ +/** @defgroup emu_defines EMU Defines + * + * @brief <b>Defined Constants and Types for the Energy Management Unit</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_EMU_H -#define LIBOPENCM3_EFM32_WG_EMU_H +#pragma once #include <libopencm3/efm32/common/emu_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/gpio.h b/include/libopencm3/efm32/wg/gpio.h index 6bd8eb9b..7dafd830 100644 --- a/include/libopencm3/efm32/wg/gpio.h +++ b/include/libopencm3/efm32/wg/gpio.h @@ -1,3 +1,11 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief <b>Defined Constants and Types for the EFM32WG GPIO module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_GPIO_H -#define LIBOPENCM3_EFM32_WG_GPIO_H +#pragma once #include <libopencm3/efm32/common/gpio_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/i2c.h b/include/libopencm3/efm32/wg/i2c.h index 0c40f10e..c137f885 100644 --- a/include/libopencm3/efm32/wg/i2c.h +++ b/include/libopencm3/efm32/wg/i2c.h @@ -1,3 +1,11 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief <b>Defined Constants and Types for the I²C module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_I2C_H -#define LIBOPENCM3_EFM32_WG_I2C_H +#pragma once #include <libopencm3/efm32/common/i2c_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/letimer.h b/include/libopencm3/efm32/wg/letimer.h index 674b2fe4..ee7473a3 100644 --- a/include/libopencm3/efm32/wg/letimer.h +++ b/include/libopencm3/efm32/wg/letimer.h @@ -1,3 +1,11 @@ +/** @defgroup letimer_defines LETIMER Defines + * + * @brief <b>Defined Constants and Types for the Low Energy Timer</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_LETIMER_H -#define LIBOPENCM3_EFM32_WG_LETIMER_H +#pragma once #include <libopencm3/efm32/common/letimer_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/msc.h b/include/libopencm3/efm32/wg/msc.h index e4324682..bc33ac43 100644 --- a/include/libopencm3/efm32/wg/msc.h +++ b/include/libopencm3/efm32/wg/msc.h @@ -1,3 +1,11 @@ +/** @defgroup msc_defines MSC Defines + * + * @brief <b>Defined Constants and Types for the Memory Systems Controller</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_MSC_H -#define LIBOPENCM3_EFM32_WG_MSC_H +#pragma once #include <libopencm3/efm32/common/msc_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/prs.h b/include/libopencm3/efm32/wg/prs.h index 2df0410d..42afc138 100644 --- a/include/libopencm3/efm32/wg/prs.h +++ b/include/libopencm3/efm32/wg/prs.h @@ -1,3 +1,11 @@ +/** @defgroup prs_defines PRS Defines + * + * @brief <b>Defined Constants and Types for the Peripheral Reflex System</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_PRS_H -#define LIBOPENCM3_EFM32_WG_PRS_H +#pragma once #include <libopencm3/efm32/common/prs_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/rmu.h b/include/libopencm3/efm32/wg/rmu.h index d2ba356b..9cc75419 100644 --- a/include/libopencm3/efm32/wg/rmu.h +++ b/include/libopencm3/efm32/wg/rmu.h @@ -1,3 +1,11 @@ +/** @defgroup rmu_defines RMU Defines + * + * @brief <b>Defined Constants and Types for the Reset Management Unit</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_RMU_H -#define LIBOPENCM3_EFM32_WG_RMU_H +#pragma once #include <libopencm3/efm32/common/rmu_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/rtc.h b/include/libopencm3/efm32/wg/rtc.h index 39c2ff0e..e2a85a66 100644 --- a/include/libopencm3/efm32/wg/rtc.h +++ b/include/libopencm3/efm32/wg/rtc.h @@ -1,3 +1,11 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief <b>Defined Constants and Types for the Real Time Clock</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_RTC_H -#define LIBOPENCM3_EFM32_WG_RTC_H +#pragma once #include <libopencm3/efm32/common/rtc_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/timer.h b/include/libopencm3/efm32/wg/timer.h index fc51e77d..9d0a1cd1 100644 --- a/include/libopencm3/efm32/wg/timer.h +++ b/include/libopencm3/efm32/wg/timer.h @@ -1,3 +1,11 @@ +/** @defgroup timer_defines TIMER Defines + * + * @brief <b>Defined Constants and Types for the TIMER module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_TIMER_H -#define LIBOPENCM3_EFM32_WG_TIMER_H +#pragma once #include <libopencm3/efm32/common/timer_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/uart.h b/include/libopencm3/efm32/wg/uart.h index 52c79f7b..b79d8c89 100644 --- a/include/libopencm3/efm32/wg/uart.h +++ b/include/libopencm3/efm32/wg/uart.h @@ -1,3 +1,11 @@ +/** @defgroup uart_defines UART Defines + * + * @brief <b>Defined Constants and Types for the UART module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_UART_H -#define LIBOPENCM3_EFM32_WG_UART_H +#pragma once #include <libopencm3/efm32/common/uart_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/usart.h b/include/libopencm3/efm32/wg/usart.h index 149842d7..edba183d 100644 --- a/include/libopencm3/efm32/wg/usart.h +++ b/include/libopencm3/efm32/wg/usart.h @@ -1,3 +1,11 @@ +/** @defgroup usart_defines USART Defines + * + * @brief <b>Defined Constants and Types for the USART module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_USART_H -#define LIBOPENCM3_EFM32_WG_USART_H +#pragma once #include <libopencm3/efm32/common/usart_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/usb.h b/include/libopencm3/efm32/wg/usb.h index 49edde04..cc066731 100644 --- a/include/libopencm3/efm32/wg/usb.h +++ b/include/libopencm3/efm32/wg/usb.h @@ -1,3 +1,11 @@ +/** @defgroup usb_defines USB Defines + * + * @brief <b>Defined Constants and Types for the USB module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_USB_H -#define LIBOPENCM3_EFM32_WG_USB_H +#pragma once #include <libopencm3/efm32/common/usb_common.h> - -#endif diff --git a/include/libopencm3/efm32/wg/wdog.h b/include/libopencm3/efm32/wg/wdog.h index bec00e9d..9f32353c 100644 --- a/include/libopencm3/efm32/wg/wdog.h +++ b/include/libopencm3/efm32/wg/wdog.h @@ -1,3 +1,11 @@ +/** @defgroup wdog_defines WDOG Defines + * + * @brief <b>Defined Constants and Types for the Watchdog module</b> + * + * @ingroup EFM32WG_defines + * + * LGPL License Terms @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -17,9 +25,6 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#ifndef LIBOPENCM3_EFM32_WG_WDOG_H -#define LIBOPENCM3_EFM32_WG_WDOG_H +#pragma once #include <libopencm3/efm32/common/wdog_common.h> - -#endif diff --git a/include/libopencm3/ethernet/mac.h b/include/libopencm3/ethernet/mac.h index b047e4db..b7887068 100644 --- a/include/libopencm3/ethernet/mac.h +++ b/include/libopencm3/ethernet/mac.h @@ -37,6 +37,8 @@ # include <libopencm3/ethernet/mac_stm32fxx7.h> #elif defined(STM32F4) # include <libopencm3/ethernet/mac_stm32fxx7.h> +#elif defined(STM32F7) +# include <libopencm3/ethernet/mac_stm32fxx7.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/gd32/f1x0/doc-gd32f1x0.h b/include/libopencm3/gd32/f1x0/doc-gd32f1x0.h new file mode 100644 index 00000000..ffbeaa65 --- /dev/null +++ b/include/libopencm3/gd32/f1x0/doc-gd32f1x0.h @@ -0,0 +1,30 @@ +/** @page libopencm3 GD32F1x0 + +@version 1.0.0 + +API documentation for GigaDevices GD32F1x0 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + +/** @defgroup GD32F1x0 GD32F1x0xx +Libraries for GigaDevices GD32F1x0xx series. + +@version 1.0.0 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup GD32F1x0_defines GD32F1x0xx Defines + +@brief Defined Constants and Types for the GD32F1x0xx series + +@version 1.0.0 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/gd32/f1x0/flash.h b/include/libopencm3/gd32/f1x0/flash.h new file mode 100644 index 00000000..e59d27fc --- /dev/null +++ b/include/libopencm3/gd32/f1x0/flash.h @@ -0,0 +1,103 @@ +/** @defgroup flash_defines FLASH Defines + * + * @brief <b>Defined Constants and Types for the GD32F1x0 Flash memory</b> + * + * @ingroup GD32F1x0_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian <BuFran@seznam.cz> + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H +/**@{*/ + +#include <libopencm3/stm32/common/flash_common_all.h> +#include <libopencm3/stm32/common/flash_common_f.h> +#include <libopencm3/stm32/common/flash_common_f01.h> + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +/** @defgroup flash_latency FLASH Wait States +@ingroup flash_defines +@{*/ +#define FLASH_ACR_LATENCY_000_024MHZ 0 +#define FLASH_ACR_LATENCY_024_048MHZ 1 +#define FLASH_ACR_LATENCY_048_072MHZ 2 +#define FLASH_ACR_LATENCY_0WS 0 +#define FLASH_ACR_LATENCY_1WS 1 +#define FLASH_ACR_LATENCY_2WS 1 +/**@}*/ + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_EOP (1 << 5) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_PGERR (1 << 2) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_OBL_LAUNCH (1 << 13) + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +#define FLASH_OBR_DATA1_SHIFT 24 +#define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT) +#define FLASH_OBR_DATA0_SHIFT 16 +#define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT) +#define FLASH_OBR_USER_SHIFT 8 +#define FLASH_OBR_USER (0xFF << FLASH_OBR_USER_SHIFT) + +#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT_L2 (3 << FLASH_OBR_RDPRT_SHIFT) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/* Read protection option byte protection level setting */ +#define FLASH_RDP_L0 ((uint8_t)0xa5) +#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */ +#define FLASH_RDP_L2 ((uint8_t)0xcc) + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/lib/stm32/f0/dac.c b/include/libopencm3/gd32/f1x0/gpio.h index 55cdd62c..9c432124 100644 --- a/lib/stm32/f0/dac.c +++ b/include/libopencm3/gd32/f1x0/gpio.h @@ -1,12 +1,12 @@ -/** @defgroup dac_file DAC +/** @defgroup gpio_defines GPIO Defines * - * @ingroup STM32F0xx + * @brief <b>Defined Constants and Types for the GD32F1x0 General Purpose I/O</b> * - * @brief <b>libopencm3 STM32F0xx DAC</b> + * @ingroup GD32F1x0_defines * * @version 1.0.0 * - * @date 11 July 2013 + * @date 1 July 2012 * * LGPL License Terms @ref lgpl_license */ @@ -28,4 +28,4 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/dac.h> +#include <libopencm3/stm32/f0/gpio.h> diff --git a/include/libopencm3/gd32/f1x0/irq.json b/include/libopencm3/gd32/f1x0/irq.json new file mode 100644 index 00000000..87c00d1a --- /dev/null +++ b/include/libopencm3/gd32/f1x0/irq.json @@ -0,0 +1,59 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "rtc", + "flash", + "rcc", + "exti0_1", + "exti2_3", + "exti4_15", + "tsc", + "dma_channel1", + "dma_channel2_3", + "dma_channel4_5", + "adc_comp", + "tim1_brk_up_trg_com", + "tim1_cc", + "tim2", + "tim3", + "tim6_dac", + "reserved0", + "tim14", + "tim15", + "tim16", + "tim17", + "i2c1_ev", + "i2c2_ev", + "spi1", + "spi2", + "usart1", + "usart2", + "reserved1", + "cec_can", + "reserved2", + "i2c1_er", + "reserved3", + "i2c2_er", + "i2c3_ev", + "i2c3_er", + "usb_lp", + "usb_hp", + "reserved4", + "reserved5", + "reserved6", + "usb_wakeup", + "reserved7", + "reserved8", + "reserved9", + "reserved10", + "reserved11", + "dma_channel6_7", + "reserved12", + "reserved13", + "spi3" + ], + "partname_humanreadable": "GD32F1x0 Series", + "partname_doxygen": "GD32F1x0", + "includeguard": "LIBOPENCM3_GD32F1X0_NVIC_H" +} diff --git a/include/libopencm3/gd32/f1x0/memorymap.h b/include/libopencm3/gd32/f1x0/memorymap.h new file mode 100644 index 00000000..2c9b86d5 --- /dev/null +++ b/include/libopencm3/gd32/f1x0/memorymap.h @@ -0,0 +1,109 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Iceonwy Zheng <icenowy@aosc.io> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include <libopencm3/cm3/memorymap.h> + +/* --- GD32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all buses */ +#define FLASH_BASE (0x08000000U) +#define PERIPH_BASE (0x40000000U) +#define INFO_BASE (0x1ffff000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x8000000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) + +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6000) +#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) + +#define BACKUP_REGS_BASE (RTC_BASE + 0x50) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800) +/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define SYSCFG_COMP_BASE (PERIPH_BASE_APB2 + 0x0000) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) + +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) + +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) + +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) + +#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) + +/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ + +/* AHB1 */ + +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x00000) + +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x01000) + +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x02000) +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x03000) +#define TSC_BASE (PERIPH_BASE_AHB1 + 0x03000) + + +/* AHB 2 */ + +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0c00) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) +#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7ac) +/* Ignore the "reserved for future use" half of the first word */ +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + + +#endif diff --git a/include/libopencm3/gd32/f1x0/rcc.h b/include/libopencm3/gd32/f1x0/rcc.h new file mode 100644 index 00000000..63778317 --- /dev/null +++ b/include/libopencm3/gd32/f1x0/rcc.h @@ -0,0 +1,558 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief <b>Defined Constants and Types for the GD32F1x0 Reset and Clock + * Control</b> + * + * @ingroup GD32F1x0_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \<memeruiz at gmail dot com\> + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann <uwe@hermann-uwe.de> + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) +#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) +#define RCC_CR2 MMIO32(RCC_BASE + 0x34) + + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +#define RCC_CFGR_PLLNODIV (1 << 31) + +#define RCC_CFGR_MCOPRE_SHIFT 28 +#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) + +#define RCC_CFGR_PLLMUL_4_SHIFT 27 +#define RCC_CFGR_PLLMUL_4 (1 << RCC_CFGR_PLLMUL_4_SHIFT) + +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO_MASK 0x7 +#define RCC_CFGR_MCO_NOCLK 0 +#define RCC_CFGR_MCO_HSI14 1 +#define RCC_CFGR_MCO_LSI 2 +#define RCC_CFGR_MCO_LSE 3 +#define RCC_CFGR_MCO_SYSCLK 4 +#define RCC_CFGR_MCO_HSI 5 +#define RCC_CFGR_MCO_HSE 6 +#define RCC_CFGR_MCO_PLL 7 + +#define RCC_CFGR_USBPRE_SHIFT 22 +#define RCC_CFGR_USBPRE (3 << RCC_CFGR_USBPRE_SHIFT) + +#define RCC_CFGR_PLLMUL_0_3_SHIFT 18 +#define RCC_CFGR_PLLMUL_0_3 (0xF << RCC_CFGR_PLLMUL_0_3_SHIFT) + +#define RCC_CFGR_PLLXTPRE (1 << 17) +#define RCC_CFGR_PLLSRC (1 << 16) + +#define RCC_CFGR_ADCPRE_SHIFT 14 +#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT) + +#define RCC_CFGR_PPRE2_SHIFT 11 +#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT) + +#define RCC_CFGR_PPRE1_SHIFT 8 +#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT) + +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT) + +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) + +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) + +/** @defgroup rcc_cfgr_usbpre USBPRE: USB prescaler (RCC_CFGR[23:22]) + * @{ + */ +#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 +#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 +#define RCC_CFGR_USBPRE_PLL_CLK_DIV2_5 0x2 +#define RCC_CFGR_USBPRE_PLL_CLK_DIV2 0x3 +/**@}*/ + +/** @defgroup rcc_cfgr_pmf PLLMUL: PLL multiplication factor + * @{ + */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe +/**@}*/ + +/** @defgroup rcc_cfgr_hsepre PLLXTPRE: HSE divider for PLL entry + * @{ + */ +#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 +#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 +/**@}*/ + +/** @defgroup rcc_cfgr_pcs PLLSRC: PLL entry clock source + * @{ + */ +#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +/**@}*/ + +/** @defgroup rcc_cfgr_adcpre ADCPRE: ADC prescaler + * @{ + */ +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 +/**@}*/ + +/** @defgroup rcc_cfgr_apb2pre PPRE2: APB high-speed prescaler (APB2) + * @{ + */ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 +/**@}*/ + +/** @defgroup rcc_cfgr_apb1pre PPRE1: APB low-speed prescaler (APB1) + * @{ + */ +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 +/**@}*/ + +/** @defgroup rcc_cfgr_ahbpre HPRE: AHB prescaler + * @{ + */ +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf +/**@}*/ + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 + +/** @defgroup rcc_cfgr_scs SW: System clock switch + * @{ + */ +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 +/**@}*/ + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_HSI14RDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_HSI14RDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_HSI14RDYF (1 << 5) +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values values +@{*/ +#define RCC_APB2RSTR_TIM17RST (1 << 18) +#define RCC_APB2RSTR_TIM16RST (1 << 17) +#define RCC_APB2RSTR_TIM15RST (1 << 16) +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_ADCRST (1 << 9) +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ + +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values values +@{*/ +#define RCC_APB1RSTR_CECRST (1 << 30) +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_USBRST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ + +/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values +@{*/ +#define RCC_AHBENR_TSCEN (1 << 24) +#define RCC_AHBENR_GPIOFEN (1 << 22) +#define RCC_AHBENR_GPIOEEN (1 << 21) +#define RCC_AHBENR_GPIODEN (1 << 20) +#define RCC_AHBENR_GPIOCEN (1 << 19) +#define RCC_AHBENR_GPIOBEN (1 << 18) +#define RCC_AHBENR_GPIOAEN (1 << 17) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLTFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMAEN (1 << 0) +/**@}*/ + +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@{*/ +#define RCC_APB2ENR_TIM17EN (1 << 18) +#define RCC_APB2ENR_TIM16EN (1 << 17) +#define RCC_APB2ENR_TIM15EN (1 << 16) +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADCEN (1 << 9) +#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0) +/**@}*/ + +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@{*/ +#define RCC_APB1ENR_CECEN (1 << 30) +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_USBEN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values values +@{*/ +#define RCC_AHBRSTR_ETHMACRST (1 << 14) +#define RCC_AHBRSTR_OTGFSRST (1 << 12) +/**@}*/ + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ + +#define RCC_CFGR2_PREDIV 0xf +#define RCC_CFGR2_PREDIV_NODIV 0x0 +#define RCC_CFGR2_PREDIV_DIV2 0x1 +#define RCC_CFGR2_PREDIV_DIV3 0x2 +#define RCC_CFGR2_PREDIV_DIV4 0x3 +#define RCC_CFGR2_PREDIV_DIV5 0x4 +#define RCC_CFGR2_PREDIV_DIV6 0x5 +#define RCC_CFGR2_PREDIV_DIV7 0x6 +#define RCC_CFGR2_PREDIV_DIV8 0x7 +#define RCC_CFGR2_PREDIV_DIV9 0x8 +#define RCC_CFGR2_PREDIV_DIV10 0x9 +#define RCC_CFGR2_PREDIV_DIV11 0xa +#define RCC_CFGR2_PREDIV_DIV12 0xb +#define RCC_CFGR2_PREDIV_DIV13 0xc +#define RCC_CFGR2_PREDIV_DIV14 0xd +#define RCC_CFGR2_PREDIV_DIV15 0xe +#define RCC_CFGR2_PREDIV_DIV16 0xf + +/* --- RCC_CFGR3 values ---------------------------------------------------- */ + +#define RCC_CFGR3_USART2SW_SHIFT 16 +#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) + +#define RCC_CFGR3_ADCSW (1 << 8) +#define RCC_CFGR3_CECSW (1 << 6) + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ahb_frequency; +extern uint32_t rcc_apb1_frequency; +extern uint32_t rcc_apb2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +enum rcc_clock_hsi { + RCC_CLOCK_HSI_48MHZ, + RCC_CLOCK_HSI_64MHZ, + RCC_CLOCK_HSI_END +}; + +enum rcc_clock_hse8 { + RCC_CLOCK_HSE8_72MHZ, + RCC_CLOCK_HSE8_END +}; + +struct rcc_clock_scale { + uint8_t pllmul; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint8_t adcpre; + uint8_t usbpre; /* Only valid if HSE used */ + bool use_hse; /* PLL source is HSE if set, HSI/2 if unset */ + uint8_t pll_hse_prediv; /* Only valid if HSE used */ + uint32_t ahb_frequency; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +}; + +extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_HSI_END]; +extern const struct rcc_clock_scale rcc_hse8_configs[RCC_CLOCK_HSE8_END]; + +enum rcc_osc { + RCC_PLL, RCC_HSE, RCC_HSI, RCC_LSE, RCC_LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +/* V = value line F100 + * N = standard line F101, F102, F103 + * C = communication line F105, F107 + */ +enum rcc_periph_clken { + + /* AHB peripherals */ + RCC_DMA = _REG_BIT(0x14, 0), + RCC_SRAM = _REG_BIT(0x14, 2), + RCC_FLTF = _REG_BIT(0x14, 4), + RCC_CRC = _REG_BIT(0x14, 6), + RCC_GPIOA = _REG_BIT(0x14, 17), + RCC_GPIOB = _REG_BIT(0x14, 18), + RCC_GPIOC = _REG_BIT(0x14, 19), + RCC_GPIOD = _REG_BIT(0x14, 20), + RCC_GPIOF = _REG_BIT(0x14, 22), + RCC_TSC = _REG_BIT(0x14, 24), + + /* APB2 peripherals */ + RCC_SYSCFG_COMP = _REG_BIT(0x18, 0), + RCC_ADC = _REG_BIT(0x18, 9), + RCC_TIM1 = _REG_BIT(0x18, 11), + RCC_SPI1 = _REG_BIT(0x18, 12), + RCC_USART1 = _REG_BIT(0x18, 14), + RCC_TIM15 = _REG_BIT(0x18, 16), + RCC_TIM16 = _REG_BIT(0x18, 17), + RCC_TIM17 = _REG_BIT(0x18, 18), + + /* APB1 peripherals */ + RCC_TIM2 = _REG_BIT(0x1C, 0), + RCC_TIM3 = _REG_BIT(0x1C, 1), + RCC_TIM6 = _REG_BIT(0x1C, 4), + RCC_TIM14 = _REG_BIT(0x1C, 8), + RCC_WWDG = _REG_BIT(0x1C, 11), + RCC_SPI2 = _REG_BIT(0x1C, 14), + RCC_SPI3 = _REG_BIT(0x1C, 15), + RCC_USART2 = _REG_BIT(0x1C, 17), + RCC_I2C1 = _REG_BIT(0x1C, 21), + RCC_I2C2 = _REG_BIT(0x1C, 22), + RCC_USB = _REG_BIT(0x1C, 23), + RCC_PWR = _REG_BIT(0x1C, 28), + RCC_DAC = _REG_BIT(0x1C, 29), + RCC_CEC = _REG_BIT(0x1C, 30), +}; + +enum rcc_periph_rst { + + /* Advanced peripherals */ + RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */ + + /* AHB peripherals */ + RST_GPIOA = _REG_BIT(0x28, 17), + RST_GPIOB = _REG_BIT(0x28, 18), + RST_GPIOC = _REG_BIT(0x28, 19), + RST_GPIOD = _REG_BIT(0x28, 20), + RST_GPIOE = _REG_BIT(0x28, 21), + RST_GPIOF = _REG_BIT(0x28, 22), + RST_TSC = _REG_BIT(0x28, 24), + + /* APB2 peripherals */ + RST_SYSCFG = _REG_BIT(0x0C, 0), + RST_ADC = _REG_BIT(0x0C, 9), + RST_TIM1 = _REG_BIT(0x0C, 11), + RST_SPI1 = _REG_BIT(0x0C, 12), + RST_USART1 = _REG_BIT(0x0C, 14), + RST_TIM15 = _REG_BIT(0x0C, 16), + RST_TIM16 = _REG_BIT(0x0C, 17), + RST_TIM17 = _REG_BIT(0x0C, 18), + + /* APB1 peripherals */ + RST_TIM2 = _REG_BIT(0x10, 0), + RST_TIM3 = _REG_BIT(0x10, 1), + RST_TIM6 = _REG_BIT(0x10, 4), + RST_TIM14 = _REG_BIT(0x10, 8), + RST_WWDG = _REG_BIT(0x10, 11), + RST_SPI2 = _REG_BIT(0x10, 14), + RST_SPI3 = _REG_BIT(0x10, 15), + RST_USART2 = _REG_BIT(0x10, 17), + RST_I2C1 = _REG_BIT(0x10, 21), + RST_I2C2 = _REG_BIT(0x10, 22), + RST_USB = _REG_BIT(0x10, 23), + RST_PWR = _REG_BIT(0x10, 28), + RST_DAC = _REG_BIT(0x10, 29), + RST_CEC = _REG_BIT(0x10, 30), +}; + +#include <libopencm3/stm32/common/rcc_common_all.h> + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum rcc_osc osc); +void rcc_osc_ready_int_enable(enum rcc_osc osc); +void rcc_osc_ready_int_disable(enum rcc_osc osc); +int rcc_osc_ready_int_flag(enum rcc_osc osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_osc_on(enum rcc_osc osc); +void rcc_osc_off(enum rcc_osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_multiplication_factor(uint32_t mul); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_pllxtpre(uint32_t pllxtpre); +uint32_t rcc_rtc_clock_enabled_flag(void); +void rcc_enable_rtc_clock(void); +void rcc_set_rtc_clock_source(enum rcc_osc clock_source); +void rcc_set_adcpre(uint32_t adcpre); +void rcc_set_ppre2(uint32_t ppre1); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_usbpre(uint32_t usbpre); +void rcc_set_prediv(uint32_t prediv); +uint32_t rcc_system_clock_source(void); +void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); +void rcc_backupdomain_reset(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/include/libopencm3/gd32/flash.h b/include/libopencm3/gd32/flash.h new file mode 100644 index 00000000..38a7328a --- /dev/null +++ b/include/libopencm3/gd32/flash.h @@ -0,0 +1,28 @@ +/* This provides unification of code over GD32 subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/gd32/memorymap.h> + +#if defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/flash.h> +#else +# error "gd32 family not defined." +#endif + diff --git a/include/libopencm3/gd32/gpio.h b/include/libopencm3/gd32/gpio.h new file mode 100644 index 00000000..51c9ff08 --- /dev/null +++ b/include/libopencm3/gd32/gpio.h @@ -0,0 +1,28 @@ +/* This provides unification of code over GD32 subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/gd32/memorymap.h> + +#if defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/gpio.h> +#else +# error "gd32 family not defined." +#endif + diff --git a/include/libopencm3/gd32/memorymap.h b/include/libopencm3/gd32/memorymap.h new file mode 100644 index 00000000..f751fadc --- /dev/null +++ b/include/libopencm3/gd32/memorymap.h @@ -0,0 +1,29 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H +#define LIBOPENCM3_MEMORYMAP_COMMON_H + +#if defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/memorymap.h> +#else +# error "gd32 family not defined." +#endif + +#endif /* LIBOPENCM3_MEMORYMAP_COMMON_H */ diff --git a/lib/stm32/f2/dma.c b/include/libopencm3/gd32/rcc.h index 285f1fe7..3eefd6ba 100644 --- a/lib/stm32/f2/dma.c +++ b/include/libopencm3/gd32/rcc.h @@ -1,15 +1,4 @@ -/** @defgroup dma_file DMA - -@ingroup STM32F2xx - -@brief <b>libopencm3 STM32F2xx DMA</b> - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license -*/ +/* This provides unification of code over GD32 subfamilies */ /* * This file is part of the libopencm3 project. @@ -28,4 +17,12 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/dma.h> +#include <libopencm3/cm3/common.h> +#include <libopencm3/gd32/memorymap.h> + +#if defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/rcc.h> +#else +# error "gd32 family not defined." +#endif + diff --git a/include/libopencm3/lm3s/doc-lm3s.h b/include/libopencm3/lm3s/doc-lm3s.h index 1a4ecb80..65451407 100644 --- a/include/libopencm3/lm3s/doc-lm3s.h +++ b/include/libopencm3/lm3s/doc-lm3s.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 LM3S +/** @page libopencm3 LM3S @version 1.0.0 diff --git a/include/libopencm3/lm4f/doc-lm4f.h b/include/libopencm3/lm4f/doc-lm4f.h index 4877721e..9812dbc4 100644 --- a/include/libopencm3/lm4f/doc-lm4f.h +++ b/include/libopencm3/lm4f/doc-lm4f.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 LM4F +/** @page libopencm3 LM4F @version 1.0.0 diff --git a/include/libopencm3/lpc13xx/doc-lpc13xx.h b/include/libopencm3/lpc13xx/doc-lpc13xx.h index 5ed7cae9..963ec0a2 100644 --- a/include/libopencm3/lpc13xx/doc-lpc13xx.h +++ b/include/libopencm3/lpc13xx/doc-lpc13xx.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 LPC13xx +/** @page libopencm3 LPC13xx @version 1.0.0 diff --git a/include/libopencm3/lpc17xx/doc-lpc17xx.h b/include/libopencm3/lpc17xx/doc-lpc17xx.h index 4bc603de..e5746179 100644 --- a/include/libopencm3/lpc17xx/doc-lpc17xx.h +++ b/include/libopencm3/lpc17xx/doc-lpc17xx.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 LPC17xx +/** @page libopencm3 LPC17xx @version 1.0.0 diff --git a/include/libopencm3/lpc43xx/doc-lpc43xx.h b/include/libopencm3/lpc43xx/doc-lpc43xx.h index 3c21aaeb..b5687d82 100644 --- a/include/libopencm3/lpc43xx/doc-lpc43xx.h +++ b/include/libopencm3/lpc43xx/doc-lpc43xx.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 LPC43xx +/** @page libopencm3 LPC43xx @version 1.0.0 diff --git a/include/libopencm3/msp432/e4/doc-msp432e4.h b/include/libopencm3/msp432/e4/doc-msp432e4.h index 50239142..6383ac14 100644 --- a/include/libopencm3/msp432/e4/doc-msp432e4.h +++ b/include/libopencm3/msp432/e4/doc-msp432e4.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 MSP432E4 +/** @page libopencm3 MSP432E4 @version 1.0.0 diff --git a/include/libopencm3/msp432/e4/gpio.h b/include/libopencm3/msp432/e4/gpio.h new file mode 100644 index 00000000..9ad39ff2 --- /dev/null +++ b/include/libopencm3/msp432/e4/gpio.h @@ -0,0 +1,2524 @@ +/** @defgroup gpio_defines General Purpose I/O Defines + * + * @ingroup MSP432E4xx_defines + * + * @brief Defined Constants and Types for the MSP432E4 General Purpose I/O + * + * @version 1.0.0 + * + * @date 23 September 2018 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> + * Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef MSP432E4_GPIO_H +#define MSP432E4_GPIO_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/msp432/e4/memorymap.h> +#include <stdbool.h> + +/** @defgroup gpio_reg_base GPIO Register Base Addresses + * @brief GPIO Register Base Addresses +@{*/ +/** GPIOA Base Address */ +#define GPIOA GPIOA_BASE +/** GPIOB Base Address */ +#define GPIOB GPIOB_BASE +/** GPIOC Base Address */ +#define GPIOC GPIOC_BASE +/** GPIOD Base Address */ +#define GPIOD GPIOD_BASE +/** GPIOE Base Address */ +#define GPIOE GPIOE_BASE +/** GPIOF Base Address */ +#define GPIOF GPIOF_BASE +/** GPIOG Base Address */ +#define GPIOG GPIOG_BASE +/** GPIOH Base Address */ +#define GPIOH GPIOH_BASE +/** GPIOJ Base Address */ +#define GPIOJ GPIOJ_BASE +/** GPIOK Base Address */ +#define GPIOK GPIOK_BASE +/** GPIOL Base Address */ +#define GPIOL GPIOL_BASE +/** GPIOM Base Address */ +#define GPIOM GPIOM_BASE +/** GPION Base Address */ +#define GPION GPION_BASE +/** GPIOP Base Address */ +#define GPIOP GPIOP_BASE +/** GPIOQ Base Address */ +#define GPIOQ GPIOQ_BASE +/**@}*/ + +/** @defgroup gpio_pin_id GPIO Pin Identifiers + * @brief GPIO Pin Identifiers +@{*/ +/** GPIO Pin 0 Identifier */ +#define GPIO0 (1 << 0) +/** GPIO Pin 1 Identifier */ +#define GPIO1 (1 << 1) +/** GPIO Pin 2 Identifier */ +#define GPIO2 (1 << 2) +/** GPIO Pin 3 Identifier */ +#define GPIO3 (1 << 3) +/** GPIO Pin 4 Identifier */ +#define GPIO4 (1 << 4) +/** GPIO Pin 5 Identifier */ +#define GPIO5 (1 << 5) +/** GPIO Pin 6 Identifier */ +#define GPIO6 (1 << 6) +/** GPIO Pin 7 Identifier */ +#define GPIO7 (1 << 7) +/** GPIO All Pins Identifier */ +#define GPIO_ALL (0xFF) +/**@}*/ + +/** @defgroup gpio_af_id GPIO Alternate Functions Identifiers + * @brief GPIO Alternate Functions Identifiers +@{*/ +/** GPIO Alternate Function 1 Identifier */ +#define GPIO_AF1 0x1 +/** GPIO Alternate Function 2 Identifier */ +#define GPIO_AF2 0x2 +/** GPIO Alternate Function 3 Identifier */ +#define GPIO_AF3 0x3 +/** GPIO Alternate Function 4 Identifier */ +#define GPIO_AF4 0x4 +/** GPIO Alternate Function 5 Identifier */ +#define GPIO_AF5 0x5 +/** GPIO Alternate Function 6 Identifier */ +#define GPIO_AF6 0x6 +/** GPIO Alternate Function 7 Identifier */ +#define GPIO_AF7 0x7 +/** GPIO Alternate Function 8 Identifier */ +#define GPIO_AF8 0x8 +/** GPIO Alternate Function 11 Identifier */ +#define GPIO_AF11 0xB +/** GPIO Alternate Function 13 Identifier */ +#define GPIO_AF13 0xD +/** GPIO Alternate Function 14 Identifier */ +#define GPIO_AF14 0xE +/** GPIO Alternate Function 15 Identifier */ +#define GPIO_AF15 0xF +/** GPIO Alternate Function Disable */ +#define GPIO_AF_DISABLE 0x0 +/**@}*/ + +/** @defgroup gpio_registers GPIO Registers + * @brief GPIO Registers +@{*/ +/** GPIO Data */ +#define GPIO_DATA(port) (&MMIO32((port) + 0x000)) +/** GPIO Direction */ +#define GPIO_DIR(port) MMIO32((port) + 0x400) +/** GPIO Interrupt Sense */ +#define GPIO_IS(port) MMIO32((port) + 0x404) +/** GPIO Interrupt Both Edges */ +#define GPIO_IBE(port) MMIO32((port) + 0x408) +/** GPIO Interrupt Event */ +#define GPIO_IEV(port) MMIO32((port) + 0x40C) +/** GPIO Interrupt Mask */ +#define GPIO_IM(port) MMIO32((port) + 0x410) +/** GPIO Raw Interrupt Status */ +#define GPIO_RIS(port) MMIO32((port) + 0x414) +/** GPIO Masked Interrupt Status */ +#define GPIO_MIS(port) MMIO32((port) + 0x418) +/** GPIO Interrupt Clear */ +#define GPIO_ICR(port) MMIO32((port) + 0x41C) +/** GPIO Alternate Function Select */ +#define GPIO_AFSEL(port) MMIO32((port) + 0x420) +/** GPIO 2-mA Drive Select */ +#define GPIO_DR2R(port) MMIO32((port) + 0x500) +/** GPIO 4-mA Drive Select */ +#define GPIO_DR4R(port) MMIO32((port) + 0x504) +/** GPIO 8-mA Drive Select */ +#define GPIO_DR8R(port) MMIO32((port) + 0x508) +/** GPIO Open Drain Select */ +#define GPIO_ODR(port) MMIO32((port) + 0x50C) +/** GPIO Pull-Up Select */ +#define GPIO_PUR(port) MMIO32((port) + 0x510) +/** GPIO Pull-Down Select */ +#define GPIO_PDR(port) MMIO32((port) + 0x514) +/** GPIO Slew Rate Control Select */ +#define GPIO_SLR(port) MMIO32((port) + 0x518) +/** GPIO Digital Enable */ +#define GPIO_DEN(port) MMIO32((port) + 0x51C) +/** GPIO Lock */ +#define GPIO_LOCK(port) MMIO32((port) + 0x520) +/** GPIO Commit */ +#define GPIO_CR(port) MMIO32((port) + 0x524) +/** GPIO Analog Mode Select */ +#define GPIO_AMSEL(port) MMIO32((port) + 0x528) +/** GPIO Port Control */ +#define GPIO_PCTL(port) MMIO32((port) + 0x52C) +/** GPIO ADC Control */ +#define GPIO_ADCCTL(port) MMIO32((port) + 0x530) +/** GPIO DMA Control */ +#define GPIO_DMACTL(port) MMIO32((port) + 0x534) +/** GPIO Select Interrupt */ +#define GPIO_SI(port) MMIO32((port) + 0x538) +/** GPIO 12-mA Drive Select */ +#define GPIO_DR12R(port) MMIO32((port) + 0x53C) +/** GPIO Wake Pin Enable + * @note This register is only available on Port K */ +#define GPIO_WAKEPEN(port) MMIO32((port) + 0x540) +/** GPIO Wake Level + * @note This register is only available on Port K */ +#define GPIO_WAKELVL(port) MMIO32((port) + 0x544) +/** GPIO Wake Status + * @note This register is only available on Port K */ +#define GPIO_WAKESTAT(port) MMIO32((port) + 0x548) +/** GPIO Peripheral Property */ +#define GPIO_PP(port) MMIO32((port) + 0xFC0) +/** GPIO Peripheral Configuration */ +#define GPIO_PC(port) MMIO32((port) + 0xFC4) + +/** GPIO Peripheral Identification 0 */ +#define GPIO_PERIPH_ID0(port) MMIO32((port) + 0xFE0) +/** GPIO Peripheral Identification 1 */ +#define GPIO_PERIPH_ID1(port) MMIO32((port) + 0xFE4) +/** GPIO Peripheral Identification 2 */ +#define GPIO_PERIPH_ID2(port) MMIO32((port) + 0xFE8) +/** GPIO Peripheral Identification 3 */ +#define GPIO_PERIPH_ID3(port) MMIO32((port) + 0xFEC) +/** GPIO Peripheral Identification 4 */ +#define GPIO_PERIPH_ID4(port) MMIO32((port) + 0xFD0) +/** GPIO Peripheral Identification 5 */ +#define GPIO_PERIPH_ID5(port) MMIO32((port) + 0xFD4) +/** GPIO Peripheral Identification 6 */ +#define GPIO_PERIPH_ID6(port) MMIO32((port) + 0xFD8) +/** GPIO Peripheral Identification 7 */ +#define GPIO_PERIPH_ID7(port) MMIO32((port) + 0xFDC) + +/** GPIO PrimeCell Identification 0 */ +#define GPIO_PCELL_ID0(port) MMIO32((port) + 0xFF0) +/** GPIO PrimeCell Identification 1 */ +#define GPIO_PCELL_ID1(port) MMIO32((port) + 0xFF4) +/** GPIO PrimeCell Identification 2 */ +#define GPIO_PCELL_ID2(port) MMIO32((port) + 0xFF8) +/** GPIO PrimeCell Identification 3 */ +#define GPIO_PCELL_ID3(port) MMIO32((port) + 0xFFC) +/**@}*/ + +/** @defgroup gpio_im_values GPIO_IM Values + * @brief GPIO Interrupt Mask Register Values +@{*/ +/** GPIO Micro Direct Memory Access Done Interrupt Mask Enable */ +#define GPIO_IM_DMAIME (1 << 8) +/**@}*/ + +/** @defgroup gpio_ris_values GPIO_RIS Values + * @brief GPIO Raw Interrupt Status Register Values +@{*/ +/** GPIO Micro Direct Memory Access Done Interrupt Raw Status */ +#define GPIO_RIS_DMARIS (1 << 8) +/**@}*/ + +/** @defgroup gpio_mis_values GPIO_MIS Values + * @brief GPIO Masked Interrupt Status Register Values +@{*/ +/** GPIO Micro Direct Memory Access Done Masked Interrupt Status */ +#define GPIO_MIS_DMAMIS (1 << 8) +/**@}*/ + +/** @defgroup gpio_icr_values GPIO_RIS Values + * @brief GPIO Interrupt Clear Register Values +@{*/ +/** GPIO Micro Direct Memory Access Interrupt Clear */ +#define GPIO_ICR_DMAIC (1 << 8) +/**@}*/ + +/** @defgroup gpio_lock_values GPIO_LOCK Values + * @brief GPIO Lock Register Values +@{*/ +/* Value we need to write to unlock the GPIO commit register */ +#define GPIO_LOCK_UNLOCK_CODE (0x4C4F434B) +/** GPIO Lock Status */ +#define GPIO_LOCK_STATUS (1 << 0) +/**@}*/ + +/** @defgroup gpio_pctl_values GPIO_PCTL Values + * @brief GPIO Port Control Register Values +@{*/ +/** GPIO Port Control Set AF for Pin */ +#define GPIO_PCTL_AF(pin, af) ((af) << ((pin) * 4)) +/* GPIO Port Control Mask for Pin */ +#define GPIO_PCTL_MASK(pin) GPIO_PCTL_AF((pin), 0xf) +/**@}*/ + +/** @defgroup gpio_si_values GPIO_SI Values + * @brief GPIO Select Interrupt Register Values +@{*/ +/** Summary Interrupt */ +#define GPIO_SI_SUM (1 << 0) +/**@}*/ + +/** @defgroup gpio_wakepen_values GPIO_WAKEPEN Values + * @brief GPIO Wake Pin Enable Register Values + * @note This register is only available on Port K +@{*/ +/** PK7 Wake Enable */ +#define GPIO_WAKEPEN_WAKEP7 (1 << 7) +/** PK6 Wake Enable */ +#define GPIO_WAKEPEN_WAKEP6 (1 << 6) +/** PK5 Wake Enable */ +#define GPIO_WAKEPEN_WAKEP5 (1 << 5) +/** PK4 Wake Enable */ +#define GPIO_WAKEPEN_WAKEP4 (1 << 4) +/**@}*/ + +/** @defgroup gpio_wakelvl_values GPIO_WAKELVL Values + * @brief GPIO Wake Level Register Values +@{*/ +/** PK7 Wake Level */ +#define GPIO_WAKELVL_WAKELVL7 (1 << 7) +/** PK6 Wake Level */ +#define GPIO_WAKELVL_WAKELVL6 (1 << 6) +/** PK5 Wake Level */ +#define GPIO_WAKELVL_WAKELVL5 (1 << 5) +/** PK4 Wake Level */ +#define GPIO_WAKELVL_WAKELVL4 (1 << 4) +/**@}*/ + +/** @defgroup gpio_wakestat_values GPIO_WAKESTAT Values + * @brief GPIO Wake Status Register Values +@{*/ +/** PK7 Wake Status */ +#define GPIO_WAKESTAT_STAT7 (1 << 7) +/** PK6 Wake Status */ +#define GPIO_WAKESTAT_STAT6 (1 << 6) +/** PK5 Wake Status */ +#define GPIO_WAKESTAT_STAT5 (1 << 5) +/** PK4 Wake Status */ +#define GPIO_WAKESTAT_STAT4 (1 << 4) +/**@}*/ + +/** @defgroup gpio_pp_values GPIO_PP Values + * @brief GPIO Peripheral Property Register Values +@{*/ +/** Extended Drive Enable */ +#define GPIO_PP_EDE (1 << 0) +/**@}*/ + +/** @defgroup gpio_pc_values GPIO_PC Values + * @brief GPIO Peripheral Configuration Register Values +@{*/ +/** Extended Drive Mode Bit N */ +#define GPIO_PC_EDM(n, mode) ((mode) << (2 * (n))) +/** Extended Drive Mode Bit N Mask */ +#define GPIO_PC_EDM_MASK(n) (0x3 << (2 * (n))) +/** Normal behavior, 2, 4 and 8 mA are available */ +#define GPIO_PC_EDM_NORMAL 0x0 +/** An additional 6 mA option is provided. + * Set one, clear other behavior is disabled */ +#define GPIO_PC_EDM_ADD_6MA 0x1 +/** Full range, 2, 4, 6, 8, 10 and 12 mA are available. + * Set one, clear other behavior is disabled */ +#define GPIO_PC_EDM_FULL_RANGE 0x3 +/**@}*/ + +/** @defgroup gpio_af_pa0_values GPIO_AF_PA0 Values + * @brief GPIO PA0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 33 | + * NFBGA-212 | V3 | +@{*/ +/** UART module 0 receive */ +#define GPIO_AF_PA0_U0RX GPIO_AF1 +/** I2C module 9 clock */ +#define GPIO_AF_PA0_I2C9SCL GPIO_AF2 +/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ +#define GPIO_AF_PA0_T0CCP0 GPIO_AF3 +/** CAN module 0 receive */ +#define GPIO_AF_PA0_CAN0RX GPIO_AF7 +/**@}*/ + +/** @defgroup gpio_af_pa1_values GPIO_AF_PA1 Values + * @brief GPIO PA1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 34 | + * NFBGA-212 | W3 | +@{*/ +/** UART module 0 transmit */ +#define GPIO_AF_PA1_U0TX GPIO_AF1 +/** I2C module 9 data */ +#define GPIO_AF_PA1_I2C9SDA GPIO_AF2 +/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ +#define GPIO_AF_PA1_T0CCP1 GPIO_AF3 +/** CAN module 0 transmit */ +#define GPIO_AF_PA1_CAN0TX GPIO_AF7 +/**@}*/ + +/** @defgroup gpio_af_pa2_values GPIO_AF_PA2 Values + * @brief GPIO PA2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 35 | + * NFBGA-212 | T6 | +@{*/ +/** UART module 4 receive */ +#define GPIO_AF_PA2_U4RX GPIO_AF1 +/** I2C module 8 clock */ +#define GPIO_AF_PA2_I2C8SCL GPIO_AF2 +/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ +#define GPIO_AF_PA2_T1CCP0 GPIO_AF3 +/** SSI module 0 clock */ +#define GPIO_AF_PA2_SSI0CLK GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pa3_values GPIO_AF_PA3 Values + * @brief GPIO PA3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 36 | + * NFBGA-212 | U5 | +@{*/ +/** UART module 4 transmit */ +#define GPIO_AF_PA3_U4TX GPIO_AF1 +/** I2C module 8 data */ +#define GPIO_AF_PA3_I2C8SDA GPIO_AF2 +/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ +#define GPIO_AF_PA3_T1CCP1 GPIO_AF3 +/** SSI module 0 frame signal */ +#define GPIO_AF_PA3_SSI0FSS GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pa4_values GPIO_AF_PA4 Values + * @brief GPIO PA4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 37 | + * NFBGA-212 | V4 | +@{*/ +/** UART module 3 receive */ +#define GPIO_AF_PA4_U3RX GPIO_AF1 +/** I2C module 7 clock */ +#define GPIO_AF_PA4_I2C7SCL GPIO_AF2 +/** 16- and 32-bit Timer 2 capture, compare, or PWM 0 */ +#define GPIO_AF_PA4_T2CCP0 GPIO_AF3 +/** SSI Module 0 bidirectional data pin 0 */ +#define GPIO_AF_PA4_SSI0XDAT0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pa5_values GPIO_AF_PA5 Values + * @brief GPIO PA5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 38 | + * NFBGA-212 | W4 | +@{*/ +/** UART module 3 transmit */ +#define GPIO_AF_PA5_U3TX GPIO_AF1 +/** I2C module 7 data */ +#define GPIO_AF_PA5_I2C7SDA GPIO_AF2 +/** 16- and 32-bit Timer 2 capture, compare, or PWM 1 */ +#define GPIO_AF_PA5_T2CCP1 GPIO_AF3 +/** SSI Module 0 bidirectional data pin 1 */ +#define GPIO_AF_PA5_SSI0XDAT1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pa6_values GPIO_AF_PA6 Values + * @brief GPIO PA6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 40 | + * NFBGA-212 | V5 | +@{*/ +/** UART module 2 receive */ +#define GPIO_AF_PA6_U2RX GPIO_AF1 +/** I2C module 6 clock */ +#define GPIO_AF_PA6_I2C6SCL GPIO_AF2 +/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ +#define GPIO_AF_PA6_T3CCP0 GPIO_AF3 +/** USB Control an external power source in host mode */ +#define GPIO_AF_PA6_USB0EPEN GPIO_AF5 +/** SSI Module 0 bidirectional data pin 2 */ +#define GPIO_AF_PA6_SSI0XDAT2 GPIO_AF13 +/** Ethernet 0 receive clock */ +#define GPIO_AF_PA6_EN0RXCK GPIO_AF14 +/** EPI module 0 signal 8 */ +#define GPIO_AF_PA6_EPI0S8 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pa7_values GPIO_AF_PA7 Values + * @brief GPIO PA7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 41 | + * NFBGA-212 | R7 | +@{*/ +/** UART module 2 transmit */ +#define GPIO_AF_PA7_U2TX GPIO_AF1 +/** I2C module 6 data */ +#define GPIO_AF_PA7_I2C6SDA GPIO_AF2 +/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ +#define GPIO_AF_PA7_T3CCP1 GPIO_AF3 +/** USB Power Fault input in host mode */ +#define GPIO_AF_PA7_USB0PFLT GPIO_AF5 +/** USB Control an external power source in host mode */ +#define GPIO_AF_PA7_USB0EPEN GPIO_AF11 +/** SSI Module 0 bidirectional data pin 3 */ +#define GPIO_AF_PA7_SSI0XDAT3 GPIO_AF13 +/** EPI module 0 signal 9 */ +#define GPIO_AF_PA7_EPI0S9 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pb0_values GPIO_AF_PB0 Values + * @brief GPIO PB0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 95 | + * NFBGA-212 | A16 | +@{*/ +/** UART module 1 receive */ +#define GPIO_AF_PB0_U1RX GPIO_AF1 +/** I2C module 5 clock */ +#define GPIO_AF_PB0_I2C5SCL GPIO_AF2 +/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ +#define GPIO_AF_PB0_T4CCP0 GPIO_AF3 +/** CAN module 1 receive */ +#define GPIO_AF_PB0_CAN1RX GPIO_AF7 +/**@}*/ + +/** @defgroup gpio_af_pb1_values GPIO_AF_PB1 Values + * @brief GPIO PB1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 96 | + * NFBGA-212 | B16 | +@{*/ +/** UART module 1 transmit */ +#define GPIO_AF_PB1_U1TX GPIO_AF1 +/** I2C module 5 data */ +#define GPIO_AF_PB1_I2C5SDA GPIO_AF2 +/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ +#define GPIO_AF_PB1_T4CCP1 GPIO_AF3 +/** CAN module 1 transmit */ +#define GPIO_AF_PB1_CAN1TX GPIO_AF7 +/**@}*/ + +/** @defgroup gpio_af_pb2_values GPIO_AF_PB2 Values + * @brief GPIO PB2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 91 | + * NFBGA-212 | A17 | +@{*/ +/** I2C module 0 clock */ +#define GPIO_AF_PB2_I2C0SCL GPIO_AF2 +/** 16- and 32-bit Timer 5 capture, compare, or PWM 0 */ +#define GPIO_AF_PB2_T5CCP0 GPIO_AF3 +/** Ethernet 0 management data clock */ +#define GPIO_AF_PB2_EN0MDC GPIO_AF5 +/** USB Asserted by the USB controller to signal the end of a USB transmit + * packet or register write operation */ +#define GPIO_AF_PB2_USB0STP GPIO_AF14 +/** EPI module 0 signal 27 */ +#define GPIO_AF_PB2_EPI0S27 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pb3_values GPIO_AF_PB3 Values + * @brief GPIO PB3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 92 | + * NFBGA-212 | B17 | +@{*/ +/** I2C module 0 data */ +#define GPIO_AF_PB3_I2C0SDA GPIO_AF2 +/** 16- and 32-bit Timer 5 capture, compare, or PWM 1 */ +#define GPIO_AF_PB3_T5CCP1 GPIO_AF3 +/** Ethernet 0 management data input/output signal */ +#define GPIO_AF_PB3_EN0MDIO GPIO_AF5 +/** USB 60-MHz clock to the external PHY */ +#define GPIO_AF_PB3_USB0CLK GPIO_AF14 +/** EPI module 0 signal 28 */ +#define GPIO_AF_PB3_EPI0S28 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pb4_values GPIO_AF_PB4 Values + * @brief GPIO PB4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 121 | + * NFBGA-212 | C6 | +@{*/ +/** UART module 0 clear to send modem flow control input signal */ +#define GPIO_AF_PB4_U0CTS GPIO_AF1 +/** I2C module 5 clock */ +#define GPIO_AF_PB4_I2C5SCL GPIO_AF2 +/** SSI module 1 frame signal */ +#define GPIO_AF_PB4_SSI1FSS GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pb5_values GPIO_AF_PB5 Values + * @brief GPIO PB5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 120 | + * NFBGA-212 | B6 | +@{*/ +/** UART module 0 request to send modem flow control output signal */ +#define GPIO_AF_PB5_U0RTS GPIO_AF1 +/** I2C module 5 data */ +#define GPIO_AF_PB5_I2C5SDA GPIO_AF2 +/** SSI module 1 clock */ +#define GPIO_AF_PB5_SSI1CLK GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pb6_values GPIO_AF_PB6 Values + * @brief GPIO PB6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | F2 | +@{*/ +/** I2C module 6 clock */ +#define GPIO_AF_PB6_I2C6SCL GPIO_AF1 +/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ +#define GPIO_AF_PB6_T6CCP0 GPIO_AF3 +/**@}*/ + +/** @defgroup gpio_af_pb7_values GPIO_AF_PB7 Values + * @brief GPIO PB7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | F1 | +@{*/ +/** I2C module 6 data */ +#define GPIO_AF_PB7_I2C6SDA GPIO_AF1 +/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ +#define GPIO_AF_PB7_T6CCP1 GPIO_AF3 +/**@}*/ + +/** @defgroup gpio_af_pc0_values GPIO_AF_PC0 Values + * @brief GPIO PC0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 100 | + * NFBGA-212 | B15 | +@{*/ +/** JTAG and SWD clock */ +#define GPIO_AF_PC0_TCK GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pc1_values GPIO_AF_PC1 Values + * @brief GPIO PC1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 99 | + * NFBGA-212 | C15 | +@{*/ +/** JTAG TMS and SWDIO */ +#define GPIO_AF_PC1_TMS GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pc2_values GPIO_AF_PC2 Values + * @brief GPIO PC2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 98 | + * NFBGA-212 | D14 | +@{*/ +/** JTAG TDI */ +#define GPIO_AF_PC2_TDI GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pc3_values GPIO_AF_PC3 Values + * @brief GPIO PC3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 97 | + * NFBGA-212 | C14 | +@{*/ +/** JTAG TDO and SWO */ +#define GPIO_AF_PC3_TDO GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pc4_values GPIO_AF_PC4 Values + * @brief GPIO PC4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 25 | + * NFBGA-212 | M2 | +@{*/ +/** UART module 7 receive */ +#define GPIO_AF_PC4_U7RX GPIO_AF1 +/** 16- and 32-bit Timer 7 capture, compare, or PWM 0 */ +#define GPIO_AF_PC4_T7CCP0 GPIO_AF3 +/** EPI module 0 signal 7 */ +#define GPIO_AF_PC4_EPI0S7 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pc5_values GPIO_AF_PC5 Values + * @brief GPIO PC5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 24 | + * NFBGA-212 | M1 | +@{*/ +/** UART module 7 transmit */ +#define GPIO_AF_PC5_U7TX GPIO_AF1 +/** 16- and 32-bit Timer 7 capture, compare, or PWM 1 */ +#define GPIO_AF_PC5_T7CCP1 GPIO_AF3 +/** Buffered version of the 32.768-kHz clock of the Hibernation module */ +#define GPIO_AF_PC5_RTCCLK GPIO_AF7 +/** EPI module 0 signal 6 */ +#define GPIO_AF_PC5_EPI0S6 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pc6_values GPIO_AF_PC6 Values + * @brief GPIO PC6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 22 | + * NFBGA-212 | L2 | +@{*/ +/** UART module 5 receive */ +#define GPIO_AF_PC6_U5RX GPIO_AF1 +/** EPI module 0 signal 5 */ +#define GPIO_AF_PC6_EPI0S5 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pc7_values GPIO_AF_PC7 Values + * @brief GPIO PC7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 22 | + * NFBGA-212 | K3 | +@{*/ +/** UART module 5 transmit */ +#define GPIO_AF_PC7_U5TX GPIO_AF1 +/** EPI module 0 signal 4 */ +#define GPIO_AF_PC7_EPI0S4 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd0_values GPIO_AF_PD0 Values + * @brief GPIO PD0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 1 | + * NFBGA-212 | C2 | +@{*/ +/** I2C module 7 clock */ +#define GPIO_AF_PD0_I2C7SCL GPIO_AF2 +/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ +#define GPIO_AF_PD0_T0CCP0 GPIO_AF3 +/** Analog comparator 0 output */ +#define GPIO_AF_PD0_C0O GPIO_AF5 +/** SSI Module 2 bidirectional data pin 1 */ +#define GPIO_AF_PD0_SSI2XDAT1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd1_values GPIO_AF_PD1 Values + * @brief GPIO PD1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 2 | + * NFBGA-212 | C1 | +@{*/ +/** I2C module 7 data */ +#define GPIO_AF_PD1_I2C7SDA GPIO_AF2 +/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ +#define GPIO_AF_PD1_T0CCP1 GPIO_AF3 +/** Analog comparator 1 output */ +#define GPIO_AF_PD1_C1O GPIO_AF5 +/** SSI Module 2 bidirectional data pin 0 */ +#define GPIO_AF_PD1_SSI2XDAT0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd2_values GPIO_AF_PD2 Values + * @brief GPIO PD2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 3 | + * NFBGA-212 | D2 | +@{*/ +/** I2C module 8 clock */ +#define GPIO_AF_PD2_I2C8SCL GPIO_AF2 +/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ +#define GPIO_AF_PD2_T1CCP0 GPIO_AF3 +/** Analog comparator 2 output */ +#define GPIO_AF_PD2_C2O GPIO_AF5 +/** SSI module 2 frame signal */ +#define GPIO_AF_PD2_SSI2FSS GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd3_values GPIO_AF_PD3 Values + * @brief GPIO PD3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 4 | + * NFBGA-212 | D1 | +@{*/ +/** I2C module 8 data */ +#define GPIO_AF_PD3_I2C8SDA GPIO_AF2 +/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ +#define GPIO_AF_PD3_T1CCP1 GPIO_AF3 +/** SSI module 2 clock */ +#define GPIO_AF_PD3_SSI2CLK GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd4_values GPIO_AF_PD4 Values + * @brief GPIO PD4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 125 | + * NFBGA-212 | A4 | +@{*/ +/** UART module 2 receive */ +#define GPIO_AF_PD4_U2RX GPIO_AF1 +/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ +#define GPIO_AF_PD4_T3CCP0 GPIO_AF3 +/** SSI Module 1 bidirectional data pin 2 */ +#define GPIO_AF_PD4_SSI1XDAT2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd5_values GPIO_AF_PD5 Values + * @brief GPIO PD5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 126 | + * NFBGA-212 | B4 | +@{*/ +/** UART module 2 transmit */ +#define GPIO_AF_PD5_U2TX GPIO_AF1 +/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ +#define GPIO_AF_PD5_T3CCP1 GPIO_AF3 +/** SSI Module 1 bidirectional data pin 3 */ +#define GPIO_AF_PD5_SSI1XDAT3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd6_values GPIO_AF_PD6 Values + * @brief GPIO PD6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 127 | + * NFBGA-212 | B3 | +@{*/ +/** UART module 2 request to send modem flow control output line */ +#define GPIO_AF_PD6_U2RTS GPIO_AF1 +/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ +#define GPIO_AF_PD6_T4CCP0 GPIO_AF3 +/** USB Control an external power source in host mode */ +#define GPIO_AF_PD6_USB0EPEN GPIO_AF5 +/** SSI Module 2 bidirectional data pin 3 */ +#define GPIO_AF_PD6_SSI2XDAT3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pd7_values GPIO_AF_PD7 Values + * @brief GPIO PD7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 128 | + * NFBGA-212 | B2 | +@{*/ +/** UART module 2 clear to send modem flow control input signal */ +#define GPIO_AF_PD7_U2CTS GPIO_AF1 +/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ +#define GPIO_AF_PD7_T4CCP1 GPIO_AF3 +/** USB Power Fault input in host mode */ +#define GPIO_AF_PD7_USB0PFLT GPIO_AF5 +/** Nonmaskable interrupt */ +#define GPIO_AF_PD7_NMI GPIO_AF8 +/** SSI Module 2 bidirectional data pin 2 */ +#define GPIO_AF_PD7_SSI2XDAT2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pe0_values GPIO_AF_PE0 Values + * @brief GPIO PE0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 15 | + * NFBGA-212 | H3 | +@{*/ +/** UART module 1 request to send modem flow control output line */ +#define GPIO_AF_PE0_U1RTS GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pe1_values GPIO_AF_PE1 Values + * @brief GPIO PE1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 14 | + * NFBGA-212 | H2 | +@{*/ +/** UART module 1 data set ready modem output control line */ +#define GPIO_AF_PE1_U1DSR GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pe2_values GPIO_AF_PE2 Values + * @brief GPIO PE2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 13 | + * NFBGA-212 | G1 | +@{*/ +/** UART module 1 data carrier detect modem status input signal */ +#define GPIO_AF_PE2_U1DCD GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pe3_values GPIO_AF_PE3 Values + * @brief GPIO PE3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 12 | + * NFBGA-212 | G2 | +@{*/ +/** UART module 1 data terminal ready modem status input signal */ +#define GPIO_AF_PE3_U1DTR GPIO_AF1 +/** 1-Wire single bus pin */ +#define GPIO_AF_PE3_OWIRE GPIO_AF5 +/**@}*/ + +/** @defgroup gpio_af_pe4_values GPIO_AF_PE4 Values + * @brief GPIO PE4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 123 | + * NFBGA-212 | A5 | +@{*/ +/** UART module 1 ring indicator modem status input signal */ +#define GPIO_AF_PE4_U1RI GPIO_AF1 +/** SSI Module 1 bidirectional data pin 0 */ +#define GPIO_AF_PE4_SSI1XDAT0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pe5_values GPIO_AF_PE5 Values + * @brief GPIO PE5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 124 | + * NFBGA-212 | B5 | +@{*/ +/** SSI Module 1 bidirectional data pin 1 */ +#define GPIO_AF_PE5_SSI1XDAT1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pe6_values GPIO_AF_PE6 Values + * @brief GPIO PE6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | A7 | +@{*/ +/** UART module 0 clear to send modem flow control input signal */ +#define GPIO_AF_PE6_U0CTS GPIO_AF1 +/** I2C module 9 clock */ +#define GPIO_AF_PE6_I2C9SCL GPIO_AF2 +/**@}*/ + +/** @defgroup gpio_af_pe7_values GPIO_AF_PE7 Values + * @brief GPIO PE7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | B7 | +@{*/ +/** UART module 0 request to send modem flow control output signal */ +#define GPIO_AF_PE7_U0RTS GPIO_AF1 +/** I2C module 9 data */ +#define GPIO_AF_PE7_I2C9SDA GPIO_AF2 +/** Nonmaskable interrupt */ +#define GPIO_AF_PE7_NMI GPIO_AF8 +/**@}*/ + +/** @defgroup gpio_af_pf0_values GPIO_AF_PF0 Values + * @brief GPIO PF0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 42 | + * NFBGA-212 | U6 | +@{*/ +/** Ethernet 0 LED 0 */ +#define GPIO_AF_PF0_EN0LED0 GPIO_AF5 +/** Motion control module 0 PWM 0 */ +#define GPIO_AF_PF0_M0PWM0 GPIO_AF6 +/** SSI Module 3 bidirectional data pin 1 */ +#define GPIO_AF_PF0_SSI3XDAT1 GPIO_AF14 +/** Trace data 2 */ +#define GPIO_AF_PF0_TRD2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pf1_values GPIO_AF_PF1 Values + * @brief GPIO PF1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 43 | + * NFBGA-212 | V6 | +@{*/ +/** Ethernet 0 LED 2 */ +#define GPIO_AF_PF1_EN0LED2 GPIO_AF5 +/** Motion control module 0 PWM 1 */ +#define GPIO_AF_PF1_M0PWM1 GPIO_AF6 +/** SSI Module 3 bidirectional data pin 0 */ +#define GPIO_AF_PF1_SSI3XDAT0 GPIO_AF14 +/** Trace data 1 */ +#define GPIO_AF_PF1_TRD1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pf2_values GPIO_AF_PF2 Values + * @brief GPIO PF2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 44 | + * NFBGA-212 | W6 | +@{*/ +/** Ethernet 0 management data clock */ +#define GPIO_AF_PF2_EN0MDC GPIO_AF5 +/** Motion control module 0 PWM 2 */ +#define GPIO_AF_PF2_M0PWM2 GPIO_AF6 +/** SSI module 3 frame signal */ +#define GPIO_AF_PF2_SSI3FSS GPIO_AF14 +/** Trace data 0 */ +#define GPIO_AF_PF2_TRD0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pf3_values GPIO_AF_PF3 Values + * @brief GPIO PF3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 45 | + * NFBGA-212 | T7 | +@{*/ +/** Ethernet 0 management data input/output signal */ +#define GPIO_AF_PF3_EN0MDIO GPIO_AF5 +/** Motion control module 0 PWM 3 */ +#define GPIO_AF_PF3_M0PWM3 GPIO_AF6 +/** SSI module 3 clock */ +#define GPIO_AF_PF3_SSI3CLK GPIO_AF14 +/** Trace clock */ +#define GPIO_AF_PF3_TRCLK GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pf4_values GPIO_AF_PF4 Values + * @brief GPIO PF4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 46 | + * NFBGA-212 | V7 | +@{*/ +/** Ethernet 0 LED 1 */ +#define GPIO_AF_PF4_EN0LED1 GPIO_AF5 +/** Motion control module 0 PWM fault 0 */ +#define GPIO_AF_PF4_M0FAULT0 GPIO_AF6 +/** SSI Module 3 bidirectional data pin 2 */ +#define GPIO_AF_PF4_SSI3XDAT2 GPIO_AF14 +/** Trace data 3 */ +#define GPIO_AF_PF4_TRD3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pf5_values GPIO_AF_PF5 Values + * @brief GPIO PF5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | W7 | +@{*/ +/** SSI Module 3 bidirectional data pin 3 */ +#define GPIO_AF_PF5_SSI3XDAT3 GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pf6_values GPIO_AF_PF6 Values + * @brief GPIO PF6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | T8 | +@{*/ +/** LCD memory clock, secondary chip select (CS1), or secondary enable (E1) */ +#define GPIO_AF_PF6_LCDMCLK GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pf7_values GPIO_AF_PF7 Values + * @brief GPIO PF7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | U8 | +@{*/ +/** LCD data pin 2 input/output */ +#define GPIO_AF_PF7_LCDDATA02 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg0_values GPIO_AF_PG0 Values + * @brief GPIO PG0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 49 | + * NFBGA-212 | N15 | +@{*/ +/** I2C module 1 clock */ +#define GPIO_AF_PG0_I2C1SCL GPIO_AF2 +/** Ethernet 0 pulse-per-second (PPS) output */ +#define GPIO_AF_PG0_EN0PPS GPIO_AF5 +/** Motion control module 0 PWM 4 */ +#define GPIO_AF_PG0_M0PWM4 GPIO_AF6 +/** EPI module 0 signal 11 */ +#define GPIO_AF_PG0_EPI0S11 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg1_values GPIO_AF_PG1 Values + * @brief GPIO PG1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 50 | + * NFBGA-212 | T14 | +@{*/ +/** I2C module 1 data */ +#define GPIO_AF_PG1_I2C1SDA GPIO_AF2 +/** Motion control module 0 PWM 5 */ +#define GPIO_AF_PG1_M0PWM5 GPIO_AF6 +/** EPI module 0 signal 10 */ +#define GPIO_AF_PG1_EPI0S10 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg2_values GPIO_AF_PG2 Values + * @brief GPIO PG2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | V11 | +@{*/ +/** I2C module 2 clock */ +#define GPIO_AF_PG2_I2C2SCL GPIO_AF2 +/** Ethernet 0 transmit clock */ +#define GPIO_AF_PG2_EN0TXCK GPIO_AF14 +/** SSI Module 2 bidirectional data pin 3 */ +#define GPIO_AF_PG2_SSI2XDAT3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg3_values GPIO_AF_PG3 Values + * @brief GPIO PG3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | M16 | +@{*/ +/** I2C module 2 data */ +#define GPIO_AF_PG3_I2C2SDA GPIO_AF2 +/** Ethernet 0 transmit enable */ +#define GPIO_AF_PG3_EN0TXEN GPIO_AF14 +/** SSI Module 2 bidirectional data pin 2 */ +#define GPIO_AF_PG3_SSI2XDAT2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg4_values GPIO_AF_PG4 Values + * @brief GPIO PG4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | K17 | +@{*/ +/** UART module 0 clear to send modem flow control input signal */ +#define GPIO_AF_PG4_U0CTS GPIO_AF1 +/** I2C module 3 clock */ +#define GPIO_AF_PG4_I2C3SCL GPIO_AF2 +/** 1-Wire single bus pin */ +#define GPIO_AF_PG4_OWIRE GPIO_AF5 +/** Ethernet 0 transmit data 0 */ +#define GPIO_AF_PG4_EN0TXD0 GPIO_AF14 +/** SSI Module 2 bidirectional data pin 1 */ +#define GPIO_AF_PG4_SSI2XDAT1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg5_values GPIO_AF_PG5 Values + * @brief GPIO PG5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | K15 | +@{*/ +/** UART module 0 request to send modem flow control output signal */ +#define GPIO_AF_PG5_U0RTS GPIO_AF1 +/** I2C module 3 data */ +#define GPIO_AF_PG5_I2C3SDA GPIO_AF2 +/** 1-Wire optional second signal to be used as output */ +#define GPIO_AF_PG5_OWALT GPIO_AF5 +/** Ethernet 0 transmit data 1 */ +#define GPIO_AF_PG5_EN0TXD1 GPIO_AF14 +/** SSI Module 2 bidirectional data pin 0 */ +#define GPIO_AF_PG5_SSI2XDAT0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg6_values GPIO_AF_PG6 Values + * @brief GPIO PG6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | V12 | +@{*/ +/** I2C module 4 clock */ +#define GPIO_AF_PG6_I2C4SCL GPIO_AF2 +/** 1-Wire single bus pin */ +#define GPIO_AF_PG6_OWIRE GPIO_AF5 +/** Ethernet 0 receive error */ +#define GPIO_AF_PG6_EN0RXER GPIO_AF14 +/** SSI module 2 frame signal */ +#define GPIO_AF_PG6_SSI2FSS GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pg7_values GPIO_AF_PG7 Values + * @brief GPIO PG7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | U14 | +@{*/ +/** I2C module 4 data */ +#define GPIO_AF_PG7_I2C4SDA GPIO_AF2 +/** 1-Wire single bus pin */ +#define GPIO_AF_PG7_OWIRE GPIO_AF5 +/** Ethernet 0 receive data valid */ +#define GPIO_AF_PG7_EN0RXDV GPIO_AF14 +/** SSI module 2 clock */ +#define GPIO_AF_PG7_SSI2CLK GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ph0_values GPIO_AF_PH0 Values + * @brief GPIO PH0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 29 | + * NFBGA-212 | P4 | +@{*/ +/** UART module 0 request to send modem flow control output signal */ +#define GPIO_AF_PH0_U0RTS GPIO_AF1 +/** EPI module 0 signal 0 */ +#define GPIO_AF_PH0_EPI0S0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ph1_values GPIO_AF_PH1 Values + * @brief GPIO PH1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 30 | + * NFBGA-212 | R2 | +@{*/ +/** UART module 0 clear to send modem flow control input signal */ +#define GPIO_AF_PH1_U0CTS GPIO_AF1 +/** EPI module 0 signal 1 */ +#define GPIO_AF_PH1_EPI0S1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ph2_values GPIO_AF_PH2 Values + * @brief GPIO PH2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 31 | + * NFBGA-212 | R1 | +@{*/ +/** UART module 0 data carrier detect modem status input signal */ +#define GPIO_AF_PH2_U0DCD GPIO_AF1 +/** EPI module 0 signal 2 */ +#define GPIO_AF_PH2_EPI0S2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ph3_values GPIO_AF_PH3 Values + * @brief GPIO PH3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 32 | + * NFBGA-212 | T1 | +@{*/ +/** UART module 0 data set ready modem output control line */ +#define GPIO_AF_PH3_U0DSR GPIO_AF1 +/** EPI module 0 signal 3 */ +#define GPIO_AF_PH3_EPI0S3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ph4_values GPIO_AF_PH4 Values + * @brief GPIO PH4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | R3 | +@{*/ +/** UART module 0 data terminal ready modem status input signal */ +#define GPIO_AF_PH4_U0DTR GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_ph5_values GPIO_AF_PH5 Values + * @brief GPIO PH5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | T2 | +@{*/ +/** UART module 0 ring indicator modem status input signal */ +#define GPIO_AF_PH5_U0RI GPIO_AF1 +/** Ethernet 0 pulse-per-second (PPS) output */ +#define GPIO_AF_PH5_EN0PPS GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ph6_values GPIO_AF_PH6 Values + * @brief GPIO PH6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | U2 | +@{*/ +/** UART module 5 receive */ +#define GPIO_AF_PH6_U5RX GPIO_AF1 +/** UART module 7 receive */ +#define GPIO_AF_PH6_U7RX GPIO_AF2 +/**@}*/ + +/** @defgroup gpio_af_ph7_values GPIO_AF_PH7 Values + * @brief GPIO PH7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | V2 | +@{*/ +/** UART module 5 transmit */ +#define GPIO_AF_PH7_U5TX GPIO_AF1 +/** UART module 7 transmit */ +#define GPIO_AF_PH7_U7TX GPIO_AF2 +/**@}*/ + +/** @defgroup gpio_af_pj0_values GPIO_AF_PJ0 Values + * @brief GPIO PJ0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 116 | + * NFBGA-212 | C8 | +@{*/ +/** UART module 3 receive */ +#define GPIO_AF_PJ0_U3RX GPIO_AF1 +/** Ethernet 0 pulse-per-second (PPS) output */ +#define GPIO_AF_PJ0_EN0PPS GPIO_AF5 +/**@}*/ + +/** @defgroup gpio_af_pj1_values GPIO_AF_PJ1 Values + * @brief GPIO PJ1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 117 | + * NFBGA-212 | E7 | +@{*/ +/** UART module 3 transmit */ +#define GPIO_AF_PJ1_U3TX GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pj2_values GPIO_AF_PJ2 Values + * @brief GPIO PJ2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | H17 | +@{*/ +/** UART module 2 request to send modem flow control output line */ +#define GPIO_AF_PJ2_U2RTS GPIO_AF1 +/** LCD data pin 14 input/output */ +#define GPIO_AF_PJ2_LCDDATA14 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pj3_values GPIO_AF_PJ3 Values + * @brief GPIO PJ3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | F16 | +@{*/ +/** UART module 2 clear to send modem flow control input signal */ +#define GPIO_AF_PJ3_U2CTS GPIO_AF1 +/** LCD data pin 15 input/output */ +#define GPIO_AF_PJ3_LCDDATA15 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pj4_values GPIO_AF_PJ4 Values + * @brief GPIO PJ4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | F18 | +@{*/ +/** UART module 3 request to send modem flow control output line */ +#define GPIO_AF_PJ4_U3RTS GPIO_AF1 +/** LCD data pin 16 output */ +#define GPIO_AF_PJ4_LCDDATA16 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pj5_values GPIO_AF_PJ5 Values + * @brief GPIO PJ5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | E17 | +@{*/ +/** UART module 3 clear to send modem flow control input signal */ +#define GPIO_AF_PJ5_U3CTS GPIO_AF1 +/** LCD data pin 17 output */ +#define GPIO_AF_PJ5_LCDDATA17 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pj6_values GPIO_AF_PJ6 Values + * @brief GPIO PJ6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | N1 | +@{*/ +/** UART module 4 request to send modem flow control output line */ +#define GPIO_AF_PJ6_U4RTS GPIO_AF1 +/** LCD AC bias or latch enable in raster mode */ +#define GPIO_AF_PJ6_LCDAC GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pj7_values GPIO_AF_PJ7 Values + * @brief GPIO PJ7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | K5 | +@{*/ +/** UART module 4 clear to send modem flow control input signal */ +#define GPIO_AF_PJ7_U4CTS GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pk0_values GPIO_AF_PK0 Values + * @brief GPIO PK0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 18 | + * NFBGA-212 | J1 | +@{*/ +/** UART module 4 receive */ +#define GPIO_AF_PK0_U4RX GPIO_AF1 +/** EPI module 0 signal 0 */ +#define GPIO_AF_PK0_EPI0S0 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk1_values GPIO_AF_PK1 Values + * @brief GPIO PK1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 19 | + * NFBGA-212 | J2 | +@{*/ +/** UART module 4 transmit */ +#define GPIO_AF_PK1_U4TX GPIO_AF1 +/** EPI module 0 signal 1 */ +#define GPIO_AF_PK1_EPI0S1 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk2_values GPIO_AF_PK2 Values + * @brief GPIO PK2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 20 | + * NFBGA-212 | K1 | +@{*/ +/** UART module 4 request to send modem flow control output line */ +#define GPIO_AF_PK2_U4RTS GPIO_AF1 +/** EPI module 0 signal 2 */ +#define GPIO_AF_PK2_EPI0S2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk3_values GPIO_AF_PK3 Values + * @brief GPIO PK3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 21 | + * NFBGA-212 | K2 | +@{*/ +/** UART module 4 clear to send modem flow control input signal */ +#define GPIO_AF_PK3_U4CTS GPIO_AF1 +/** EPI module 0 signal 3 */ +#define GPIO_AF_PK3_EPI0S3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk4_values GPIO_AF_PK4 Values + * @brief GPIO PK4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 63 | + * NFBGA-212 | U19 | +@{*/ +/** I2C module 3 clock */ +#define GPIO_AF_PK4_I2C3SCL GPIO_AF2 +/** Ethernet 0 LED 0 */ +#define GPIO_AF_PK4_EN0LED0 GPIO_AF5 +/** Motion control module 0 PWM 6 */ +#define GPIO_AF_PK4_M0PWM6 GPIO_AF6 +/** Ethernet 0 interrupt from the Ethernet PHY */ +#define GPIO_AF_PK4_EN0INTRN GPIO_AF7 +/** Ethernet 0 receive data 3 */ +#define GPIO_AF_PK4_EN0RXD3 GPIO_AF14 +/** EPI module 0 signal 32 */ +#define GPIO_AF_PK4_EPI0S32 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk5_values GPIO_AF_PK5 Values + * @brief GPIO PK5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 62 | + * NFBGA-212 | V17 | +@{*/ +/** I2C module 3 data */ +#define GPIO_AF_PK5_I2C3SDA GPIO_AF2 +/** Ethernet 0 LED 2 */ +#define GPIO_AF_PK5_EN0LED2 GPIO_AF5 +/** Motion control module 0 PWM 7 */ +#define GPIO_AF_PK5_M0PWM7 GPIO_AF6 +/** Ethernet 0 receive data 2 */ +#define GPIO_AF_PK5_EN0RXD2 GPIO_AF14 +/** EPI module 0 signal 31 */ +#define GPIO_AF_PK5_EPI0S31 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk6_values GPIO_AF_PK6 Values + * @brief GPIO PK6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 61 | + * NFBGA-212 | V16 | +@{*/ +/** I2C module 4 clock */ +#define GPIO_AF_PK6_I2C4SCL GPIO_AF2 +/** Ethernet 0 LED 1 */ +#define GPIO_AF_PK6_EN0LED1 GPIO_AF5 +/** Motion control module 0 PWM fault 1 */ +#define GPIO_AF_PK6_M0FAULT1 GPIO_AF6 +/** Ethernet 0 transmit data 2 */ +#define GPIO_AF_PK6_EN0TXD2 GPIO_AF14 +/** EPI module 0 signal 25 */ +#define GPIO_AF_PK6_EPI0S25 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pk7_values GPIO_AF_PK7 Values + * @brief GPIO PK7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 60 | + * NFBGA-212 | W16 | +@{*/ +/** UART module 0 ring indicator modem status input signal */ +#define GPIO_AF_PK7_U0RI GPIO_AF1 +/** I2C module 4 data */ +#define GPIO_AF_PK7_I2C4SDA GPIO_AF2 +/** Buffered version of the 32.768-kHz clock of the Hibernation module */ +#define GPIO_AF_PK7_RTCCLK GPIO_AF5 +/** Motion control module 0 PWM fault 2 */ +#define GPIO_AF_PK7_M0FAULT2 GPIO_AF6 +/** Ethernet 0 transmit data 3 */ +#define GPIO_AF_PK7_EN0TXD3 GPIO_AF14 +/** EPI module 0 signal 24 */ +#define GPIO_AF_PK7_EPI0S24 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl0_values GPIO_AF_PL0 Values + * @brief GPIO PL0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 81 | + * NFBGA-212 | G16 | +@{*/ +/** I2C module 2 data */ +#define GPIO_AF_PL0_I2C2SDA GPIO_AF2 +/** Motion control module 0 PWM fault 3 */ +#define GPIO_AF_PL0_M0FAULT3 GPIO_AF6 +/** USB data 0 */ +#define GPIO_AF_PL0_USB0D0 GPIO_AF14 +/** EPI module 0 signal 16 */ +#define GPIO_AF_PL0_EPI0S16 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl1_values GPIO_AF_PL1 Values + * @brief GPIO PL1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 82 | + * NFBGA-212 | H19 | +@{*/ +/** I2C module 2 clock */ +#define GPIO_AF_PL1_I2C2SCL GPIO_AF2 +/** QEI module 0 phase A */ +#define GPIO_AF_PL1_PHA0 GPIO_AF6 +/** USB data 1 */ +#define GPIO_AF_PL1_USB0D1 GPIO_AF14 +/** EPI module 0 signal 17 */ +#define GPIO_AF_PL1_EPI0S17 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl2_values GPIO_AF_PL2 Values + * @brief GPIO PL2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 83 | + * NFBGA-212 | G18 | +@{*/ +/** Analog comparator 0 output */ +#define GPIO_AF_PL2_C0O GPIO_AF5 +/** QEI module 0 phase B */ +#define GPIO_AF_PL2_PHB0 GPIO_AF6 +/** USB data 2 */ +#define GPIO_AF_PL2_USB0D2 GPIO_AF14 +/** EPI module 0 signal 18 */ +#define GPIO_AF_PL2_EPI0S18 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl3_values GPIO_AF_PL3 Values + * @brief GPIO PL3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 84 | + * NFBGA-212 | J18 | +@{*/ +/** Analog comparator 1 output */ +#define GPIO_AF_PL3_C1O GPIO_AF5 +/** QEI module 0 index */ +#define GPIO_AF_PL3_IDX0 GPIO_AF6 +/** USB data 3 */ +#define GPIO_AF_PL3_USB0D3 GPIO_AF14 +/** EPI module 0 signal 19 */ +#define GPIO_AF_PL3_EPI0S19 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl4_values GPIO_AF_PL4 Values + * @brief GPIO PL4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 85 | + * NFBGA-212 | H18 | +@{*/ +/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ +#define GPIO_AF_PL4_T0CCP0 GPIO_AF3 +/** USB data 4 */ +#define GPIO_AF_PL4_USB0D4 GPIO_AF14 +/** EPI module 0 signal 26 */ +#define GPIO_AF_PL4_EPI0S26 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl5_values GPIO_AF_PL5 Values + * @brief GPIO PL5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 86 | + * NFBGA-212 | G19 | +@{*/ +/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ +#define GPIO_AF_PL5_T0CCP1 GPIO_AF3 +/** USB data 5 */ +#define GPIO_AF_PL5_USB0D5 GPIO_AF14 +/** EPI module 0 signal 33 */ +#define GPIO_AF_PL5_EPI0S33 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pl6_values GPIO_AF_PL6 Values + * @brief GPIO PL6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 94 | + * NFBGA-212 | C18 | +@{*/ +/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ +#define GPIO_AF_PL6_T1CCP0 GPIO_AF3 +/**@}*/ + +/** @defgroup gpio_af_pl7_values GPIO_AF_PL7 Values + * @brief GPIO PL7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 93 | + * NFBGA-212 | B18 | +@{*/ +/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ +#define GPIO_AF_PL7_T1CCP1 GPIO_AF3 +/**@}*/ + +/** @defgroup gpio_af_pm0_values GPIO_AF_PM0 Values + * @brief GPIO PM0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 78 | + * NFBGA-212 | K18 | +@{*/ +/** 16- and 32-bit Timer 2 capture, compare, or PWM 0 */ +#define GPIO_AF_PM0_T2CCP0 GPIO_AF3 +/** EPI module 0 signal 15 */ +#define GPIO_AF_PM0_EPI0S15 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pm1_values GPIO_AF_PM1 Values + * @brief GPIO PM1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 77 | + * NFBGA-212 | K19 | +@{*/ +/** 16- and 32-bit Timer 2 capture, compare, or PWM 1 */ +#define GPIO_AF_PM1_T2CCP1 GPIO_AF3 +/** EPI module 0 signal 14 */ +#define GPIO_AF_PM1_EPI0S14 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pm2_values GPIO_AF_PM2 Values + * @brief GPIO PM2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 76 | + * NFBGA-212 | L18 | +@{*/ +/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ +#define GPIO_AF_PM2_T3CCP0 GPIO_AF3 +/** EPI module 0 signal 13 */ +#define GPIO_AF_PM2_EPI0S13 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pm3_values GPIO_AF_PM3 Values + * @brief GPIO PM3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 75 | + * NFBGA-212 | L19 | +@{*/ +/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ +#define GPIO_AF_PM3_T3CCP1 GPIO_AF3 +/** EPI module 0 signal 12 */ +#define GPIO_AF_PM3_EPI0S12 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pm4_values GPIO_AF_PM4 Values + * @brief GPIO PM4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 74 | + * NFBGA-212 | M18 | +@{*/ +/** UART module 0 clear to send modem flow control input signal */ +#define GPIO_AF_PM4_U0CTS GPIO_AF1 +/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ +#define GPIO_AF_PM4_T4CCP0 GPIO_AF3 +/** Ethernet 0 reference clock */ +#define GPIO_AF_PM4_EN0RREF_CLK GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pm5_values GPIO_AF_PM5 Values + * @brief GPIO PM5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 73 | + * NFBGA-212 | G15 | +@{*/ +/** UART module 0 data carrier detect modem status input signal */ +#define GPIO_AF_PM5_U0DCD GPIO_AF1 +/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ +#define GPIO_AF_PM5_T4CCP1 GPIO_AF3 +/**@}*/ + +/** @defgroup gpio_af_pm6_values GPIO_AF_PM6 Values + * @brief GPIO PM6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 72 | + * NFBGA-212 | N19 | +@{*/ +/** UART module 0 data set ready modem output control line */ +#define GPIO_AF_PM6_U0DSR GPIO_AF1 +/** 16- and 32-bit Timer 5 capture, compare, or PWM 0 */ +#define GPIO_AF_PM6_T5CCP0 GPIO_AF3 +/** Ethernet 0 carrier sense */ +#define GPIO_AF_PM6_EN0CRS GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pm7_values GPIO_AF_PM7 Values + * @brief GPIO PM7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 71 | + * NFBGA-212 | N18 | +@{*/ +/** UART module 0 ring indicator modem status input signal */ +#define GPIO_AF_PM7_U0RI GPIO_AF1 +/** 16- and 32-bit Timer 5 capture, compare, or PWM 1 */ +#define GPIO_AF_PM7_T5CCP1 GPIO_AF3 +/** Ethernet 0 collision detect */ +#define GPIO_AF_PM7_EN0COL GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pn0_values GPIO_AF_PN0 Values + * @brief GPIO PN0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 107 | + * NFBGA-212 | C10 | +@{*/ +/** UART module 1 request to send modem flow control output line */ +#define GPIO_AF_PN0_U1RTS GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pn1_values GPIO_AF_PN1 Values + * @brief GPIO PN1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 108 | + * NFBGA-212 | B11 | +@{*/ +/** UART module 1 clear to send modem flow control input signal */ +#define GPIO_AF_PN1_U1CTS GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pn2_values GPIO_AF_PN2 Values + * @brief GPIO PN2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 109 | + * NFBGA-212 | A11 | +@{*/ +/** UART module 1 data carrier detect modem status input signal */ +#define GPIO_AF_PN2_U1DCD GPIO_AF1 +/** UART module 2 request to send modem flow control output line */ +#define GPIO_AF_PN2_U2RTS GPIO_AF2 +/** EPI module 0 signal 29 */ +#define GPIO_AF_PN2_EPI0S29 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pn3_values GPIO_AF_PN3 Values + * @brief GPIO PN3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 110 | + * NFBGA-212 | B10 | +@{*/ +/** UART module 1 data set ready modem output control line */ +#define GPIO_AF_PN3_U1DSR GPIO_AF1 +/** UART module 2 clear to send modem flow control input signal */ +#define GPIO_AF_PN3_U2CTS GPIO_AF2 +/** EPI module 0 signal 30 */ +#define GPIO_AF_PN3_EPI0S30 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pn4_values GPIO_AF_PN4 Values + * @brief GPIO PN4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 111 | + * NFBGA-212 | A10 | +@{*/ +/** UART module 1 data terminal ready modem status input signal */ +#define GPIO_AF_PN4_U1DTR GPIO_AF1 +/** UART module 3 request to send modem flow control output line */ +#define GPIO_AF_PN4_U3RTS GPIO_AF2 +/** I2C module 2 data */ +#define GPIO_AF_PN4_I2C2SDA GPIO_AF3 +/** EPI module 0 signal 34 */ +#define GPIO_AF_PN4_EPI0S34 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pn5_values GPIO_AF_PN5 Values + * @brief GPIO PN5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 112 | + * NFBGA-212 | B9 | +@{*/ +/** UART module 1 ring indicator modem status input signal */ +#define GPIO_AF_PN5_U1RI GPIO_AF1 +/** UART module 3 clear to send modem flow control input signal */ +#define GPIO_AF_PN5_U3CTS GPIO_AF2 +/** I2C module 2 clock */ +#define GPIO_AF_PN5_I2C2SCL GPIO_AF3 +/** EPI module 0 signal 35 */ +#define GPIO_AF_PN5_EPI0S35 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pn6_values GPIO_AF_PN7 Values + * @brief GPIO PN6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | T12 | +@{*/ +/** UART module 4 request to send modem flow control output line */ +#define GPIO_AF_PN6_U4RTS GPIO_AF2 +/** Ethernet 0 transmit error */ +#define GPIO_AF_PN6_EN0TXER GPIO_AF14 +/** LCD data pin 13 input/output */ +#define GPIO_AF_PN6_LCDDATA13 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pn7_values GPIO_AF_PN7 Values + * @brief GPIO PN7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | U12 | +@{*/ +/** UART module 1 request to send modem flow control output line */ +#define GPIO_AF_PN7_U1RTS GPIO_AF1 +/** UART module 4 clear to send modem flow control input signal */ +#define GPIO_AF_PN7_U4CTS GPIO_AF2 +/** LCD data pin 12 input/output */ +#define GPIO_AF_PN7_LCDDATA12 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pp0_values GPIO_AF_PP0 Values + * @brief GPIO PP0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 118 | + * NFBGA-212 | D6 | +@{*/ +/** UART module 6 receive */ +#define GPIO_AF_PP0_U6RX GPIO_AF1 +/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ +#define GPIO_AF_PP0_T6CCP0 GPIO_AF5 +/** Ethernet 0 interrupt from the Ethernet PHY */ +#define GPIO_AF_PP0_EN0INTRN GPIO_AF7 +/** SSI Module 3 bidirectional data pin 2 */ +#define GPIO_AF_PP0_SSI3XDAT2 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pp1_values GPIO_AF_PP1 Values + * @brief GPIO PP1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 119 | + * NFBGA-212 | D7 | +@{*/ +/** UART module 6 transmit */ +#define GPIO_AF_PP1_U6TX GPIO_AF1 +/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ +#define GPIO_AF_PP1_T6CCP1 GPIO_AF5 +/** SSI Module 3 bidirectional data pin 3 */ +#define GPIO_AF_PP1_SSI3XDAT3 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pp2_values GPIO_AF_PP2 Values + * @brief GPIO PP2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 103 | + * NFBGA-212 | B13 | +@{*/ +/** UART module 0 data terminal ready modem status input signal */ +#define GPIO_AF_PP2_U0DTR GPIO_AF1 +/** USB Asserted by the external PHY to throttle all data types */ +#define GPIO_AF_PP2_USB0NXT GPIO_AF14 +/** EPI module 0 signal 29 */ +#define GPIO_AF_PP2_EPI0S29 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pp3_values GPIO_AF_PP3 Values + * @brief GPIO PP3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 104 | + * NFBGA-212 | C12 | +@{*/ +/** UART module 1 clear to send modem flow control input signal */ +#define GPIO_AF_PP3_U1CTS GPIO_AF1 +/** UART module 0 data carrier detect modem status input signal */ +#define GPIO_AF_PP3_U0DCD GPIO_AF2 +/** Buffered version of the 32.768-kHz clock of the Hibernation module */ +#define GPIO_AF_PP3_RTCCLK GPIO_AF7 +/** USB Indicates that the external PHY is able to accept data + * from the USB controller */ +#define GPIO_AF_PP3_USB0DIR GPIO_AF14 +/** EPI module 0 signal 30 */ +#define GPIO_AF_PP3_EPI0S30 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pp4_values GPIO_AF_PP4 Values + * @brief GPIO PP4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 105 | + * NFBGA-212 | D8 | +@{*/ +/** UART module 3 request to send modem flow control output line */ +#define GPIO_AF_PP4_U3RTS GPIO_AF1 +/** UART module 0 data set ready modem output control line */ +#define GPIO_AF_PP4_U0DSR GPIO_AF2 +/** 1-Wire single bus pin */ +#define GPIO_AF_PP4_OWIRE GPIO_AF4 +/** USB data 7 */ +#define GPIO_AF_PP4_USB0D7 GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pp5_values GPIO_AF_PP5 Values + * @brief GPIO PP5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 106 | + * NFBGA-212 | B12 | +@{*/ +/** UART module 3 clear to send modem flow control input signal */ +#define GPIO_AF_PP5_U3CTS GPIO_AF1 +/** I2C module 2 clock */ +#define GPIO_AF_PP5_I2C2SCL GPIO_AF2 +/** 1-Wire optional second signal to be used as output */ +#define GPIO_AF_PP5_OWALT GPIO_AF4 +/** USB data 6 */ +#define GPIO_AF_PP5_USB0D6 GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pp6_values GPIO_AF_PP6 Values + * @brief GPIO PP6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | B8 | +@{*/ +/** UART module 1 data carrier detect modem status input signal */ +#define GPIO_AF_PP6_U1DCD GPIO_AF1 +/** I2C module 2 data */ +#define GPIO_AF_PP6_I2C2SDA GPIO_AF2 +/**@}*/ + +/** @defgroup gpio_af_pp7_values GPIO_AF_PP7 Values + * @brief GPIO PP7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | A8 | +@{*/ +/** 1-Wire single bus pin */ +#define GPIO_AF_PP7_OWIRE GPIO_AF5 +/**@}*/ + +/** @defgroup gpio_af_pq0_values GPIO_AF_PQ0 Values + * @brief GPIO PQ0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 5 | + * NFBGA-212 | E3 | +@{*/ +/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ +#define GPIO_AF_PQ0_T6CCP0 GPIO_AF3 +/** SSI module 3 clock */ +#define GPIO_AF_PQ0_SSI3CLK GPIO_AF14 +/** EPI module 0 signal 20 */ +#define GPIO_AF_PQ0_EPI0S20 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pq1_values GPIO_AF_PQ1 Values + * @brief GPIO PQ1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 6 | + * NFBGA-212 | E2 | +@{*/ +/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ +#define GPIO_AF_PQ1_T6CCP1 GPIO_AF3 +/** SSI module 3 frame signal */ +#define GPIO_AF_PQ1_SSI3FSS GPIO_AF14 +/** EPI module 0 signal 21 */ +#define GPIO_AF_PQ1_EPI0S21 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pq2_values GPIO_AF_PQ2 Values + * @brief GPIO PQ2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 11 | + * NFBGA-212 | H4 | +@{*/ +/** 16- and 32-bit Timer 7 capture, compare, or PWM 0 */ +#define GPIO_AF_PQ2_T7CCP0 GPIO_AF3 +/** SSI Module 3 bidirectional data pin 0 */ +#define GPIO_AF_PQ2_SSI3XDAT0 GPIO_AF14 +/** EPI module 0 signal 22 */ +#define GPIO_AF_PQ2_EPI0S22 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pq3_values GPIO_AF_PQ3 Values + * @brief GPIO PQ3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 27 | + * NFBGA-212 | M4 | +@{*/ +/** 16- and 32-bit Timer 7 capture, compare, or PWM 1 */ +#define GPIO_AF_PQ3_T7CCP1 GPIO_AF3 +/** SSI Module 3 bidirectional data pin 1 */ +#define GPIO_AF_PQ3_SSI3XDAT1 GPIO_AF14 +/** EPI module 0 signal 23 */ +#define GPIO_AF_PQ3_EPI0S23 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pq4_values GPIO_AF_PQ4 Values + * @brief GPIO PQ4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | 102 | + * NFBGA-212 | A13 | +@{*/ +/** UART module 1 receive */ +#define GPIO_AF_PQ4_U1RX GPIO_AF1 +/** Divided reference clock output */ +#define GPIO_AF_PQ4_DIVSCLK GPIO_AF7 +/**@}*/ + +/** @defgroup gpio_af_pq5_values GPIO_AF_PQ5 Values + * @brief GPIO PQ5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | W12 | +@{*/ +/** UART module 1 transmit */ +#define GPIO_AF_PQ5_U1TX GPIO_AF1 +/** Ethernet 0 receive data 0 */ +#define GPIO_AF_PQ5_EN0RXD0 GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pq6_values GPIO_AF_PQ6 Values + * @brief GPIO PQ6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | U15 | +@{*/ +/** UART module 1 data terminal ready modem status input signal */ +#define GPIO_AF_PQ6_U1DTR GPIO_AF1 +/** Ethernet 0 receive data 1 */ +#define GPIO_AF_PQ6_EN0RXD1 GPIO_AF14 +/**@}*/ + +/** @defgroup gpio_af_pq7_values GPIO_AF_PQ7 Values + * @brief GPIO PQ7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | M3 | +@{*/ +/** UART module 1 ring indicator modem status input signal */ +#define GPIO_AF_PQ7_U1RI GPIO_AF1 +/**@}*/ + +/** @defgroup gpio_af_pr0_values GPIO_AF_PR0 Values + * @brief GPIO PR0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | N5 | +@{*/ +/** UART module 4 transmit */ +#define GPIO_AF_PR0_U4TX GPIO_AF1 +/** I2C module 1 clock */ +#define GPIO_AF_PR0_I2C1SCL GPIO_AF2 +/** Motion control module 0 PWM 0 */ +#define GPIO_AF_PR0_M0PWM0 GPIO_AF6 +/** LCD pixel clock in raster mode */ +#define GPIO_AF_PR0_LCDCP GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr1_values GPIO_AF_PR1 Values + * @brief GPIO PR1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | N4 | +@{*/ +/** UART module 4 receive */ +#define GPIO_AF_PR1_U4RX GPIO_AF1 +/** I2C module 1 data */ +#define GPIO_AF_PR1_I2C1SDA GPIO_AF2 +/** Motion control module 0 PWM 1 */ +#define GPIO_AF_PR1_M0PWM1 GPIO_AF6 +/** LCD frame clock or VSYNC in raster mode */ +#define GPIO_AF_PR1_LCDFP GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr2_values GPIO_AF_PR2 Values + * @brief GPIO PR2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | N2 | +@{*/ +/** I2C module 2 clock */ +#define GPIO_AF_PR2_I2C2SCL GPIO_AF2 +/** Motion control module 0 PWM 2 */ +#define GPIO_AF_PR2_M0PWM2 GPIO_AF6 +/** LCD line clock or HSYNC in raster mode */ +#define GPIO_AF_PR2_LCDLP GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr3_values GPIO_AF_PR3 Values + * @brief GPIO PR3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | V8 | +@{*/ +/** I2C module 2 data */ +#define GPIO_AF_PR3_I2C2SDA GPIO_AF2 +/** Motion control module 0 PWM 3 */ +#define GPIO_AF_PR3_M0PWM3 GPIO_AF6 +/** LCD data pin 3 input/output */ +#define GPIO_AF_PR3_LCDDATA03 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr4_values GPIO_AF_PR4 Values + * @brief GPIO PR4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | P3 | +@{*/ +/** I2C module 3 clock */ +#define GPIO_AF_PR4_I2C3SCL GPIO_AF2 +/** 16- and 32-bit Timer 0 capture, compare, or PWM 0 */ +#define GPIO_AF_PR4_T0CCP0 GPIO_AF3 +/** Motion control module 0 PWM 4 */ +#define GPIO_AF_PR4_M0PWM4 GPIO_AF6 +/** LCD data pin 0 input/output */ +#define GPIO_AF_PR4_LCDDATA00 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr5_values GPIO_AF_PR5 Values + * @brief GPIO PR5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | P2 | +@{*/ +/** UART module 1 receive */ +#define GPIO_AF_PR5_U1RX GPIO_AF1 +/** I2C module 3 data */ +#define GPIO_AF_PR5_I2C3SDA GPIO_AF2 +/** 16- and 32-bit Timer 0 capture, compare, or PWM 1 */ +#define GPIO_AF_PR5_T0CCP1 GPIO_AF3 +/** Motion control module 0 PWM 5 */ +#define GPIO_AF_PR5_M0PWM5 GPIO_AF6 +/** LCD data pin 1 input/output */ +#define GPIO_AF_PR5_LCDDATA01 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr6_values GPIO_AF_PR6 Values + * @brief GPIO PR6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | W9 | +@{*/ +/** UART module 1 transmit */ +#define GPIO_AF_PR6_U1TX GPIO_AF1 +/** I2C module 4 clock */ +#define GPIO_AF_PR6_I2C4SCL GPIO_AF2 +/** 16- and 32-bit Timer 1 capture, compare, or PWM 0 */ +#define GPIO_AF_PR6_T1CCP0 GPIO_AF3 +/** Motion control module 0 PWM 6 */ +#define GPIO_AF_PR6_M0PWM6 GPIO_AF6 +/** LCD data pin 4 input/output */ +#define GPIO_AF_PR6_LCDDATA04 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pr7_values GPIO_AF_PR7 Values + * @brief GPIO PR7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | R10 | +@{*/ +/** I2C module 4 data */ +#define GPIO_AF_PR7_I2C4SDA GPIO_AF2 +/** 16- and 32-bit Timer 1 capture, compare, or PWM 1 */ +#define GPIO_AF_PR7_T1CCP1 GPIO_AF3 +/** Motion control module 0 PWM 7 */ +#define GPIO_AF_PR7_M0PWM7 GPIO_AF6 +/** Ethernet 0 transmit enable */ +#define GPIO_AF_PR7_EN0TXEN GPIO_AF14 +/** LCD data pin 5 input/output */ +#define GPIO_AF_PR7_LCDDATA05 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps0_values GPIO_AF_PS0 Values + * @brief GPIO PS0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | D12 | +@{*/ +/** 16- and 32-bit Timer 2 capture, compare, or PWM 0 */ +#define GPIO_AF_PS0_T2CCP0 GPIO_AF3 +/** Motion control module 0 PWM fault 0 */ +#define GPIO_AF_PS0_M0FAULT0 GPIO_AF6 +/** LCD data pin 20 output */ +#define GPIO_AF_PS0_LCDDATA20 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps1_values GPIO_AF_PS1 Values + * @brief GPIO PS1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | D13 | +@{*/ +/** 16- and 32-bit Timer 2 capture, compare, or PWM 1 */ +#define GPIO_AF_PS1_T2CCP1 GPIO_AF3 +/** Motion control module 0 PWM fault 1 */ +#define GPIO_AF_PS1_M0FAULT1 GPIO_AF6 +/** LCD data pin 21 output */ +#define GPIO_AF_PS1_LCDDATA21 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps2_values GPIO_AF_PS2 Values + * @brief GPIO PS2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | B14 | +@{*/ +/** UART module 1 data set ready modem output control line */ +#define GPIO_AF_PS2_U1DSR GPIO_AF1 +/** 16- and 32-bit Timer 3 capture, compare, or PWM 0 */ +#define GPIO_AF_PS2_T3CCP0 GPIO_AF3 +/** Motion control module 0 PWM fault 2 */ +#define GPIO_AF_PS2_M0FAULT2 GPIO_AF6 +/** LCD data pin 22 output */ +#define GPIO_AF_PS2_LCDDATA22 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps3_values GPIO_AF_PS3 Values + * @brief GPIO PS3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | A14 | +@{*/ +/** 16- and 32-bit Timer 3 capture, compare, or PWM 1 */ +#define GPIO_AF_PS3_T3CCP1 GPIO_AF3 +/** Motion control module 0 PWM fault 3 */ +#define GPIO_AF_PS3_M0FAULT3 GPIO_AF6 +/** LCD data pin 23 output */ +#define GPIO_AF_PS3_LCDDATA23 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps4_values GPIO_AF_PS4 Values + * @brief GPIO PS4 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | V9 | +@{*/ +/** 16- and 32-bit Timer 4 capture, compare, or PWM 0 */ +#define GPIO_AF_PS4_T4CCP0 GPIO_AF3 +/** QEI module 0 phase A */ +#define GPIO_AF_PS4_PHA0 GPIO_AF6 +/** Ethernet 0 transmit data 0 */ +#define GPIO_AF_PS4_EN0TXD0 GPIO_AF14 +/** LCD data pin 6 input/output */ +#define GPIO_AF_PS4_LCDDATA06 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps5_values GPIO_AF_PS5 Values + * @brief GPIO PS5 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | T13 | +@{*/ +/** 16- and 32-bit Timer 4 capture, compare, or PWM 1 */ +#define GPIO_AF_PS5_T4CCP1 GPIO_AF3 +/** QEI module 0 phase B */ +#define GPIO_AF_PS5_PHB0 GPIO_AF6 +/** Ethernet 0 transmit data 1 */ +#define GPIO_AF_PS5_EN0TXD1 GPIO_AF14 +/** LCD data pin 7 input/output */ +#define GPIO_AF_PS5_LCDDATA07 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps6_values GPIO_AF_PS6 Values + * @brief GPIO PS6 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | U10 | +@{*/ +/** 16- and 32-bit Timer 5 capture, compare, or PWM 0 */ +#define GPIO_AF_PS6_T5CCP0 GPIO_AF3 +/** QEI module 0 index */ +#define GPIO_AF_PS6_IDX0 GPIO_AF6 +/** Ethernet 0 receive error */ +#define GPIO_AF_PS6_EN0RXER GPIO_AF14 +/** LCD data pin 8 input/output */ +#define GPIO_AF_PS6_LCDDATA08 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_ps7_values GPIO_AF_PS7 Values + * @brief GPIO PS7 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | R13 | +@{*/ +/** 16- and 32-bit Timer 5 capture, compare, or PWM 1 */ +#define GPIO_AF_PS7_T5CCP1 GPIO_AF3 +/** Ethernet 0 receive data valid */ +#define GPIO_AF_PS7_EN0RXDV GPIO_AF14 +/** LCD data pin 9 input/output */ +#define GPIO_AF_PS7_LCDDATA09 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pt0_values GPIO_AF_PT0 Values + * @brief GPIO PT0 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | W10 | +@{*/ +/** 16- and 32-bit Timer 6 capture, compare, or PWM 0 */ +#define GPIO_AF_PT0_T6CCP0 GPIO_AF3 +/** CAN module 0 receive */ +#define GPIO_AF_PT0_CAN0RX GPIO_AF7 +/** Ethernet 0 receive data 0 */ +#define GPIO_AF_PT0_EN0RXD0 GPIO_AF14 +/** LCD data pin 10 input/output */ +#define GPIO_AF_PT0_LCDDATA10 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pt1_values GPIO_AF_PT1 Values + * @brief GPIO PT1 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | V10 | +@{*/ +/** 16- and 32-bit Timer 6 capture, compare, or PWM 1 */ +#define GPIO_AF_PT1_T6CCP1 GPIO_AF3 +/** CAN module 0 transmit */ +#define GPIO_AF_PT1_CAN0TX GPIO_AF7 +/** Ethernet 0 receive data 1 */ +#define GPIO_AF_PT1_EN0RXD1 GPIO_AF14 +/** LCD data pin 11 input/output */ +#define GPIO_AF_PT1_LCDDATA11 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pt2_values GPIO_AF_PT2 Values + * @brief GPIO PT2 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | E18 | +@{*/ +/** 16- and 32-bit Timer 7 capture, compare, or PWM 0 */ +#define GPIO_AF_PT2_T7CCP0 GPIO_AF3 +/** CAN module 1 receive */ +#define GPIO_AF_PT2_CAN1RX GPIO_AF7 +/** LCD data pin 18 output */ +#define GPIO_AF_PT2_LCDDATA18 GPIO_AF15 +/**@}*/ + +/** @defgroup gpio_af_pt3_values GPIO_AF_PT3 Values + * @brief GPIO PT3 Alternate Functions Values + * Package | Pin number | + * ----------- | -------------- | + * TQFP-128 | Not available | + * NFBGA-212 | F17 | +@{*/ +/** 16- and 32-bit Timer 7 capture, compare, or PWM 1 */ +#define GPIO_AF_PT3_T7CCP1 GPIO_AF3 +/** CAN module 1 transmit */ +#define GPIO_AF_PT3_CAN1TX GPIO_AF7 +/** LCD data pin 19 output */ +#define GPIO_AF_PT3_LCDDATA19 GPIO_AF15 +/**@}*/ + +/** @brief GPIO Mode Definitions */ +enum gpio_mode { + GPIO_MODE_OUTPUT, /**< Configure pin as output */ + GPIO_MODE_INPUT, /**< Configure pin as input */ + GPIO_MODE_ANALOG /**< Configure pin as analog function */ +}; + +/** @brief GPIO Pull-Up/Pull-Down Definitions */ +enum gpio_pull_up_down { + GPIO_PUPD_NONE, /**< Do not pull the pin high or low */ + GPIO_PUPD_PULLUP, /**< Pull the pin high */ + GPIO_PUPD_PULLDOWN, /**< Pull the pin low */ +}; + +/** @brief GPIO Output Type Definitions */ +enum gpio_output_type { + GPIO_OTYPE_PP, /**< Push-pull configuration */ + GPIO_OTYPE_OD, /**< Open drain configuration */ +}; + +/** @brief GPIO Drive Strength Definitions */ +enum gpio_drive_strength { + GPIO_DRIVE_2MA, /**< 2mA drive */ + GPIO_DRIVE_4MA, /**< 4mA drive */ + GPIO_DRIVE_6MA, /**< 6mA drive */ + GPIO_DRIVE_8MA, /**< 8mA drive */ + GPIO_DRIVE_10MA, /**< 10mA drive */ + GPIO_DRIVE_12MA /**< 12mA drive */ +}; + +/** @brief GPIO Slew Control Definitions */ +enum gpio_slew_ctl { + GPIO_SLEW_CTL_ENABLE, /**< Slew rate control enable */ + GPIO_SLEW_CTL_DISABLE /**< Slew rate control disable */ +}; + +/** @brief GPIO Trigger Level/Edge Definitions */ +enum gpio_trigger { + GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */ + GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */ + GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */ + GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger */ + GPIO_TRIG_EDGE_BOTH /**< Both edges trigger */ +}; + +BEGIN_DECLS + +void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, + enum gpio_pull_up_down pull_up_down, uint8_t gpios); +void gpio_set_output_options(uint32_t gpioport, enum gpio_output_type otype, + enum gpio_drive_strength drive, + enum gpio_slew_ctl slewctl, + uint8_t gpios); +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios); +void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, + uint8_t gpios); +void gpio_set(uint32_t gpioport, uint8_t gpios); +void gpio_clear(uint32_t gpioport, uint8_t gpios); +uint8_t gpio_get(uint32_t gpioport, uint8_t gpios); +void gpio_toggle(uint32_t gpioport, uint8_t gpios); +uint8_t gpio_port_read(uint32_t gpioport); +void gpio_port_write(uint32_t gpioport, uint8_t data); +void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios); +void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios); +void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios); +uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios); +void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios); + +END_DECLS + +/**@}*/ + +#endif /* MSP432E4_GPIO_H */ diff --git a/include/libopencm3/stm32/adc.h b/include/libopencm3/stm32/adc.h index 2663a4ab..1c3d6662 100644 --- a/include/libopencm3/stm32/adc.h +++ b/include/libopencm3/stm32/adc.h @@ -28,6 +28,8 @@ # include <libopencm3/stm32/f3/adc.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/adc.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/adc.h> #elif defined(STM32L0) # include <libopencm3/stm32/l0/adc.h> #elif defined(STM32L1) diff --git a/include/libopencm3/stm32/common/adc_common_v1_multi.h b/include/libopencm3/stm32/common/adc_common_v1_multi.h new file mode 100644 index 00000000..05a2ac6c --- /dev/null +++ b/include/libopencm3/stm32/common/adc_common_v1_multi.h @@ -0,0 +1,379 @@ +/** @addtogroup adc_defines + +@author @htmlonly © @endhtmlonly 2014 Karl Palsson <karlp@tweak.net.au> + + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Matthew Lai <m@matthewlai.ca> + * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H +The order of header inclusion is important. adc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_ADC_H +/** @endcond */ +#ifndef LIBOPENCM3_ADC_COMMON_V1_MULTI_H +#define LIBOPENCM3_ADC_COMMON_V1_MULTI_H + +#include <libopencm3/stm32/common/adc_common_v1.h> + +/* --- Convenience macros -------------------------------------------------- */ + + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) + +/* --- ADC Channels ------------------------------------------------------- */ + + +/* --- ADC_SR values ------------------------------------------------------- */ + +/** @defgroup adc_sr_values ADC Status Register Flags + * @ingroup adc_defines + *@{*/ + +/* OVR:*//** Overrun */ +#define ADC_SR_OVR (1 << 5) +/**@}*/ + +/* OVRIE: Overrun interrupt enable */ +#define ADC_CR1_OVRIE (1 << 26) + +/* RES[1:0]: Resolution */ +/****************************************************************************/ +/** @defgroup adc_cr1_res ADC Resolution. +@ingroup adc_defines + +@{*/ +#define ADC_CR1_RES_12BIT (0x0 << 24) +#define ADC_CR1_RES_10BIT (0x1 << 24) +#define ADC_CR1_RES_8BIT (0x2 << 24) +#define ADC_CR1_RES_6BIT (0x3 << 24) +/**@}*/ +#define ADC_CR1_RES_MASK (0x3 << 24) +#define ADC_CR1_RES_SHIFT 24 + +/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ + + + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* SWSTART: Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 30) + +/* EXTEN[1:0]: External trigger enable for regular channels. */ +/****************************************************************************/ +#define ADC_CR2_EXTEN_SHIFT 28 +#define ADC_CR2_EXTEN_MASK (0x3 << ADC_CR2_EXTEN_SHIFT) +/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity +@ingroup adc_defines +@{*/ +#define ADC_CR2_EXTEN_DISABLED (0x0 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << ADC_CR2_EXTEN_SHIFT) +/**@}*/ + +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +/* Note: Selection values are family-dependent. */ +#define ADC_CR2_EXTSEL_MASK (0xF << 24) +#define ADC_CR2_EXTSEL_SHIFT 24 + +/* Bit 23 is reserved */ + +/* JSWSTART: Start conversion of injected channels. */ +#define ADC_CR2_JSWSTART (1 << 22) + +/* JEXTEN[1:0]: External trigger enable for injected channels. */ +/****************************************************************************/ +#define ADC_CR2_JEXTEN_SHIFT 20 +#define ADC_CR2_JEXTEN_MASK (0x3 << ADC_CR2_JEXTEN_SHIFT) +/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity +@ingroup adc_defines +@{*/ +#define ADC_CR2_JEXTEN_DISABLED (0x0 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << ADC_CR2_JEXTEN_SHIFT) +/**@}*/ + +/* JEXTSEL[3:0]: External event selection for injected group. */ +/****************************************************************************/ +/* Note: Selection values are family-dependent. */ +#define ADC_CR2_JEXTSEL_SHIFT 16 +#define ADC_CR2_JEXTSEL_MASK (0xF << ADC_CR2_JEXTSEL_SHIFT) + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* EOCS: End of conversion selection. */ +#define ADC_CR2_EOCS (1 << 10) + +/* DDS: DMA disable selection */ +#define ADC_CR2_DDS (1 << 9) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* Note: Bits [7:2] are reserved and must be kept at reset value. */ + +/* CONT: Continuous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + + +/* --- ADC_SMPRx values --------------------------------------------------- */ +/****************************************************************************/ + +#define ADC_SQRx_MASK 0x1f + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) + +/* --- Common Registers ---------------------------------------------------- */ + +/* --- ADC_CSR values (read only images) ------------------------------------ */ + +/* OVR3: Overrun ADC3. */ +#define ADC_CSR_OVR3 (1 << 21) + +/* STRT3: Regular channel start ADC3. */ +#define ADC_CSR_STRT3 (1 << 20) + +/* JSTRT3: Injected channel start ADC3. */ +#define ADC_CSR_JSTRT3 (1 << 19) + +/* JEOC3: Injected channel end of conversion ADC3. */ +#define ADC_CSR_JEOC3 (1 << 18) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_EOC3 (1 << 17) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_AWD3 (1 << 16) + +/* Bits 15:14 Reserved, must be kept at reset value */ + +/* OVR2: Overrun ADC2. */ +#define ADC_CSR_OVR2 (1 << 13) + +/* STRT2: Regular channel start ADC2. */ +#define ADC_CSR_STRT2 (1 << 12) + +/* JSTRT2: Injected channel start ADC2. */ +#define ADC_CSR_JSTRT2 (1 << 11) + +/* JEOC2: Injected channel end of conversion ADC2. */ +#define ADC_CSR_JEOC2 (1 << 10) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_EOC2 (1 << 9) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_AWD2 (1 << 8) + +/* Bits 7:6 Reserved, must be kept at reset value */ + +/* OVR1: Overrun ADC1. */ +#define ADC_CSR_OVR1 (1 << 5) + +/* STRT1: Regular channel start ADC1. */ +#define ADC_CSR_STRT1 (1 << 4) + +/* JSTRT1: Injected channel start ADC1. */ +#define ADC_CSR_JSTRT1 (1 << 3) + +/* JEOC1: Injected channel end of conversion ADC1. */ +#define ADC_CSR_JEOC1 (1 << 2) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_EOC1 (1 << 1) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_AWD1 (1 << 0) + +/* --- ADC_CCR values ------------------------------------------------------ */ + +/* TSVREFE: Temperature sensor and Vrefint enable. */ +#define ADC_CCR_TSVREFE (1 << 23) + +/* VBATE: VBat enable. */ +#define ADC_CCR_VBATE (1 << 22) + +/* Bit 18:21 reserved, must be kept at reset value. */ + +/* DMA: Direct memory access mode for multi ADC mode. */ +/****************************************************************************/ +/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DMA_DISABLE (0x0 << 14) +#define ADC_CCR_DMA_MODE_1 (0x1 << 14) +#define ADC_CCR_DMA_MODE_2 (0x2 << 14) +#define ADC_CCR_DMA_MODE_3 (0x3 << 14) +/**@}*/ +#define ADC_CCR_DMA_MASK (0x3 << 14) +#define ADC_CCR_DMA_SHIFT 14 + +/* DDS: DMA disable selection (for multi-ADC mode). */ +#define ADC_CCR_DDS (1 << 13) + +/* Bit 12 reserved, must be kept at reset value */ + +/* DELAY: Delay between 2 sampling phases. */ +/****************************************************************************/ +/** @defgroup adc_delay ADC Delay between 2 sampling phases +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) +#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) +#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) +#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) +#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) +#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) +#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) +#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) +#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) +#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) +#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) +#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) +#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) +#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) +#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) +#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) +/**@}*/ +#define ADC_CCR_DELAY_MASK (0xf << 8) +#define ADC_CCR_DELAY_SHIFT 8 + +/* Bit 7:5 reserved, must be kept at reset value */ + +/* MULTI: Multi ADC mode selection. */ +/****************************************************************************/ +/** @defgroup adc_multi_mode ADC Multi mode selection +@ingroup adc_defines + +@{*/ + +/** All ADCs independent */ +#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) + +/* Dual modes (ADC1 + ADC2) */ +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) +/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) +/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) +/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ +#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) +/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) + +/* Triple modes (ADC1 + ADC2 + ADC3) */ +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) +/**@}*/ + +#define ADC_CCR_MULTI_MASK (0x1f << 0) +#define ADC_CCR_MULTI_SHIFT 0 + +/* --- ADC_CDR values ------------------------------------------------------ */ + +#define ADC_CDR_DATA2_MASK (0xffff << 16) +#define ADC_CDR_DATA2_SHIFT 16 + +#define ADC_CDR_DATA1_MASK (0xffff << 0) +#define ADC_CDR_DATA1_SHIFT 0 + +BEGIN_DECLS + +void adc_set_clk_prescale(uint32_t prescaler); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_set_resolution(uint32_t adc, uint32_t resolution); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +bool adc_awd(uint32_t adc); +void adc_eoc_after_each(uint32_t adc); +void adc_eoc_after_group(uint32_t adc); +void adc_set_dma_continue(uint32_t adc); +void adc_set_dma_terminate(uint32_t adc); +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + +#endif +/** @cond */ +#endif +/** @endcond */ +/**@}*/ diff --git a/include/libopencm3/stm32/common/adc_common_v2.h b/include/libopencm3/stm32/common/adc_common_v2.h index afe23c39..d46bd496 100644 --- a/include/libopencm3/stm32/common/adc_common_v2.h +++ b/include/libopencm3/stm32/common/adc_common_v2.h @@ -36,138 +36,181 @@ specific memorymap.h header before including this header file.*/ #define LIBOPENCM3_ADC_COMMON_V2_H /* ----- ADC registers -----------------------------------------------------*/ -/* ADC interrupt and status register */ +/** ADC interrupt and status register */ #define ADC_ISR(adc) MMIO32((adc) + 0x00) -/* Interrupt Enable Register */ +/** Interrupt Enable Register */ #define ADC_IER(adc) MMIO32((adc) + 0x04) -/* Control Register */ +/** Control Register */ #define ADC_CR(adc) MMIO32((adc) + 0x08) -/* Configuration Register 1 */ +/** Configuration Register 1 */ #define ADC_CFGR1(adc) MMIO32((adc) + 0x0C) -/* Configuration Register 2 */ +/** Configuration Register 2 */ #define ADC_CFGR2(adc) MMIO32((adc) + 0x10) -/* Sample Time Register 1 */ +/** Sample Time Register 1 */ #define ADC_SMPR1(adc) MMIO32((adc) + 0x14) -/* Watchdog Threshold Register 1*/ +/** Watchdog Threshold Register 1*/ #define ADC_TR1(adc) MMIO32((adc) + 0x20) -/* Regular Data Register */ +/** Regular Data Register */ #define ADC_DR(adc) MMIO32((adc) + 0x40) /* CALFACT for all but f0 :(*/ -/* ADC common (shared) registers */ +/** Common Configuration register */ #define ADC_CCR(adc) MMIO32((adc) + 0x300 + 0x8) /* --- Register values -------------------------------------------------------*/ /* ADC_ISR Values -----------------------------------------------------------*/ +/** @defgroup adc_isr ISR ADC interrupt status register +@{*/ -/* AWD1: Analog watchdog 1 flag */ +/** AWD1: Analog watchdog 1 flag */ #define ADC_ISR_AWD1 (1 << 7) +/** OVR: Overrun flag */ #define ADC_ISR_OVR (1 << 4) +/** EOS: End of sequence conversions flag */ #define ADC_ISR_EOS (1 << 3) // FIXME - move to single/multi here. #define ADC_ISR_EOSEQ ADC_ISR_EOS /* TODO - keep only one? */ +/** EOS: End of regular conversion flag */ #define ADC_ISR_EOC (1 << 2) +/** EOSMP: End of sampling flag */ #define ADC_ISR_EOSMP (1 << 1) +/** ADRDY: Ready flag */ #define ADC_ISR_ADRDY (1 << 0) +/**@}*/ + /* ADC_IER Values -----------------------------------------------------------*/ +/** @defgroup adc_ier IER ADC interrupt enable register +@{*/ -/* AWD1IE: Analog watchdog 1 interrupt enable */ +/** AWD1IE: Analog watchdog 1 interrupt enable */ #define ADC_IER_AWD1IE (1 << 7) -/* OVRIE: Overrun interrupt enable */ +/** OVRIE: Overrun interrupt enable */ #define ADC_IER_OVRIE (1 << 4) -/* EOSIE: End of regular sequence of conversions interrupt enable */ +/** EOSIE: End of regular sequence of conversions interrupt enable */ #define ADC_IER_EOSIE (1 << 3) #define ADC_IER_EOSEQIE ADC_IER_EOSIE /* TODO - keep only one? */ -/* EOCIE: End of regular conversion interrupt enable */ +/** EOCIE: End of regular conversion interrupt enable */ #define ADC_IER_EOCIE (1 << 2) -/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ +/** EOSMPIE: End of sampling flag interrupt enable for regular conversions */ #define ADC_IER_EOSMPIE (1 << 1) -/* ADRDYIE : ADC ready interrupt enable */ +/** ADRDYIE: ADC ready interrupt enable */ #define ADC_IER_ADRDYIE (1 << 0) +/**@}*/ + /* ADC_CR Values -----------------------------------------------------------*/ +/** @defgroup adc_cr CR ADC control register +@{*/ -/* ADCAL: ADC calibration */ +/** ADCAL: ADC calibration */ #define ADC_CR_ADCAL (1 << 31) -/* ADSTP: ADC stop of regular conversion command */ +/** ADSTP: ADC stop of regular conversion command */ #define ADC_CR_ADSTP (1 << 4) -/* ADSTART: ADC start of regular conversion */ +/** ADSTART: ADC start of regular conversion */ #define ADC_CR_ADSTART (1 << 2) -/* ADDIS: ADC disable command */ +/** ADDIS: ADC disable command */ #define ADC_CR_ADDIS (1 << 1) -/* ADEN: ADC enable control */ +/** ADEN: ADC enable control */ #define ADC_CR_ADEN (1 << 0) +/**@}*/ + /* ADC_CFGR1 Values -----------------------------------------------------------*/ +/** @defgroup adc_cfgr1 CFGR1 ADC configuration register 1 +@{*/ -/* AWD1CH[4:0]: Analog watchdog 1 channel selection */ #define ADC_CFGR1_AWD1CH_SHIFT 26 #define ADC_CFGR1_AWD1CH (0x1F << ADC_CFGR1_AWD1CH_SHIFT) +/** AWD1CH: Analog watchdog 1 channel selection */ #define ADC_CFGR1_AWD1CH_VAL(x) ((x) << ADC_CFGR1_AWD1CH_SHIFT) -/* AWD1EN: Analog watchdog 1 enable on regular channels */ +/** AWD1EN: Analog watchdog 1 enable on regular channels */ #define ADC_CFGR1_AWD1EN (1 << 23) - -/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ +/** AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ #define ADC_CFGR1_AWD1SGL (1 << 22) - -/* DISCEN: Discontinuous mode for regular channels */ +/** DISCEN: Discontinuous mode for regular channels */ #define ADC_CFGR1_DISCEN (1 << 16) - -/* AUTDLY: Delayed conversion mode */ +/** AUTDLY: Delayed conversion mode */ #define ADC_CFGR1_AUTDLY (1 << 14) - -/* CONT: Single / continuous conversion mode for regular conversions */ +/** CONT: Single / continuous conversion mode for regular conversions */ #define ADC_CFGR1_CONT (1 << 13) - -/* OVRMOD: Overrun Mode */ +/** OVRMOD: Overrun Mode */ #define ADC_CFGR1_OVRMOD (1 << 12) -/* - * EXTEN[1:0]: External trigger enable and polarity selection for regular - * channels - */ +#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) +/** @defgroup adc_cfgr1_exten EXTEN: External trigger enable and polarity selection for regular channels +@{*/ #define ADC_CFGR1_EXTEN_DISABLED (0x0 << 10) #define ADC_CFGR1_EXTEN_RISING_EDGE (0x1 << 10) #define ADC_CFGR1_EXTEN_FALLING_EDGE (0x2 << 10) #define ADC_CFGR1_EXTEN_BOTH_EDGES (0x3 << 10) +/**@}*/ -#define ADC_CFGR1_EXTEN_MASK (0x3 << 10) - -/* ALIGN: Data alignment */ +/** ALIGN: Data alignment */ #define ADC_CFGR1_ALIGN (1 << 5) -/* RES[1:0]: Data resolution */ +#define ADC_CFGR1_RES_MASK (0x3 << 3) +/** @defgroup adc_cfgr1_res RES: Data resolution +@{*/ #define ADC_CFGR1_RES_12_BIT (0x0 << 3) #define ADC_CFGR1_RES_10_BIT (0x1 << 3) #define ADC_CFGR1_RES_8_BIT (0x2 << 3) #define ADC_CFGR1_RES_6_BIT (0x3 << 3) -#define ADC_CFGR1_RES_MASK (0x3 << 3) +/**@}*/ -/* DMACFG: Direct memory access configuration */ +/** DMACFG: Direct memory access configuration */ #define ADC_CFGR1_DMACFG (1 << 1) -/* DMAEN: Direct memory access enable */ +/** DMAEN: Direct memory access enable */ #define ADC_CFGR1_DMAEN (1 << 0) +/**@}*/ + +/* ADC_SMPR Values -----------------------------------------------------------*/ +/** @defgroup adc_smpr SMPR ADC sample time register +@{*/ + +/**@}*/ + +/* ADC_CFGR2 Values -----------------------------------------------------------*/ +/** @defgroup adc_cfgr2 CFGR2 ADC configuration register 2 +@{*/ + +/**@}*/ + /* ADC_TR1 Values ------------------------------------------------------------*/ +/** @defgroup adc_tr1 TR1 ADC watchdog threshold register 1 +@{*/ #define ADC_TR1_LT_SHIFT 0 +#define ADC_TR1_LT_MASK 0xFFF #define ADC_TR1_LT (0xFFF << ADC_TR1_LT_SHIFT) +/** TR1_LT: analog watchdog 1 threshold low */ #define ADC_TR1_LT_VAL(x) ((x) << ADC_TR1_LT_SHIFT) #define ADC_TR1_HT_SHIFT 16 +#define ADC_TR1_HT_MASK 0xFFF #define ADC_TR1_HT (0xFFF << ADC_TR1_HT_SHIFT) +/** TR1_HT: analog watchdog 1 threshold high */ #define ADC_TR1_HT_VAL(x) ((x) << ADC_TR1_HT_SHIFT) - +/**@}*/ /* ADC_CCR Values -----------------------------------------------------------*/ +/** @defgroup adc_ccr CCR ADC common configuration register +@{*/ + +/** VBATEN: Enable VBAT Channel */ #define ADC_CCR_VBATEN (1 << 24) + +/** TSEN: Enable Temperature Sensor */ #define ADC_CCR_TSEN (1 << 23) + +/** VREFEN: Enable internal Voltage Reference */ #define ADC_CCR_VREFEN (1 << 22) +/**@}*/ /* --- Function prototypes ------------------------------------------------- */ @@ -205,7 +248,8 @@ bool adc_get_overrun_flag(uint32_t adc); void adc_clear_overrun_flag(uint32_t adc); uint32_t adc_read_regular(uint32_t adc); void adc_start_conversion_regular(uint32_t adc); - +void adc_enable_dma_circular_mode(uint32_t adc); +void adc_disable_dma_circular_mode(uint32_t adc); END_DECLS #endif diff --git a/include/libopencm3/stm32/common/adc_common_v2_single.h b/include/libopencm3/stm32/common/adc_common_v2_single.h index 1d6729d1..d2db6dce 100644 --- a/include/libopencm3/stm32/common/adc_common_v2_single.h +++ b/include/libopencm3/stm32/common/adc_common_v2_single.h @@ -48,22 +48,27 @@ specific memorymap.h header before including this header file.*/ /* ----- ADC registers values -----------------------------------------------*/ /* ADC_CFGR1 values */ +/** @addtogroup adc_cfgr1 +@{*/ /** Wait conversion mode */ #define ADC_CFGR1_WAIT (1<<14) /** Auto off mode */ #define ADC_CFGR1_AUTOFF (1 << 15) -/* EXTSEL[2:0]: External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_SHIFT 6 #define ADC_CFGR1_EXTSEL (0x7 << ADC_CFGR1_EXTSEL_SHIFT) +/** EXTSEL[2:0]: External trigger selection for regular group */ #define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) +/** SCANDIR: Scan Sequence Direction: Upwards Scan (0), Downwards(1) */ #define ADC_CFGR1_SCANDIR (1 << 2) +/**@}*/ /* ADC_CHSELR Values --------------------------------------------------------*/ - +/** @addtogroup adc_chselr +@{*/ #define ADC_CHSELR_CHSEL(x) (1 << (x)) - +/**@}*/ /* --- Function prototypes ------------------------------------------------- */ diff --git a/include/libopencm3/stm32/common/crc_common_all.h b/include/libopencm3/stm32/common/crc_common_all.h index f883590c..f0cd13d6 100644 --- a/include/libopencm3/stm32/common/crc_common_all.h +++ b/include/libopencm3/stm32/common/crc_common_all.h @@ -43,6 +43,8 @@ specific memorymap.h header before including this header file.*/ /* Register definitions */ /*****************************************************************************/ +/**@defgroup crc_registers CRC Registers + @{*/ /** CRC_DR Data register */ #define CRC_DR MMIO32(CRC_BASE + 0x00) @@ -51,6 +53,7 @@ specific memorymap.h header before including this header file.*/ /** CRC_CR Control register */ #define CRC_CR MMIO32(CRC_BASE + 0x08) +/*@}*/ /*****************************************************************************/ /* Register values */ diff --git a/include/libopencm3/stm32/common/crc_v2.h b/include/libopencm3/stm32/common/crc_v2.h index 850dc252..515f7570 100644 --- a/include/libopencm3/stm32/common/crc_v2.h +++ b/include/libopencm3/stm32/common/crc_v2.h @@ -27,11 +27,7 @@ The order of header inclusion is important. crc.h includes the device specific memorymap.h header before including this header file.*/ -/** @cond */ -#ifdef LIBOPENCM3_CRC_H -/** @endcond */ -#ifndef LIBOPENCM3_CRC_V2_H -#define LIBOPENCM3_CRC_V2_H +#pragma once /**@{*/ @@ -45,6 +41,8 @@ /* Register definitions */ /*****************************************************************************/ +/** @addtogroup crc_registers CRC Registers +@{*/ /** CRC_DR Data register 8bit wide access */ #define CRC_DR8 MMIO8(CRC_BASE + 0x00) /** CRC_DR Data register 16bit wide access */ @@ -55,6 +53,7 @@ /** CRC_POL CRC Polynomial */ #define CRC_POL MMIO32(CRC_BASE + 0x14) +/**@}*/ /*****************************************************************************/ /* Register values */ @@ -65,29 +64,31 @@ #define CRC_CR_REV_IN_SHIFT 5 #define CRC_CR_REV_IN (3 << CRC_CR_REV_IN_SHIFT) +/** @defgroup crc_rev_in CRC Reverse input options + @{*/ #define CRC_CR_REV_IN_NONE (0 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_BYTE (1 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_HALF (2 << CRC_CR_REV_IN_SHIFT) #define CRC_CR_REV_IN_WORD (3 << CRC_CR_REV_IN_SHIFT) +/**@}*/ #define CRC_CR_POLYSIZE_SHIFT 3 -#define CRC_CR_POLYSIZE (3 << CRC_CR_POLYSIZE_SHIFT) +#define CRC_CR_POLYSIZE (3 << CRC_CR_POLYSIZE_SHIFT) +/** + * @defgroup crc_polysize CRC Polynomial size + * @{ + */ #define CRC_CR_POLYSIZE_32 (0 << CRC_CR_POLYSIZE_SHIFT) #define CRC_CR_POLYSIZE_16 (1 << CRC_CR_POLYSIZE_SHIFT) #define CRC_CR_POLYSIZE_8 (2 << CRC_CR_POLYSIZE_SHIFT) #define CRC_CR_POLYSIZE_7 (3 << CRC_CR_POLYSIZE_SHIFT) +/**@}*/ -/* Default polynomial */ -#define CRC_POL_DEFAULT 0x04C11DB7 /**@}*/ -/*****************************************************************************/ -/* API definitions */ -/*****************************************************************************/ +/** Default polynomial */ +#define CRC_POL_DEFAULT 0x04C11DB7 -/*****************************************************************************/ -/* API Functions */ -/*****************************************************************************/ BEGIN_DECLS @@ -104,10 +105,3 @@ END_DECLS /**@}*/ -#endif -/** @cond */ -#else -#warning "crc_v2.h should not be included explicitly, only via crc.h" -#endif -/** @endcond */ - diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h index 7a241ab8..258af88b 100644 --- a/include/libopencm3/stm32/common/dac_common_all.h +++ b/include/libopencm3/stm32/common/dac_common_all.h @@ -77,6 +77,10 @@ specific memorymap.h header before including this header file.*/ /* DAC channel2 data output register (DAC_DOR2) */ #define DAC_DOR2 MMIO32(DAC_BASE + 0x30) +/** DAC status register. + * @note not available on F1 + */ +#define DAC_SR MMIO32(DAC_BASE + 0x34) /* --- DAC_CR values ------------------------------------------------------- */ @@ -377,6 +381,15 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 #define DAC_DOR2_DACC2DOR_LSB (1 << 0) #define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) +/** @defgroup dac_sr_values DAC_SR Values +@{*/ +/** DAC channel 1 DMA underrun flag */ +#define DAC_SR_DMAUDR1 (1 << 13) + +/** DAC channel 2 DMA underrun flag */ +#define DAC_SR_DMAUDR2 (1 << 29) +/*@}*/ + /** DAC channel identifier */ typedef enum { CHANNEL_1, CHANNEL_2, CHANNEL_D diff --git a/include/libopencm3/stm32/common/dma2d_common_f47.h b/include/libopencm3/stm32/common/dma2d_common_f47.h new file mode 100644 index 00000000..d66e37e3 --- /dev/null +++ b/include/libopencm3/stm32/common/dma2d_common_f47.h @@ -0,0 +1,188 @@ +/** @addtogroup dma2d_defines + * + * @version 1.0.0 + * + * @date 15 August 2016 + * + * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx + * series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * STM32F4xx/STM32F7xx DMA2D Register defines + * + * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com> + * + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <libopencm3/stm32/memorymap.h> +#include <stdint.h> + +#ifndef DMA2D_H +#define DMA2D_H + +/**@{*/ + +/** DMA2D Control Register */ +#define DMA2D_CR MMIO32(DMA2D_BASE + 0x0U) +#define DMA2D_CR_MODE_SHIFT 16 +#define DMA2D_CR_MODE_MASK 0x3 +#define DMA2D_CR_MODE_M2M 0 /* memory to memory */ +#define DMA2D_CR_MODE_M2MWPFC 1 /* memory to memory with pix convert */ +#define DMA2D_CR_MODE_M2MWB 2 /* memory to memory with blend */ +#define DMA2D_CR_MODE_R2M 3 /* register to memory */ +#define DMA2D_CR_CEIE (1 << 13) +#define DMA2D_CR_CTCIE (1 << 12) +#define DMA2D_CR_CAEIE (1 << 11) +#define DMA2D_CR_TWIE (1 << 10) +#define DMA2D_CR_TCIE (1 << 9) +#define DMA2D_CR_TEIE (1 << 8) +#define DMA2D_CR_ABORT (1 << 2) +#define DMA2D_CR_SUSP (1 << 1) +#define DMA2D_CR_START (1 << 0) + +/** DMA2D Interrupt Status Register */ +#define DMA2D_ISR MMIO32(DMA2D_BASE + 0x4U) +#define DMA2D_ISR_CEIF (1 << 5) +#define DMA2D_ISR_CTCIF (1 << 4) +#define DMA2D_ISR_CAEIF (1 << 3) +#define DMA2D_ISR_TWIF (1 << 2) +#define DMA2D_ISR_TCIF (1 << 1) +#define DMA2D_ISR_TEIF (1 << 0) + +/** DMA2D Interrupt Flag Clear Register */ +#define DMA2D_IFCR MMIO32(DMA2D_BASE + 0x8U) +#define DMA2D_IFCR_CCEIF (1 << 5) +#define DMA2D_IFCR_CCTCIF (1 << 4) +#define DMA2D_IFCR_CCAEIF (1 << 3) +#define DMA2D_IFCR_CTWIF (1 << 2) +#define DMA2D_IFCR_CTCIF (1 << 1) +#define DMA2D_IFCR_CTEIF (1 << 0) + +/** DMA2D Foreground Memory Address Register */ +#define DMA2D_FGMAR MMIO32(DMA2D_BASE + 0xCU) + +/** DMA2D Foreground Offset Register */ +#define DMA2D_FGOR MMIO32(DMA2D_BASE + 0x10U) +#define DMA2D_FGOR_LO_SHIFT 0 +#define DMA2D_FGOR_LO_MASK 0x3fff + +/** DMA2D Background Memory Address Register */ +#define DMA2D_BGMAR MMIO32(DMA2D_BASE + 0x14U) + +/** DMA2D Background Offset Register */ +#define DMA2D_BGOR MMIO32(DMA2D_BASE + 0x18U) +#define DMA2D_BGOR_LO_SHIFT 0 +#define DMA2D_BGOR_LO_MASK 0x3fff + +/** DMA2D Foreground and Background PFC Control Register */ +#define DMA2D_FGPFCCR MMIO32(DMA2D_BASE + 0x1cU) +#define DMA2D_BGPFCCR MMIO32(DMA2D_BASE + 0x24U) + +#define DMA2D_xPFCCR_ALPHA_SHIFT 24 +#define DMA2D_xPFCCR_ALPHA_MASK 0xff +#define DMA2D_xPFCCR_AM_SHIFT 16 +#define DMA2D_xPFCCR_AM_MASK 0x3 +#define DMA2D_xPFCCR_AM_NONE 0 +#define DMA2D_xPFCCR_AM_FORCE 1 +#define DMA2D_xPFCCR_AM_PRODUCT 2 +#define DMA2D_xPFCCR_CS_SHIFT 8 +#define DMA2D_xPFCCR_CS_MASK 0xff +#define DMA2D_xPFCCR_START (1 << 5) +#define DMA2D_xPFCCR_CCM_ARGB8888 (0 << 4) +#define DMA2D_xPFCCR_CCM_RGB888 (1 << 4) +#define DMA2D_xPFCCR_CM_SHIFT 0 +#define DMA2D_xPFCCR_CM_MASK 0xf +#define DMA2D_xPFCCR_CM_ARGB8888 0 +#define DMA2D_xPFCCR_CM_RGB888 1 +#define DMA2D_xPFCCR_CM_RGB565 2 +#define DMA2D_xPFCCR_CM_ARGB1555 3 +#define DMA2D_xPFCCR_CM_ARGB4444 4 +#define DMA2D_xPFCCR_CM_L8 5 +#define DMA2D_xPFCCR_CM_AL44 6 +#define DMA2D_xPFCCR_CM_AL88 7 +#define DMA2D_xPFCCR_CM_L4 8 +#define DMA2D_xPFCCR_CM_A8 9 +#define DMA2D_xPFCCR_CM_A4 10 + +/** DMA2D Foreground and Background Color Register */ +#define DMA2D_FGCOLR MMIO32(DMA2D_BASE + 0x20U) +#define DMA2D_BGCOLR MMIO32(DMA2D_BASE + 0x28U) +#define DMA2D_xCOLR_RED_SHIFT 16 +#define DMA2D_xCOLR_RED_MASK 0xff +#define DMA2D_xCOLR_GREEN_SHIFT 8 +#define DMA2D_xCOLR_GREEN_MASK 0xff +#define DMA2D_xCOLR_BLUE_SHIFT 0 +#define DMA2D_xCOLR_BLUE_MASK 0xff + +/** DMA2D Foreground CLUT Memory Address Register */ +#define DMA2D_FGCMAR MMIO32(DMA2D_BASE + 0x2CU) + +/** DMA2D Background CLUT Memory Address Register */ +#define DMA2D_BGCMAR MMIO32(DMA2D_BASE + 0x30U) + +/** DMA2D Output PFC Control Register */ +#define DMA2D_OPFCCR MMIO32(DMA2D_BASE + 0x34U) +#define DMA2D_OPFCCR_CM_SHIFT 0 +#define DMA2D_OPFCCR_CM_MASK 0x3 +#define DMA2D_OPFCCR_CM_ARGB8888 0 +#define DMA2D_OPFCCR_CM_RGB888 1 +#define DMA2D_OPFCCR_CM_RGB565 2 +#define DMA2D_OPFCCR_CM_ARGB1555 3 +#define DMA2D_OPFCCR_CM_ARGB4444 4 + +/** DMA2D Output Color Register */ +/* The format of this register depends on PFC control above */ +#define DMA2D_OCOLR MMIO32(DMA2D_BASE + 0x38U) + +/** DMA2D Output Memory Address Register */ +#define DMA2D_OMAR MMIO32(DMA2D_BASE + 0x3CU) + +/** DMA2D Output offset Register */ +#define DMA2D_OOR MMIO32(DMA2D_BASE + 0x40U) +#define DMA2D_OOR_LO_SHIFT 0 +#define DMA2D_OOR_LO_MASK 0x3fff + +/** DMA2D Number of Lines Register */ +#define DMA2D_NLR MMIO32(DMA2D_BASE + 0x44U) +#define DMA2D_NLR_PL_SHIFT 16 +#define DMA2D_NLR_PL_MASK 0x3fff +#define DMA2D_NLR_NL_SHIFT 0 +#define DMA2D_NLR_NL_MASK 0xffff + +/** DMA2D Line Watermark Register */ +#define DMA2D_LWR MMIO32(DMA2D_BASE + 0x48U) +#define DMA2D_LWR_LW_SHIFT 0 +#define DMA2D_LWR_LW_MASK 0xffff + +/** DMA2D AHB Master Timer Config Register */ +#define DMA2D_AMTCR MMIO32(DMA2D_BASE + 0x4CU) +#define DMA2D_AMTCR_DT_SHIFT 8 +#define DMA2D_AMTCR_DT_MASK 0xff +#define DMA2D_AMTCR_EN (1 << 0) + +/** DMA2D Foreground Color Lookup table */ +#define DMA2D_FG_CLUT (uint32_t *)(DMA2D_BASE + 0x400U) + +/** DMA2D Background Color Lookup table */ +#define DMA2D_BG_CLUT (uint32_t *)(DMA2D_BASE + 0x800U) + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/common/dma_common_csel.h b/include/libopencm3/stm32/common/dma_common_csel.h new file mode 100644 index 00000000..755bb1df --- /dev/null +++ b/include/libopencm3/stm32/common/dma_common_csel.h @@ -0,0 +1,56 @@ +/** @addtogroup dma_defines +*/ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +The order of header inclusion is important. dma.h includes the device +specific memorymap.h header before including this header file.*/ + +/**@{*/ + +/** @cond */ +#ifdef LIBOPENCM3_DMA_H +/** @endcond */ +#pragma once + + +/* DMA channel selection register (DMAx_CSELR) */ +#define DMA_CSELR(dma_base) MMIO32((dma_base) + 0xA8) +#define DMA1_CSELR DMA_CSELR(DMA1) +#define DMA2_CSELR DMA_CSELR(DMA2) + +/* --- DMA_CSELR values -------------------------------------------- */ + +#define DMA_CSELR_CxS_SHIFT(channel) (4 * ((channel) - 1)) +#define DMA_CSELR_CxS_MASK (0x0f) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dma_set_channel_request(uint32_t dma, uint8_t channel, uint8_t request); + +END_DECLS + +/** @cond */ +#else +#warning "dma_common_csel.h should not be included explicitly, only via dma.h" +#endif +/** @endcond */ + +/**@}*/ diff --git a/include/libopencm3/stm32/common/dsi_common_f47.h b/include/libopencm3/stm32/common/dsi_common_f47.h new file mode 100644 index 00000000..963c3dc0 --- /dev/null +++ b/include/libopencm3/stm32/common/dsi_common_f47.h @@ -0,0 +1,824 @@ +/** @addtogroup dsi_defines + * + * @version 1.0.0 + * + * @date 7 July 2016 + * + * @author @htmlonly © @endhtmlonly 2016 + * Chuck McManis <cmcmanis@mcmanis.com> + * + * This library supports the Display Serial Interface Host and Wrapper in + * the STM32F4xx and STM32F7xx series of ARM Cortex Microcontrollers by + * ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * STM32F4/7 DSI Host Defines + * + * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com> + * + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/stm32/memorymap.h> + +/** @cond */ +#ifndef DSI_H +/** @endcond */ +#define DSI_H + +/**@{*/ + + +/** + * DSI Host Version Register + */ +#define DSI_VR MMIO32(DSI_BASE + 0x0U) + +/** + * DSI Host Control Register + */ +#define DSI_CR MMIO32(DSI_BASE + 0x4U) +#define DSI_CR_EN (1 << 0) + +/** + * DSI Host Clock Control Register + */ +#define DSI_CCR MMIO32(DSI_BASE + 0x8U) +#define DSI_CCR_TOCKDIV_SHIFT 8 +#define DSI_CCR_TOCKDIV_MASK 0xff +#define DSI_CCR_TXECKDIV_SHIFT 0 +#define DSI_CCR_TXECKDIV_MASK 0xff + +/** + * DSI Host LTDC VCID Register + */ +#define DSI_LVCIDR MMIO32(DSI_BASE + 0xcU) +#define DSI_LVCIDR_VCID_SHIFT 0 +#define DSI_LVCIDR_VCID_MASK 0x3 + +/** + * DSI Host LTDC Color Coding Register + */ +#define DSI_LCOLCR MMIO32(DSI_BASE + 0x10U) +#define DSI_LCOLCR_LPE (1 << 8) +#define DSI_LCOLCR_COLC_SHIFT 0 +#define DSI_LCOLCR_COLC_MASK 0xf + +/** + * DSI Host LTDC Polarity Configuration Register + */ +#define DSI_LPCR MMIO32(DSI_BASE + 0x14U) +#define DSI_LPCR_HSP (1 << 2) +#define DSI_LPCR_VSP (1 << 1) +#define DSI_LPCR_DEP (1 << 0) + +/** + * DSI Host Low-power Configuration Register + */ +#define DSI_LPMCR MMIO32(DSI_BASE + 0x18U) +#define DSI_LPMCR_LPSIZE_SHIFT 16 +#define DSI_LPMCR_LPSIZE_MASK 0xff +#define DSI_LPMCR_VLPSIZE_SHIFT 0 +#define DSI_LPMCR_VLPSIZE_MASK 0xff + +/** + * DSI Host Protocol Configuration Register + */ +#define DSI_PCR MMIO32(DSI_BASE + 0x2cU) +#define DSI_PCR_CRCRXE (1 << 4) +#define DSI_PCR_ECCRXE (1 << 3) +#define DSI_PCR_BTAE (1 << 2) +#define DSI_PCR_ETRXE (1 << 1) +#define DSI_PCR_ETTXE (1 << 0) + +/** + * DSI Host Generic VCID Register + */ +#define DSI_GVCIDR MMIO32(DSI_BASE + 0x30U) +#define DSI_GVCIDR_VCID_SHIFT 0 +#define DSI_GVCIDR_VCID_MASK 0x3 + +/** + * DSI Host mode Configuration Register + */ +#define DSI_MCR MMIO32(DSI_BASE + 0x34U) +#define DSI_MCR_CMDM (1 << 0) + +/** + * DSI Host Video mode Configuration Register + */ +#define DSI_VMCR MMIO32(DSI_BASE + 0x38U) +#define DSI_VMCR_PGO (1 << 24) +#define DSI_VMCR_PGM (1 << 20) +#define DSI_VMCR_PGE (1 << 16) +#define DSI_VMCR_LPCE (1 << 15) +#define DSI_VMCR_FBTAAE (1 << 14) +#define DSI_VMCR_LPHFPE (1 << 13) +#define DSI_VMCR_LPHBPE (1 << 12) +#define DSI_VMCR_LPVAE (1 << 11) +#define DSI_VMCR_LPVFPE (1 << 10) +#define DSI_VMCR_LPVBPE (1 << 9) +#define DSI_VMCR_LPVSAE (1 << 8) +#define DSI_VMCR_VMT_SHIFT 0 +#define DSI_VMCR_VMT_MASK 0x3 +#define DSI_VMCR_VMT_NON_BURST_PULSE 0x0 +#define DSI_VMCR_VMT_NON_BURSE_EVENT 0x1 +#define DSI_VMCR_VMT_BURST 0x2 + +/** + * DSI Host Video Packet Configuration Register + */ +#define DSI_VPCR MMIO32(DSI_BASE + 0x3CU) +#define DSI_VPCR_VPSIZE_SHIFT 0 +#define DSI_VPCR_VPSIZE_MASK 0x3fff + +/** + * DSI Host Video Chunks Configuration Register + */ +#define DSI_VCCR MMIO32(DSI_BASE + 0x40U) +#define DSI_VCCR_NUMC_SHIFT 0 +#define DSI_VCCR_NUMC_MASK 0x1fff + +/** + * DSI Host Video Null Packet Configuration Register + */ +#define DSI_VNPCR MMIO32(DSI_BASE + 0x44U) +#define DSI_VNPCR_NPSIZE_SHIFT 0 +#define DSI_VNPCR_NPSIZE_MASK 0x1fff + +/** + * DSI Host Video HSA Configuration Register + */ +#define DSI_VHSACR MMIO32(DSI_BASE + 0x48U) +#define DSI_VHSACR_HSA_SHIFT 0 +#define DSI_VHSACR_HSA_MASK 0xfff + +/** + * DSI Host Video HBP Configuration Register + */ +#define DSI_VHBPCR MMIO32(DSI_BASE + 0x4CU) +#define DSI_VHBPCR_HBP_SHIFT 0 +#define DSI_VHBPCR_HBP_MASK 0xfff + +/** + * DSI Host Video Line Configuration Register + */ +#define DSI_VLCR MMIO32(DSI_BASE + 0x50U) +#define DSI_VLCR_HLINE_SHIFT 0 +#define DSI_VLCR_HLINE_MASK 0x7fff + +/** + * DSI Host Video VSA Configuration Register + */ +#define DSI_VVSACR MMIO32(DSI_BASE + 0x54U) +#define DSI_VVSACR_VSA_SHIFT 0 +#define DSI_VVSACR_VSA_MASK 0x3ff + +/** + * DSI Host Video VBP Configuration Register + */ +#define DSI_VVBPCR MMIO32(DSI_BASE + 0x58U) +#define DSI_VVBPCR_VBP_SHIFT 0 +#define DSI_VVBPCR_VBP_MASK 0x3ff + +/** + * DSI Host Video VFP Configuration Register + */ +#define DSI_VVFPCR MMIO32(DSI_BASE + 0x5CU) +#define DSI_VVFPCR_VFP_SHIFT 0 +#define DSI_VVFPCR_VFP_MASK 0x3ff + +/** + * DSI Host Video VA Configuration Register + */ +#define DSI_VVACR MMIO32(DSI_BASE + 0x60U) +#define DSI_VVACR_VA_SHIFT 0 +#define DSI_VVACR_VA_MASK 0x3fff + +/** + * DSI Host LTDC Command Configuration Register + */ +#define DSI_LCCR MMIO32(DSI_BASE + 0x64U) +#define DSI_LCCR_CMDSIZE_SHIFT 0 +#define DSI_LCCR_CMDSIZE_MASK 0xffff + +/** + * DSI Host Command mode Configuration Register + */ +#define DSI_CMCR MMIO32(DSI_BASE + 0x68U) +#define DSI_CMCR_MRDPS (1 << 24) +#define DSI_CMCR_DLWTX (1 << 19) +#define DSI_CMCR_DSR0TX (1 << 18) +#define DSI_CMCR_DSW1TX (1 << 17) +#define DSI_CMCR_DSW0TX (1 << 16) +/* Bit 15 reserved */ +#define DSI_CMCR_GLWTX (1 << 14) +#define DSI_CMCR_GSR2TX (1 << 13) +#define DSI_CMCR_GSR1TX (1 << 12) +#define DSI_CMCR_GSR0TX (1 << 11) +#define DSI_CMCR_GSW2TX (1 << 10) +#define DSI_CMCR_GSW1TX (1 << 9) +#define DSI_CMCR_GSW0TX (1 << 8) +/* Bits 7:2 Reserved */ +#define DSI_CMCR_ARE (1 << 1) +#define DSI_CMCR_TEARE (1 << 0) + +/** + * DSI Host Generic Header Configuration Register + */ +#define DSI_GHCR MMIO32(DSI_BASE + 0x6CU) +#define DSI_GHCR_WCMSB_SHIFT 16 +#define DSI_GHCR_WCMSB_MASK 0xff +#define DSI_GHCR_WCLSB_SHIFT 8 +#define DSI_GHCR_WCLSB_MASK 0xff +#define DSI_GHCR_DATA1_SHIFT 16 /* data 1 in 'short' mode */ +#define DSI_GHCR_DATA1_MASK 0xff +#define DSI_GHCR_DATA0_SHIFT 8 /* data 0 in 'short' mode */ +#define DSI_GHCR_DATA0_MASK 0xff +#define DSI_GHCR_VCID_SHIFT 6 +#define DSI_GHCR_VCID_MASK 0x3 +#define DSI_GHCR_DT_SHIFT 0 +#define DSI_GHCR_DT_MASK 0x3f + +/** + * DSI Host Generic Payload Data Register + */ +#define DSI_GPDR MMIO32(DSI_BASE + 0x70U) +#define DSI_GPDR_BYTE4_SHIFT 24 +#define DSI_GPDR_BYTE4_MASK 0xff +#define DSI_GPDR_BYTE3_SHIFT 16 +#define DSI_GPDR_BYTE3_MASK 0xff +#define DSI_GPDR_BYTE2_SHIFT 8 +#define DSI_GPDR_BYTE2_MASK 0xff +#define DSI_GPDR_BYTE1_SHIFT 0 +#define DSI_GPDR_BYTE1_MASK 0xff + +/** + * DSI Host Generate Packet Status Register + */ +#define DSI_GPSR MMIO32(DSI_BASE + 0x74U) +/* Reserved 31:7 */ +#define DSI_GPSR_RCB (1 << 6) +#define DSI_GPSR_PRDFF (1 << 5) +#define DSI_GPSR_PRDFE (1 << 4) +#define DSI_GPSR_PWRFF (1 << 3) +#define DSI_GPSR_PWRFE (1 << 2) +#define DSI_GPSR_CMDFF (1 << 1) +#define DSI_GPSR_CMDFE (1 << 0) + +/** + * DSI Host Timeout Counter Configuration Register + */ +#define DSI_TCCR0 MMIO32(DSI_BASE + 0x78U) +#define DSI_TCCR0_HSTX_TOCNT_SHIFT 16 +#define DSI_TCCR0_HSTX_TOCNT_MASK 0xffff +#define DSI_TCCR0_LPRX_TOCNT_SHIFT 0 +#define DSI_TCCR0_LPRX_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 1 + */ +#define DSI_TCCR1 MMIO32(DSI_BASE + 0x7CU) +#define DSI_TCCR1_HSRD_TOCNT_SHIFT 0 +#define DSI_TCCR1_HSRD_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 2 + */ +#define DSI_TCCR2 MMIO32(DSI_BASE + 0x80U) +#define DSI_TCCR2_LPRD_TOCNT_SHIFT 0 +#define DSI_TCCR2_LPRD_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 3 + */ +#define DSI_TCCR3 MMIO32(DSI_BASE + 0x84U) +#define DSI_TCCR3_PM (1 << 24) +#define DSI_TCCR3_HSWR_TOCNT_SHIFT 0 +#define DSI_TCCR3_HSWR_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 4 + */ +#define DSI_TCCR4 MMIO32(DSI_BASE + 0x88U) +#define DSI_TCCR4_LPWR_TOCNT_SHIFT 0 +#define DSI_TCCR4_LPWR_TOCNT_MASK 0xffff + +/** + * DSI Host Timeout Counter Configuration Register 5 + */ +#define DSI_TCCR5 MMIO32(DSI_BASE + 0x8CU) +#define DSI_TCCR5_BTA_TOCNT_SHIFT 0 +#define DSI_TCCR5_BTA_TOCNT_MASK 0xffff + +/** + * DSI Host Clock Lane Configuration Register + */ +#define DSI_CLCR MMIO32(DSI_BASE + 0x94U) +#define DSI_CLCR_ACR (1 << 1) +#define DSI_CLCR_DPCC (1 << 0) + +/** + * DSI Host Clock Lane Timer Configuration Register + */ +#define DSI_CLTCR MMIO32(DSI_BASE + 0x98U) +#define DSI_CLTCR_HS2LP_TIME_SHIFT 16 +#define DSI_CLTCR_HS2LP_TIME_MASK 0x3ff +#define DSI_CLTCR_LP2HS_TIME_SHIFT 0 +#define DSI_CLTCR_LP2HS_TIME_MASK 0x3ff + +/** + * DSI Host Data Lane Time Configuration Register + */ +#define DSI_DLTCR MMIO32(DSI_BASE + 0x9CU) +#define DSI_DLTCR_HS2LP_TIME_SHIFT 24 +#define DSI_DLTCR_HS2LP_TIME_MASK 0xff +#define DSI_DLTCR_LP2HS_TIME_SHIFT 16 +#define DSI_DLTCR_LP2HS_TIME_MASK 0xff +#define DSI_DLTCR_MRD_TIME_SHIFT 0 +#define DSI_DLTCR_MRD_TIME_MASK 0x7fff + +/** + * DSI Host PHY Control Register + */ +#define DSI_PCTLR MMIO32(DSI_BASE + 0xA0U) +#define DSI_PCTLR_CKE (1 << 2) +#define DSI_PCTLR_DEN (1 << 1) + +/** + * DSI Host PHY Configuration Register + */ +#define DSI_PCONFR MMIO32(DSI_BASE + 0xA4U) +#define DSI_PCONFR_SW_TIME_SHIFT 8 +#define DSI_PCONFR_SW_TIME_MASK 0xff +#define DSI_PCONFR_NL_SHIFT 0 +#define DSI_PCONFR_NL_MASK 0x3 +#define DSI_PCONFR_NL_1LANE 0 +#define DSI_PCONFR_NL_2LANE 1 + +/** + * DSI Host PHY ULPS Control Register + */ +#define DSI_PUCR MMIO32(DSI_BASE + 0xA8U) +#define DSI_PUCR_UEDL (1 << 3) +#define DSI_PUCR_URDL (1 << 2) +#define DSI_PUCR_UECL (1 << 1) +#define DSI_PUCR_URCL (1 << 0) + +/** + * DSI Host PHY TX Triggers Configuration Register + */ +#define DSI_PTTCR MMIO32(DSI_BASE + 0xACU) +#define DSI_PTTCR_TX_TRIG_SHIFT 0 +#define DSI_PTTCR_TX_TRIG_MASK 0xf +#define DSI_PTTCR_TX_TRIG_1 0x1 +#define DSI_PTTCR_TX_TRIG_2 0x2 +#define DSI_PTTCR_TX_TRIG_3 0x4 +#define DSI_PTTCR_TX_TRIG_4 0x8 + +/** + * DSI Host PHY Status Register + */ +#define DSI_PSR MMIO32(DSI_BASE + 0xB0U) +#define DSI_PSR_UAN1 (1 << 8) +#define DSI_PSR_PSS1 (1 << 7) +#define DSI_PSR_RUE0 (1 << 6) +#define DSI_PSR_UAN0 (1 << 5) +#define DSI_PSR_PSS0 (1 << 4) +#define DSI_PSR_UANC (1 << 3) +#define DSI_PSR_PSSC (1 << 2) +#define DSI_PSR_PD (1 << 1) + +/** + * DSI Host Interrupt & Status Register 0 + */ +#define DSI_ISR0 MMIO32(DSI_BASE + 0xBCU) +#define DSI_ISR0_PE4 (1 << 20) +#define DSI_ISR0_PE3 (1 << 19) +#define DSI_ISR0_PE2 (1 << 18) +#define DSI_ISR0_PE1 (1 << 17) +#define DSI_ISR0_PE0 (1 << 16) +#define DSI_ISR0_AE15 (1 << 15) +#define DSI_ISR0_AE14 (1 << 14) +#define DSI_ISR0_AE13 (1 << 13) +#define DSI_ISR0_AE12 (1 << 12) +#define DSI_ISR0_AE11 (1 << 11) +#define DSI_ISR0_AE10 (1 << 10) +#define DSI_ISR0_AE9 (1 << 9) +#define DSI_ISR0_AE8 (1 << 8) +#define DSI_ISR0_AE7 (1 << 7) +#define DSI_ISR0_AE6 (1 << 6) +#define DSI_ISR0_AE5 (1 << 5) +#define DSI_ISR0_AE4 (1 << 4) +#define DSI_ISR0_AE3 (1 << 3) +#define DSI_ISR0_AE2 (1 << 2) +#define DSI_ISR0_AE1 (1 << 1) +#define DSI_ISR0_AE0 (1 << 0) + +/** + * DSI Host Interrupt & Status Register 1 + */ +#define DSI_ISR1 MMIO32(DSI_BASE + 0xC0U) +#define DSI_ISR1_GPRXE (1 << 12) +#define DSI_ISR1_GPRDE (1 << 11) +#define DSI_ISR1_GPTXE (1 << 10) +#define DSI_ISR1_GPWRE (1 << 9) +#define DSI_ISR1_GCWRE (1 << 8) +#define DSI_ISR1_LPWRE (1 << 7) +#define DSI_ISR1_EOTPE (1 << 6) +#define DSI_ISR1_PSE (1 << 5) +#define DSI_ISR1_CRCE (1 << 4) +#define DSI_ISR1_ECCME (1 << 3) +#define DSI_ISR1_ECCSE (1 << 2) +#define DSI_ISR1_TOLPRX (1 << 1) +#define DSI_ISR1_TOHSTX (1 << 0) + +/** + * DSI Host Interrupt Enable Register 0 + */ +#define DSI_IER0 MMIO32(DSI_BASE + 0xC4U) +#define DSI_IER0_PE4IE (1 << 20) +#define DSI_IER0_PE3IE (1 << 19) +#define DSI_IER0_PE2IE (1 << 18) +#define DSI_IER0_PE1IE (1 << 17) +#define DSI_IER0_PE0IE (1 << 16) +#define DSI_IER0_AE15IE (1 << 15) +#define DSI_IER0_AE14IE (1 << 14) +#define DSI_IER0_AE13IE (1 << 13) +#define DSI_IER0_AE12IE (1 << 12) +#define DSI_IER0_AE11IE (1 << 11) +#define DSI_IER0_AE10IE (1 << 10) +#define DSI_IER0_AE9IE (1 << 9) +#define DSI_IER0_AE8IE (1 << 8) +#define DSI_IER0_AE7IE (1 << 7) +#define DSI_IER0_AE6IE (1 << 6) +#define DSI_IER0_AE5IE (1 << 5) +#define DSI_IER0_AE4IE (1 << 4) +#define DSI_IER0_AE3IE (1 << 3) +#define DSI_IER0_AE2IE (1 << 2) +#define DSI_IER0_AE1IE (1 << 1) +#define DSI_IER0_AE0IE (1 << 0) + +/** + * DSI Host Interrupt Enable Register 1 + */ +#define DSI_IER1 MMIO32(DSI_BASE + 0xC8U) +#define DSI_IER1_GPRXEIE (1 << 12) +#define DSI_IER1_GPRDEIE (1 << 11) +#define DSI_IER1_GPTXEIE (1 << 10) +#define DSI_IER1_GPWREIE (1 << 9) +#define DSI_IER1_GCWREIE (1 << 8) +#define DSI_IER1_LPWREIE (1 << 7) +#define DSI_IER1_EOTPEIE (1 << 6) +#define DSI_IER1_PSEIE (1 << 5) +#define DSI_IER1_CRCEIE (1 << 4) +#define DSI_IER1_ECCMEIE (1 << 3) +#define DSI_IER1_ECCSEIE (1 << 2) +#define DSI_IER1_TOLPRXIE (1 << 1) +#define DSI_IER1_TOHSTXIE (1 << 0) + +/** + * DSI Host Force Interrupt Register 0 + */ +#define DSI_FIR0 MMIO32(DSI_BASE + 0xD8U) +#define DSI_FIR0_FPE4 (1 << 20) +#define DSI_FIR0_FPE3 (1 << 19) +#define DSI_FIR0_FPE2 (1 << 18) +#define DSI_FIR0_FPE1 (1 << 17) +#define DSI_FIR0_FPE0 (1 << 16) +#define DSI_FIR0_FAE15 (1 << 15) +#define DSI_FIR0_FAE14 (1 << 14) +#define DSI_FIR0_FAE13 (1 << 13) +#define DSI_FIR0_FAE12 (1 << 12) +#define DSI_FIR0_FAE11 (1 << 11) +#define DSI_FIR0_FAE10 (1 << 10) +#define DSI_FIR0_FAE9 (1 << 9) +#define DSI_FIR0_FAE8 (1 << 8) +#define DSI_FIR0_FAE7 (1 << 7) +#define DSI_FIR0_FAE6 (1 << 6) +#define DSI_FIR0_FAE5 (1 << 5) +#define DSI_FIR0_FAE4 (1 << 4) +#define DSI_FIR0_FAE3 (1 << 3) +#define DSI_FIR0_FAE2 (1 << 2) +#define DSI_FIR0_FAE1 (1 << 1) +#define DSI_FIR0_FAE0 (1 << 0) + +/** + * DSI Host Force Interrupt Register 1 + */ +#define DSI_FIR1 MMIO32(DSI_BASE + 0xDCU) +#define DSI_FIR1_FGPRXE (1 << 12) +#define DSI_FIR1_FGPRDE (1 << 11) +#define DSI_FIR1_FGPTXE (1 << 10) +#define DSI_FIR1_FGPWRE (1 << 9) +#define DSI_FIR1_FGCWRE (1 << 8) +#define DSI_FIR1_FLPWRE (1 << 7) +#define DSI_FIR1_FEOTPE (1 << 6) +#define DSI_FIR1_FPSE (1 << 5) +#define DSI_FIR1_FCRCE (1 << 4) +#define DSI_FIR1_FECCME (1 << 3) +#define DSI_FIR1_FECCSE (1 << 2) +#define DSI_FIR1_FTOLPRX (1 << 1) +#define DSI_FIR1_FTOHSTX (1 << 0) + +/** + * DSI Host Video Shadow Control Register + */ +#define DSI_VSCR MMIO32(DSI_BASE + 0x100U) +#define DSI_VSCR_UR (1 << 8) +#define DSI_VSCR_EN (1 << 0) + +/** + * DSI Host LTDC Current VCID Register + */ +#define DSI_LCVCIDR MMIO32(DSI_BASE + 0x10CU) +#define DSI_LCVCIDR_VCID_SHIFT 0 +#define DSI_LCVCIDR_VCID_MASK 0x3 + +/** + * DSI Host LTCD Current Color Coding Register + */ +#define DSI_LCCCR MMIO32(DSI_BASE + 0x110U) +#define DSI_LCCR_LPE (1 << 8) +#define DSI_LCCR_COLC_SHIFT 0 +#define DSI_LCCR_COLC_MASK 0xf + +/** + * DSI Host Low-power mode Current Configuration Register + */ +#define DSI_LPMCCR MMIO32(DSI_BASE + 0x118U) +#define DSI_LPMCCR_LPSIZE_SHIFT 16 +#define DSI_LPMCCR_LPSIZE_MASK 0xff +#define DSI_LPMCCR_VLPSIZE_SHIFT 0 +#define DSI_LPMCCR_VLPSIZE_MASK 0xff + +/** + * DSI Host Video mode Current Configuration Register + */ +#define DSI_VMCCR MMIO32(DSI_BASE + 0x138U) +#define DSI_VMCCR_LPCE (1 << 9) +#define DSI_VMCCR_FBTAAE (1 << 8) +#define DSI_VMCCR_LPHFE (1 << 7) +#define DSI_VMCCR_LPHBPE (1 << 6) +#define DSI_VMCCR_LPVAE (1 << 5) +#define DSI_VMCCR_LPVFPE (1 << 4) +#define DSI_VMCCR_LPVBPE (1 << 3) +#define DSI_VMCCR_LPVSAE (1 << 2) +#define DSI_VMCCR_VMT_SHIFT 0 +#define DSI_VMCCR_VMT_MASK 0x3 + +/** + * DSI Host Video Packet Current Configuration Register + */ +#define DSI_VPCCR MMIO32(DSI_BASE + 0x13CU) +#define DSI_VPCCR_VPSIZE_SHIFT 0 +#define DSI_VPCCR_VPSIZE_MASK 0x3fff + +/** + * DSI Host Video Chunks Current Configuration Register + */ +#define DSI_VCCCR MMIO32(DSI_BASE + 0x140U) +#define DSI_VCCCR_NUMC_SHIFT 0 +#define DSI_VCCCR_NUMC_MASK 0x1fff + +/** + * DSI Host Video Null Packet Current Configuration Register + */ +#define DSI_VNPCCR MMIO32(DSI_BASE + 0x144U) +#define DSI_VNPCCR_NPSIZE_SHIFT 0 +#define DSI_VNPCCR_NPSIZE_MASK 0x1fff + +/** + * DSI Host Video HSA Current Configuration Register + */ +#define DSI_VHSACCR MMIO32(DSI_BASE + 0x148U) +#define DSI_VHSACCR_HSA_SHIFT 0 +#define DSI_VHSACCR_HSA_MASK 0xfff + +/** + * DSI Host Video HBP Current Configuration Register + */ +#define DSI_VHBPCCR MMIO32(DSI_BASE + 0x14CU) +#define DSI_VHBPCCR_HBP_SHIFT 0 +#define DSI_VHBPCCR_HBP_MASK 0xfff + +/** + * DSI Host Video Line Current Configuration Register + */ +#define DSI_VLCCR MMIO32(DSI_BASE + 0x150U) +#define DSI_VLCCR_HLINE_SHIFT 0 +#define DSI_VLCCR_HLINE_MASK 0x7fff + +/** + * DSI Host Video VSA Current Configuration Register + */ +#define DSI_VVSACCR MMIO32(DSI_BASE + 0x154U) +#define DSI_VVSACCR_VSA_SHIFT 0 +#define DSI_VVSACCR_VSA_MASK 0x3ff + +/** + * DSI Host Video VBP Current Configuration Register + */ +#define DSI_VVBPCCR MMIO32(DSI_BASE + 0x0158U) +#define DSI_VVBPCCR_VBP_SHIFT 0 +#define DSI_VVBPCCR_VBP_MAST 0x3ff + +/** + * DSI Host Video VFP Current Configuration Register + */ +#define DSI_VVFPCCR MMIO32(DSI_BASE + 0x15CU) +#define DSI_VVFPCCR_VFP_SHIFT 0 +#define DSI_VVFPCCR_VFP_MASK 0x3ff + +/** + * DSI Host Video VA Current Configuration Register + */ +#define DSI_VVACCR MMIO32(DSI_BASE + 0x160U) +#define DSI_VVACCR_VA_SHIFT 0 +#define DSI_VVACCR_VA_MASK 0x3fff + +/** + * DSI Wrapper Configuration Register + */ +#define DSI_WCFGR MMIO32(DSI_BASE + 0x400U) +#define DSI_WCFGR_VSPOL (1 << 7) +#define DSI_WCFGR_AR (1 << 6) +#define DSI_WCFGR_TEPOL (1 << 5) +#define DSI_WCFGR_TESRC (1 << 4) +#define DSI_WCFGR_COLMUX_SHIFT 1 +#define DSI_WCFGR_COLMUX_MASK 7 +#define DSI_WCFGR_DSIM (1 << 0) + +/** + * DSI Wrapper Control Register + */ +#define DSI_WCR MMIO32(DSI_BASE + 0x404U) +#define DSI_WCR_DSIEN (1 << 3) +#define DSI_WCR_LTDCEN (1 << 2) +#define DSI_WCR_SHTDN (1 << 1) +#define DSI_WCR_COLM (1 << 0) + +/** + * DSI Wrapper Interrupt Enable Register + */ +#define DSI_WIER MMIO32(DSI_BASE + 0x408U) +#define DSI_WIER_RRIE (1 << 13) +#define DSI_WIER_PLLUIE (1 << 10) +#define DSI_WIER_PLLLIE (1 << 9) +#define DSI_WIER_ERIE (1 << 1) +#define DSI_WIER_TEIE (1 << 0) + +/** + * DSI Wrapper Interrupt & Status Register + */ +#define DSI_WISR MMIO32(DSI_BASE + 0x40CU) +/* reserved 31:14 */ +#define DSI_WISR_RRIF (1 << 13) +#define DSI_WISR_RRS (1 << 12) +#define DSI_WISR_PLLUIF (1 << 10) +#define DSI_WISR_PLLLIF (1 << 9) +#define DSI_WISR_PLLLS (1 << 8) +/* reserved 7:3 */ +#define DSI_WISR_BUSY (1 << 2) +#define DSI_WISR_ERIF (1 << 1) +#define DSI_WISR_TEIF (1 << 0) + +/** + * DSI Wrapper Interrupt Flag Clear Register + */ +#define DSI_WIFCR MMIO32(DSI_BASE + 0x410U) +/* reserved 31:14 */ +#define DSI_WIFCR_CRRIF (1 << 13) +/* reserved 12:11 */ +#define DSI_WIFCR_CPLLUIF (1 << 10) +#define DSI_WIFCR_CPLLLIF (1 << 9) +/* reserved 8:2 */ +#define DSI_WIFCR_CERIF (1 << 1) +#define DSI_WIFCR_CTEIF (1 << 0) + +/** + * DSI Wrapper PHY Configuration Register 0 + */ +#define DSI_WPCR0 MMIO32(DSI_BASE + 0x418U) +#define DSI_WPCR0_TCLKPOSTEN (1 << 27) +#define DSI_WPCR0_TLPXCEN (1 << 26) +#define DSI_WPCR0_THSEXITEN (1 << 25) +#define DSI_WPCR0_TLPXDEN (1 << 24) +#define DSI_WPCR0_THSZEROEN (1 << 23) +#define DSI_WPCR0_THSTRAILEN (1 << 22) +#define DSI_WPCR0_THSPREPEN (1 << 21) +#define DSI_WPCR0_TCLKZEROEN (1 << 20) +#define DSI_WPCR0_TCLKPREPEN (1 << 19) +#define DSI_WPCR0_PDEN (1 << 18) +#define DSI_WPCR0_TDDL (1 << 16) +#define DSI_WPCR0_CDOFFDL (1 << 14) +#define DSI_WPCR0_FTXSMDL (1 << 13) +#define DSI_WPCR0_FTXSMCL (1 << 12) +#define DSI_WPCR0_HSIDL1 (1 << 11) +#define DSI_WPCR0_HSIDL0 (1 << 10) +#define DSI_WPCR0_HSICL (1 << 9) +#define DSI_WPCR0_SWDL1 (1 << 8) +#define DSI_WPCR0_SWDL0 (1 << 7) +#define DSI_WPCR0_SWCL (1 << 6) +#define DSI_WPCR0_UIX4_SHIFT 0 +#define DSI_WPCR0_UIX4_MASK 0x3f + +/** + * DSI Wrapper PHY Configration Register 1 + */ +#define DSI_WPCR1 MMIO32(DSI_BASE + 0x41CU) +#define DSI_WPCR1_LPRXFT_SHIFT 25 +#define DSI_WPCR1_LPRXFT_MASK 0x3 +#define DSI_WPCR1_FLPRXLPM (1 << 22) +#define DSI_WPCR1_HSTXSRCDL_SHIFT 18 +#define DSI_WPCR1_HSTXSRCDL_MASK 0x3 +#define DSI_WPCR1_HSTXSRCCL_SHIFT 16 +#define DSI_WPCR1_HSTXSRCCL_MASK 0x3 +#define DSI_WPCR1_SDDC (1 << 12) +#define DSI_WPCR1_LPSRCDL_SHIFT 8 +#define DSI_WPCR1_LPSRCDL_MASK 0x3 +#define DSI_WPCR1_HSTXDDL_SHIFT 2 +#define DSI_WPCR1_HSTXDDL_MASK 0x3 +#define DSI_WPCR1_HSTXDCL_SHIFT 0 +#define DSI_WPCR1_HSTXDCL_MASK 0x3 + +/** + * DSI Wrapper PHY Configuration Register 2 + */ +#define DSI_WPCR2 MMIO32(DSI_BASE + 0x420U) +#define DSI_WPCR2_THSTRAIL_SHIFT 24 +#define DSI_WPCR2_THSTRAIL_MASK 0xff +#define DSI_WPCR2_THSPREP_SHIFT 16 +#define DSI_WPCR2_THSPREP_MASK 0xff +#define DSI_WPCR2_TCLKZERO_SHIFT 8 +#define DSI_WPCR2_TCLKZERO_MASK 0xff +#define DSI_WPCR2_TCLKPREP_SHIFT 0 +#define DSI_WPCR2_TCLKPREP_MASK 0xff + +/** + * DSI Wrapper PHY Configuration Register 3 + */ +#define DSI_WPCR3 MMIO32(DSI_BASE + 0x424U) +#define DSI_WPCR3_TLPXC_SHIFT 24 +#define DSI_WPCR3_TLPXC_MASK 0xff +#define DSI_WPCR3_THSEXIT_SHIFT 16 +#define DSI_WPCR3_THSEXIT_MASK 0xff +#define DSI_WPCR3_TLPXD_SHIFT 8 +#define DSI_WPCR3_TLPXD_MASK 0xff +#define DSI_WPCR3_THSZERO_SHIFT 0 +#define DSI_WPCR3_THSZERO_MASK 0xff + +/** + * DSI Wrapper PHY Configuration Register 4 + */ +#define DSI_WPCR4 MMIO32(DSI_BASE + 0x428U) +#define DSI_WPCR4_TCLKPOST_SHIFT 0 +#define DSI_WPCR4_TCLKPOST_MASK 0xff + +/** + * DSI Wrapper Regulator and PLL Control Register + */ +#define DSI_WRPCR MMIO32(DSI_BASE + 0x430U) +#define DSI_WRPCR_REGEN (1 << 24) +#define DSI_WRPCR_ODF_SHIFT 16 +#define DSI_WRPCR_ODF_MASK 0x3 +#define DSI_WRPCR_ODF_DIV_1 0 +#define DSI_WRPCR_ODF_DIV_2 1 +#define DSI_WRPCR_ODF_DIV_4 2 +#define DSI_WRPCR_ODF_DIV_8 3 +#define DSI_WRPCR_IDF_SHIFT 11 +#define DSI_WRPCR_IDF_MASK 0xf +#define DSI_WRPCR_IDF_DIV_1 1 +#define DSI_WRPCR_IDF_DIV_2 2 +#define DSI_WRPCR_IDF_DIV_3 3 +#define DSI_WRPCR_IDF_DIV_4 4 +#define DSI_WRPCR_IDF_DIV_5 5 +#define DSI_WRPCR_IDF_DIV_6 6 +#define DSI_WRPCR_IDF_DIV_7 7 +/* valid NDIV values 10 - 125 all other reserved */ +#define DSI_WRPCR_NDIV_SHIFT 2 +#define DSI_WRPCR_NDIV_MASK 0x7f +#define DSI_WRPCR_PLLEN (1 << 0) + +/** @cond */ +#endif +/** @endcond */ +/**@}*/ diff --git a/include/libopencm3/stm32/common/exti_common_all.h b/include/libopencm3/stm32/common/exti_common_all.h index 18596ad4..61753618 100644 --- a/include/libopencm3/stm32/common/exti_common_all.h +++ b/include/libopencm3/stm32/common/exti_common_all.h @@ -29,15 +29,6 @@ #define LIBOPENCM3_EXTI_COMMON_ALL_H /**@{*/ -/* --- EXTI registers ------------------------------------------------------ */ - -#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) -#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) -#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) -#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) -#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) -#define EXTI_PR MMIO32(EXTI_BASE + 0x14) - /* EXTI number definitions */ #define EXTI0 (1 << 0) #define EXTI1 (1 << 1) diff --git a/include/libopencm3/stm32/common/exti_common_v1.h b/include/libopencm3/stm32/common/exti_common_v1.h new file mode 100644 index 00000000..9b091edb --- /dev/null +++ b/include/libopencm3/stm32/common/exti_common_v1.h @@ -0,0 +1,55 @@ +/** @addtogroup exti_defines */ +#pragma once + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/** @cond */ +#if defined(LIBOPENCM3_EXTI_H) +/** @endcond */ + +/**@{*/ + +/* --- EXTI registers ------------------------------------------------------ */ + +/** @defgroup exti_registers EXTI Registers +@{*/ +/** EXTI Interrupt Mask Registers */ +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +/** EXTI Event Mask Register */ +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +/** EXTI Rising Trigger Selection Register */ +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +/** EXTI Falling Triger Selection Register */ +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +/** EXTI Software Interrupt Event Register */ +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +/** EXTI Pending Register */ +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ + +/** @cond */ +#else +#warning "exti_common_v1.h should not be included directly, only via exti.h" +#endif +/** @endcond */ diff --git a/include/libopencm3/stm32/common/flash_common_l01.h b/include/libopencm3/stm32/common/flash_common_l01.h index 64f2f6a5..442c000f 100644 --- a/include/libopencm3/stm32/common/flash_common_l01.h +++ b/include/libopencm3/stm32/common/flash_common_l01.h @@ -119,6 +119,7 @@ void flash_lock_pecr(void); void flash_unlock_progmem(void); void flash_lock_progmem(void); void flash_lock_option_bytes(void); +void flash_unlock_acr(void); void eeprom_program_word(uint32_t address, uint32_t data); void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words); diff --git a/include/libopencm3/stm32/common/fmc_common_f47.h b/include/libopencm3/stm32/common/fmc_common_f47.h new file mode 100644 index 00000000..91fe410e --- /dev/null +++ b/include/libopencm3/stm32/common/fmc_common_f47.h @@ -0,0 +1,269 @@ +/** @addtogroup fmc_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Chuck McManis <cmcmanis@mcmanis.com> + * + * @date 2013 + * + * This library supports the Flexible Memory Controller (FMC) in the STM32F4xx + * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_FMC_COMMON_F47_H +#define LIBOPENCM3_FMC_COMMON_F47_H + +#ifndef LIBOPENCM3_FSMC_H +#error "This file should not be included directly, it is included with fsmc.h" +#endif + +/* --- Convenience macros -------------------------------------------------- */ +#define FMC_BANK5_BASE 0xa0000000U +#define FMC_BANK6_BASE 0xb0000000U +#define FMC_BANK7_BASE 0xc0000000U +#define FMC_BANK8_BASE 0xd0000000U + +/* --- FMC registers ------------------------------------------------------ */ + +/* SDRAM Control Registers 1 .. 2 */ +#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x)) +#define FMC_SDCR1 FMC_SDCR(0) +#define FMC_SDCR2 FMC_SDCR(1) + + +/* SDRAM Timing Registers 1 .. 2 */ +#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x)) +#define FMC_SDTR1 FMC_SDTR(0) +#define FMC_SDTR2 FMC_SDTR(1) + +/* SDRAM Command Mode Register */ +#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150) + +/* SDRAM Refresh Timer Register */ +#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154) + +/* SDRAM Status Register */ +#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158) + +/* --- FMC_SDCRx values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* RPIPE: Read Pipe */ +#define FMC_SDCR_RPIPE_SHIFT 13 +#define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT) +#define FMC_SDCR_RPIPE_NONE (0 << FMC_SDCR_RPIPE_SHIFT) +#define FMC_SDCR_RPIPE_1CLK (1 << FMC_SDCR_RPIPE_SHIFT) +#define FMC_SDCR_RPIPE_2CLK (2 << FMC_SDCR_RPIPE_SHIFT) + +/* RBURST: Burst Read */ +#define FMC_SDCR_RBURST (1 << 12) + +/* SDCLK: SDRAM Clock Configuration */ +#define FMC_SDCR_SDCLK_SHIFT 10 +#define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT) +#define FMC_SDCR_SDCLK_DISABLE (0 << FMC_SDCR_SDCLK_SHIFT) +#define FMC_SDCR_SDCLK_2HCLK (2 << FMC_SDCR_SDCLK_SHIFT) +#define FMC_SDCR_SDCLK_3HCLK (3 << FMC_SDCR_SDCLK_SHIFT) + +/* WP: Write Protect */ +#define FMC_SDCR_WP_ENABLE (1 << 9) + +/* CAS: CAS Latency */ +#define FMC_SDCR_CAS_SHIFT 7 +#define FMC_SDCR_CAS_1CYC (1 << FMC_SDCR_CAS_SHIFT) +#define FMC_SDCR_CAS_2CYC (2 << FMC_SDCR_CAS_SHIFT) +#define FMC_SDCR_CAS_3CYC (3 << FMC_SDCR_CAS_SHIFT) + +/* NB: Number of Internal banks */ +#define FMC_SDCR_NB2 0 +#define FMC_SDCR_NB4 (1 << 6) + +/* MWID: Memory width */ +#define FMC_SDCR_MWID_SHIFT 4 +#define FMC_SDCR_MWID_8b (0 << FMC_SDCR_MWID_SHIFT) +#define FMC_SDCR_MWID_16b (1 << FMC_SDCR_MWID_SHIFT) +#define FMC_SDCR_MWID_32b (2 << FMC_SDCR_MWID_SHIFT) + +/* NR: Number of rows */ +#define FMC_SDCR_NR_SHIFT 2 +#define FMC_SDCR_NR_11 (0 << FMC_SDCR_NR_SHIFT) +#define FMC_SDCR_NR_12 (1 << FMC_SDCR_NR_SHIFT) +#define FMC_SDCR_NR_13 (2 << FMC_SDCR_NR_SHIFT) + +/* NC: Number of Columns */ +#define FMC_SDCR_NC_SHIFT 0 +#define FMC_SDCR_NC_8 (0 << FMC_SDCR_NC_SHIFT) +#define FMC_SDCR_NC_9 (1 << FMC_SDCR_NC_SHIFT) +#define FMC_SDCR_NC_10 (2 << FMC_SDCR_NC_SHIFT) +#define FMC_SDCR_NC_11 (3 << FMC_SDCR_NC_SHIFT) + +/* --- FMC_SDTRx values --------------------------------------------------- */ + +/* Bits [31:28]: Reserved. */ + +/* TRCD: Row to Column Delay */ +#define FMC_SDTR_TRCD_SHIFT 24 +#define FMC_SDTR_TRCD_MASK (15 << FMC_SDTR_TRCD_SHIFT) + +/* TRP: Row Precharge Delay */ +#define FMC_SDTR_TRP_SHIFT 20 +#define FMC_SDTR_TRP_MASK (15 << FMC_SDTR_TRP_SHIFT) + +/* TWR: Recovery Delay */ +#define FMC_SDTR_TWR_SHIFT 16 +#define FMC_SDTR_TWR_MASK (15 << FMC_SDTR_TWR_SHIFT) + +/* TRC: Row Cycle Delay */ +#define FMC_SDTR_TRC_SHIFT 12 +#define FMC_SDTR_TRC_MASK (15 << FMC_SDTR_TRC_SHIFT) + +/* TRAS: Self Refresh Time */ +#define FMC_SDTR_TRAS_SHIFT 8 +#define FMC_SDTR_TRAS_MASK (15 << FMC_SDTR_TRAS_SHIFT) + +/* TXSR: Exit Self-refresh Delay */ +#define FMC_SDTR_TXSR_SHIFT 4 +#define FMC_SDTR_TXSR_MASK (15 << FMC_SDTR_TXSR_SHIFT) + +/* TRMD: Load Mode Register to Active */ +#define FMC_SDTR_TMRD_SHIFT 0 +#define FMC_SDTR_TMRD_MASK (15 << FMC_SDTR_TMRD_SHIFT) + +/* + * Some config bits only count in CR1 or TR1, even if you + * are just configuring bank 2, so these masks let you copy + * out those bits after you have computed values for CR2 and + * TR2 and put them into CR1 and TR1 + */ +#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK) +#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \ + FMC_SDCR_RPIPE_MASK | \ + FMC_SDCR_RBURST) + +/* --- FMC_SDCMR values --------------------------------------------------- */ + +/* Bits [31:22]: Reserved. */ + +/* MRD: Mode Register Definition */ +#define FMC_SDCMR_MRD_SHIFT 9 +#define FMC_SDCMR_MRD_MASK (0x1fff << FMC_SDCMR_MRD_SHIFT) + +/* NRFS: Number of Auto-refresh */ +#define FMC_SDCMR_NRFS_SHIFT 5 +#define FMC_SDCMR_NRFS_MASK (15 << FMC_SDCMR_NRFS_SHIFT) + +/* CTB1: Command Target Bank 1 */ +#define FMC_SDCMR_CTB1 (1 << 4) + +/* CTB2: Command Target Bank 2 */ +#define FMC_SDCMR_CTB2 (1 << 3) + +/* MODE: Command Mode */ +#define FMC_SDCMR_MODE_SHIFT 0 +#define FMC_SDCMR_MODE_MASK 7 +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1 +#define FMC_SDCMR_MODE_PALL 2 +#define FMC_SDCMR_MODE_AUTO_REFRESH 3 +#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4 +#define FMC_SDCMR_MODE_SELF_REFRESH 5 +#define FMC_SDCMR_MODE_POWER_DOWN 6 + +/* --- FMC_SDRTR values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* REIE: Refresh Error Interrupt Enable */ +#define FMC_SDRTR_REIE (1 << 14) + +/* COUNT: Refresh Timer Count */ +#define FMC_SDRTR_COUNT_SHIFT 1 +#define FMC_SDRTR_COUNT_MASK (0x1fff << FMC_SDRTR_COUNT_SHIFT) + +/* CRE: Clear Refresh Error Flag */ +#define FMC_SDRTR_CRE (1 << 0) + +/* --- FMC_SDSR values ---------------------------------------------------- */ + +/* Bits [31:6]: Reserved. */ + +/* BUSY: Set if the SDRAM is working on the command */ +#define FMC_SDSR_BUSY (1 << 5) + +/* MODES: Status modes */ +#define FMC_SDSR_MODE_NORMAL 0 +#define FMC_SDSR_MODE_SELF_REFRESH 1 +#define FMC_SDSR_MODE_POWER_DOWN 2 + +/* Mode shift */ +#define FMC_SDSR_MODE2_SHIFT 3 +#define FMC_SDSR_MODE1_SHIFT 1 + +/* RE: Refresh Error */ +#define FMC_SDSR_RE (1 << 0) + +/* Helper function for setting the timing parameters */ +struct sdram_timing { + int trcd; /* RCD Delay */ + int trp; /* RP Delay */ + int twr; /* Write Recovery Time */ + int trc; /* Row Cycle Delay */ + int tras; /* Self Refresh TIme */ + int txsr; /* Exit Self Refresh Time */ + int tmrd; /* Load to Active delay */ +}; + +/* Mode register parameters */ +#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS }; +enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL, + SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE, + SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN }; + +/* Send an array of timing parameters (indices above) to create SDTR register + * value + */ +BEGIN_DECLS + +uint32_t sdram_timing(struct sdram_timing *t); +void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd, + int autorefresh, int modereg); + +END_DECLS + +#endif +/**@}*/ diff --git a/include/libopencm3/stm32/common/i2c_common_v2.h b/include/libopencm3/stm32/common/i2c_common_v2.h index cd311064..ad4846b9 100644 --- a/include/libopencm3/stm32/common/i2c_common_v2.h +++ b/include/libopencm3/stm32/common/i2c_common_v2.h @@ -46,6 +46,9 @@ specific memorymap.h header before including this header file.*/ #ifdef I2C3_BASE #define I2C3 I2C3_BASE #endif +#ifdef I2C4_BASE +#define I2C4 I2C4_BASE +#endif /**@}*/ /* --- I2C registers ------------------------------------------------------- */ diff --git a/include/libopencm3/stm32/common/lptimer_common_all.h b/include/libopencm3/stm32/common/lptimer_common_all.h new file mode 100644 index 00000000..37ea10f1 --- /dev/null +++ b/include/libopencm3/stm32/common/lptimer_common_all.h @@ -0,0 +1,296 @@ +/** @addtogroup lptimer_defines + * + * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski <piotr@esden.net> + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski <piotr@esden.net> + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +/** @cond */ +#if defined(LIBOPENCM3_LPTIMER_H) +/** @endcond */ +#ifndef LIBOPENCM3_LPTIMER_COMMON_H +#define LIBOPENCM3_LPTIMER_COMMON_H + +/* --- LPTIM (low power timer) ------------------------------------------- */ + +#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) +#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) +#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) +#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) +#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) +#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) +#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) +#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) + +#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) +#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) +#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE) +#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) +#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE) +#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) +#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) +#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) + +#if defined(LPTIM2_BASE) +#define LPTIM2_ISR LPTIM_ISR(LPTIM2_BASE) +#define LPTIM2_ICR LPTIM_ICR(LPTIM2_BASE) +#define LPTIM2_IER LPTIM_IER(LPTIM2_BASE) +#define LPTIM2_CFGR LPTIM_CFGR(LPTIM2_BASE) +#define LPTIM2_CR LPTIM_CR(LPTIM2_BASE) +#define LPTIM2_CMP LPTIM_CMP(LPTIM2_BASE) +#define LPTIM2_ARR LPTIM_ARR(LPTIM2_BASE) +#define LPTIM2_CNT LPTIM_CNT(LPTIM2_BASE) +#endif + +/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register +@{*/ + +/** LPTIM_ISR_CMPM Compare match */ +#define LPTIM_ISR_CMPM (1 << 0) + +/** LPTIM_ISR_ARRM Autoreload match */ +#define LPTIM_ISR_ARRM (1 << 1) + +/** LPTIM_ISR_EXTTRIG External trigger edge event */ +#define LPTIM_ISR_EXTTRIG (1 << 2) + +/** LPTIM_ISR_CMPOK Compare register update OK */ +#define LPTIM_ISR_CMPOK (1 << 3) + +/** LPTIM_ISR_ARROK Autoreload register update OK */ +#define LPTIM_ISR_ARROK (1 << 4) + +/** LPTIM_ISR_UP Counter direction change down to up */ +#define LPTIM_ISR_UP (1 << 5) + +/** LPTIM_ISR_DOWN Counter direction change up to down */ +#define LPTIM_ISR_DOWN (1 << 6) + +/**@}*/ + +/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register +@{*/ + +/** LPTIM_ICR_CMPMCF compare match Clear Flag */ +#define LPTIM_ICR_CMPMCF (1 << 0) + +/** LPTIM_ICR_ARRMCF Autoreload match Clear Flag */ +#define LPTIM_ICR_ARRMCF (1 << 1) + +/** LPTIM_ICR_EXTTRIGCF External trigger valid edge Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF (1 << 2) + +/** LPTIM_ICR_CMPOKCF Compare register update OK Clear Flag */ +#define LPTIM_ICR_CMPOKCF (1 << 3) + +/** LPTIM_ICR_ARROKCF Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF (1 << 4) + +/** LPTIM_ICR_UPCF Direction change to UP Clear Flag */ +#define LPTIM_ICR_UPCF (1 << 5) + +/** LPTIM_ICR_DOWNCF Direction change to down Clear Flag */ +#define LPTIM_ICR_DOWNCF (1 << 6) + +/**@}*/ + +/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register +@{*/ + +/** LPTIM_IER_CMPMIE Compare match Interrupt Enable */ +#define LPTIM_IER_CMPMIE (1 << 0) + +/** LPTIM_IER_ARRMIE Autoreload match Interrupt Enable */ +#define LPTIM_IER_ARRMIE (1 << 1) + +/** LPTIM_IER_EXTTRIGIE External trigger valid edge Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE (1 << 2) + +/** LPTIM_IER_CMPOKIE Compare register update OK Interrupt Enable */ +#define LPTIM_IER_CMPOKIE (1 << 3) + +/** LPTIM_IER_ARROKIE Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE (1 << 4) + +/** LPTIM_IER_UPIE Direction change to UP Interrupt Enable */ +#define LPTIM_IER_UPIE (1 << 5) + +/** LPTIM_IER_DOWNIE Direction change to down Interrupt Enable */ +#define LPTIM_IER_DOWNIE (1 << 6) + +/**@}*/ + +/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register +@{*/ + +/** CKSEL: Select internal (0) or external clock source (1) */ +#define LPTIM_CFGR_CKSEL (1 << 0) + +#define LPTIM_CFGR_CKPOL_SHIFT 1 +#define LPTIM_CFGR_CKPOL_MASK 0x03 +#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) +/** @defgroup lptim_cfgr_ckpol LPTIM_CFGR CKPOL Clock Polarity +@{*/ +#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) +#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_CKFLT_SHIFT 3 +#define LPTIM_CFGR_CKFLT_MASK 0x03 +#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) +/** @defgroup lptim_cfgr_ckflt LPTIM_CFGR CKFLT Configurable digital filter for external clock +@{*/ +#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) +#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) +#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_TRGFLT_SHIFT 6 +#define LPTIM_CFGR_TRGFLT_MASK 0x03 +#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) +/** @defgroup lptim_cfgr_trgflt LPTIM_CFGR TRGFLT Configurable digital filter for trigger +@{*/ +#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) +#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) +#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_PRESC_SHIFT 9 +#define LPTIM_CFGR_PRESC_MASK 0x07 +#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) +/** @defgroup lptim_cfgr_presc LPTIM_CFGR PRESC Clock prescaler +@{*/ +#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) +#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_TRIGSEL_SHIFT 13 +#define LPTIM_CFGR_TRIGSEL_MASK 0x07 +#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) +/** @defgroup lptim_cfgr_trigsel LPTIM_CFGR TRIGSEL Trigger selector +@{*/ +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) +/* 5 is reserved */ +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) +#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) +/**@}*/ + +#define LPTIM_CFGR_TRIGEN_SHIFT 17 +#define LPTIM_CFGR_TRIGEN_MASK 0x07 +#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) +/** @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity +@{*/ +#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) +#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) +/**@}*/ + +/** TIMOUT: Timeout enable */ +#define LPTIM_CFGR_TIMOUT (1 << 19) + +/** WAVE: Waveform shape */ +#define LPTIM_CFGR_WAVE (1 << 20) + +/** WAVPOL: Waveform shape polarity */ +#define LPTIM_CFGR_WAVPOL (1 << 21) + +/** PRELOAD: Register update mode */ +#define LPTIM_CFGR_PRELOAD (1 << 22) + +/** COUNTMODE: Counter mode enable */ +#define LPTIM_CFGR_COUNTMODE (1 << 23) + +/** ENC: Encoder mode enable */ +#define LPTIM_CFGR_ENC (1 << 24) + +/**@}*/ + +/** @defgroup lptim_cr LPTIM_CR Control Register +@{*/ + +/** ENABLE: LPTIM Enable */ +#define LPTIM_CR_ENABLE (1 << 0) + +/** SNGSTRT: Start in Single Mode */ +#define LPTIM_CR_SNGSTRT (1 << 1) + +/** CNGSTRT: Start in Continuous Mode */ +#define LPTIM_CR_CNTSTRT (1 << 2) + +/**@}*/ + +/* --- LPTIM function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void lptimer_enable(uint32_t timer_peripheral); +void lptimer_disable(uint32_t timer_peripheral); + +void lptimer_start_counter(uint32_t timer_peripheral, uint32_t mode); +void lptimer_set_counter(uint32_t timer_peripheral, uint16_t count); +uint16_t lptimer_get_counter(uint32_t timer_peripheral); +void lptimer_set_compare(uint32_t timer_peripheral, uint16_t compare_value); +void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value); +void lptimer_enable_preload(uint32_t lptimer_peripheral); +void lptimer_disable_preload(uint32_t lptimer_peripheral); +void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral); +void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral); + +void lptimer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); +void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen); +void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source); +void lptimer_set_internal_clock_source(uint32_t timer_peripheral); +void lptimer_set_external_clock_source(uint32_t timer_peripheral); + +void lptimer_clear_flag(uint32_t timer_peripheral, uint32_t flag); +bool lptimer_get_flag(uint32_t timer_peripheral, uint32_t flag); +void lptimer_enable_irq(uint32_t timer_peripheral, uint32_t irq); +void lptimer_disable_irq(uint32_t timer_peripheral, uint32_t irq); + + +END_DECLS + +#endif +/** @cond */ +#else +#warning "lptimer_common_all.h should not be included directly, only via lptimer.h" +#endif +/** @endcond */ + +/**@}*/ diff --git a/include/libopencm3/stm32/common/ltdc_common_f47.h b/include/libopencm3/stm32/common/ltdc_common_f47.h new file mode 100644 index 00000000..d938d6cc --- /dev/null +++ b/include/libopencm3/stm32/common/ltdc_common_f47.h @@ -0,0 +1,535 @@ +/** @addtogroup ltdc_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2014 + * Oliver Meier <h2obrain@gmail.com> + * + * @date 5 December 2014 + * + * This library supports the LCD TFT display controller (LTDC) in the STM32F4xx + * and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Oliver Meier <h2obrain@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ +/** @cond */ +#ifndef LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ +/** @endcond */ +#define LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ + + +#include <stdint.h> +#include <libopencm3/stm32/rcc.h> + +/** + * LTDC + */ + + +#define LTDC_SSCR (MMIO32(LTDC_BASE + 0x08)) +#define LTDC_BPCR (MMIO32(LTDC_BASE + 0x0C)) +#define LTDC_AWCR (MMIO32(LTDC_BASE + 0x10)) +#define LTDC_TWCR (MMIO32(LTDC_BASE + 0x14)) +#define LTDC_GCR (MMIO32(LTDC_BASE + 0x18)) +#define LTDC_SRCR (MMIO32(LTDC_BASE + 0x24)) +#define LTDC_BCCR (MMIO32(LTDC_BASE + 0x2C)) +#define LTDC_IER (MMIO32(LTDC_BASE + 0x34)) +#define LTDC_ISR (MMIO32(LTDC_BASE + 0x38)) +#define LTDC_ICR (MMIO32(LTDC_BASE + 0x3C)) +#define LTDC_LIPCR (MMIO32(LTDC_BASE + 0x40)) +#define LTDC_CPSR (MMIO32(LTDC_BASE + 0x44)) +#define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) + +/* x == LTDC_LAYER_x */ +#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) +#define LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) +#define LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) + +#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) +#define LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) +#define LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) + +#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) +#define LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) +#define LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) + +#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) +#define LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) +#define LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) + +#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) +#define LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) +#define LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) + +#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) +#define LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) +#define LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) + +#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) +#define LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) +#define LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) + +#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) +#define LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) +#define LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) + +#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) +#define LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) +#define LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) + +#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) +#define LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) +#define LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) + +#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) +#define LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) +#define LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) + +#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) +#define LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) +#define LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) + + +#define LTDC_LAYER_1 1 +#define LTDC_LAYER_2 2 + +/* --- LTDC_SSCR values ---------------------------------------------------- */ + +/* Horizontal Synchronization Width */ +#define LTDC_SSCR_HSW_SHIFT 16 +#define LTDC_SSCR_HSW_MASK 0xfff + +/* Vertical Synchronization Height */ +#define LTDC_SSCR_VSH_SHIFT 0 +#define LTDC_SSCR_VSH_MASK 0x7ff + +/* --- LTDC_BPCR values ---------------------------------------------------- */ + +/* Accumulated Horizontal Back Porch */ +#define LTDC_BPCR_AHBP_SHIFT 16 +#define LTDC_BPCR_AHBP_MASK 0xfff + +/* Accumulated Vertical Back Porch */ +#define LTDC_BPCR_AVBP_SHIFT 0 +#define LTDC_BPCR_AVBP_MASK 0x7FF + +/* --- LTDC_AWCR values ---------------------------------------------------- */ + +/* Accumulated Active Width */ +#define LTDC_AWCR_AAW_SHIFT 16 +#define LTDC_AWCR_AAW_MASK 0xfff + +/* Accumulated Active Height */ +#define LTDC_AWCR_AAH_SHIFT 0 +#define LTDC_AWCR_AAH_MASK 0x7ff + +/* --- LTDC_TWCR values ---------------------------------------------------- */ + +/* Total Width */ +#define LTDC_TWCR_TOTALW_SHIFT 16 +#define LTDC_TWCR_TOTALW_MASK 0xfff + +/* Total Height */ +#define LTDC_TWCR_TOTALH_SHIFT 0 +#define LTDC_TWCR_TOTALH_MASK 0x7ff + +/* GCR - control register */ +#define LTDC_GCR_LTDC_ENABLE (1<<0) +#define LTDC_GCR_DITHER_ENABLE (1<<16) + +#define LTDC_GCR_PCPOL_ACTIVE_LOW (0<<28) +#define LTDC_GCR_PCPOL_ACTIVE_HIGH (1<<28) + +#define LTDC_GCR_DEPOL_ACTIVE_LOW (0<<29) +#define LTDC_GCR_DEPOL_ACTIVE_HIGH (1<<29) + +#define LTDC_GCR_VSPOL_ACTIVE_LOW (0<<30) +#define LTDC_GCR_VSPOL_ACTIVE_HIGH (1<<30) + +#define LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31) +#define LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31) + +/* GCR - register bit defines (no semantics) */ +#define LTDC_GCR_HSPOL (1 << 31) +#define LTDC_GCR_VSPOL (1 << 30) +#define LTDC_GCR_DEPOL (1 << 29) +#define LTDC_GCR_PCPOL (1 << 28) +#define LTDC_GCR_DITHER (1 << 16) +#define LTDC_GCR_LTDCEN (1 << 0) + +/* --- LTDC_SRCR values ---------------------------------------------------- */ + +/* Vertical Blanking Reload */ +#define LTDC_SRCR_VBR (1 << 1) + +/* Immediate Reload */ +#define LTDC_SRCR_IMR (1 << 0) + +/* LTDC_BCCR - reload control */ +#define LTDC_SRCR_RELOAD_IMR (1<<0) +#define LTDC_SRCR_RELOAD_VBR (1<<1) + +/* --- LTDC_IER values ----------------------------------------------------- */ + +/* Register Reload Interrupt Enable */ +#define LTDC_IER_RRIE (1 << 3) + +/* Transfer Error Interrupt Enable */ +#define LTDC_IER_TERRIE (1 << 2) + +/* FIFO Underrun Interrupt Enable */ +#define LTDC_IER_FUIE (1 << 1) + +/* Line Interrupt Enable */ +#define LTDC_IER_LIE (1 << 0) + +/* --- LTDC_ISR values ----------------------------------------------------- */ + +/* Register Reload Interrupt Flag */ +#define LTDC_ISR_RRIF (1 << 3) + +/* Transfer Error Interrupt Flag */ +#define LTDC_ISR_TERRIF (1 << 2) + +/* FIFO Underrun Interrupt Flag */ +#define LTDC_ISR_FUIF (1 << 1) + +/* Line Interrupt Flag */ +#define LTDC_ISR_LIF (1 << 0) + +/* --- LTDC_ICR values ----------------------------------------------------- */ + +/* Clears Register Reload Interrupt Flag */ +#define LTDC_ICR_CRRIF (1 << 3) + +/* Clears Transfer Error Interrupt Flag */ +#define LTDC_ICR_CTERRIF (1 << 2) + +/* Clears FIFO Underrun Interrupt Flag */ +#define LTDC_ICR_CFUIF (1 << 1) + +/* Clears Line Interrupt Flag */ +#define LTDC_ICR_CLIF (1 << 0) + +/* --- LTDC_LIPCR values --------------------------------------------------- */ + +/* Line Interrupt Position */ +#define LTDC_LIPCR_LIPOS_SHIFT 0 +#define LTDC_LIPCR_LIPOS_MASK 0x7ff + +/* --- LTDC_CPSR values ---------------------------------------------------- */ + +/* Current X Position */ +#define LTDC_CPSR_CXPOS_SHIFT 16 +#define LTDC_CPSR_CXPOS_MASK 0xffff + +/* Current Y Position */ +#define LTDC_CPSR_CYPOS_SHIFT 0 +#define LTDC_CPSR_CYPOS_MASK 0xffff + +/* LTDC_CDSR - display status register */ +#define LTDC_CDSR_VDES (1<<0) +#define LTDC_CDSR_HDES (1<<1) +#define LTDC_CDSR_VSYNCS (1<<2) +#define LTDC_CDSR_HSYNCS (1<<3) + +/* LTDC_LxCR - layer control */ +#define LTDC_LxCR_LAYER_ENABLE (1<<0) +#define LTDC_LxCR_COLKEY_ENABLE (1<<1) +#define LTDC_LxCR_COLTAB_ENABLE (1<<4) + +/* --- LTDC_LxWHPCR values ------------------------------------------------- */ + +/* Window Horizontal Stop Position */ +#define LTDC_LxWHPCR_WHSPPOS_SHIFT 16 +#define LTDC_LxWHPCR_WHSPPOS_MASK 0xfff + +/* Window Horizontal Start Position */ +#define LTDC_LxWHPCR_WHSTPOS_SHIFT 0 +#define LTDC_LxWHPCR_WHSTPOS_MASK 0xfff + +/* --- LTDC_LxWVPCR values ------------------------------------------------- */ + +/* Window Vertical Stop Position */ +#define LTDC_LxWVPCR_WVSPPOS_SHIFT 16 +#define LTDC_LxWVPCR_WVSPPOS_MASK 0x7ff + +/* Window Vertical Start Position */ +#define LTDC_LxWVPCR_WVSTPOS_SHIFT 0 +#define LTDC_LxWVPCR_WVSTPOS_MASK 0x7ff + +/* --- LTDC_LxCKCR values -------------------------------------------------- */ + +/* Color Key Red */ +#define LTDC_LxCKCR_CKRED_SHIFT 16 +#define LTDC_LxCKCR_CKRED_MASK 0xff + +/* Color Key Green */ +#define LTDC_LxCKCR_CKGREEN_SHIFT 16 +#define LTDC_LxCKCR_CKGREEN_MASK 0xff + +/* Color Key Blue */ +#define LTDC_LxCKCR_CKBLUE_SHIFT 16 +#define LTDC_LxCKCR_CKBLUE_MASK 0xff + +/* LTDC_LxPFCR - Pixel formats */ +#define LTDC_LxPFCR_ARGB8888 (0b000) +#define LTDC_LxPFCR_RGB888 (0b001) +#define LTDC_LxPFCR_RGB565 (0b010) +#define LTDC_LxPFCR_ARGB1555 (0b011) +#define LTDC_LxPFCR_ARGB4444 (0b100) +#define LTDC_LxPFCR_L8 (0b101) +#define LTDC_LxPFCR_AL44 (0b110) +#define LTDC_LxPFCR_AL88 (0b111) + +/* --- LTDC_LxCACR values -------------------------------------------------- */ + +/* Constant Alpha */ +#define LTDC_LxCACR_CONSTA_SHIFT 0 +#define LTDC_LxCACR_CONSTA_MASK 0xff + +/* --- LTDC_LxDCCR values -------------------------------------------------- */ + +/* Default Color Alpha */ +#define LTDC_LxDCCR_DCALPHA_SHIFT 24 +#define LTDC_LxDCCR_DCALPHA_MASK 1 + +/* Default Color Red */ +#define LTDC_LxDCCR_DCRED_SHIFT 16 +#define LTDC_LxDCCR_DCRED_MASK 1 + +/* Default Color Green */ +#define LTDC_LxDCCR_DCGREEN_SHIFT 8 +#define LTDC_LxDCCR_DCGREEN_MASK 1 + +/* Default Color Blue */ +#define LTDC_LxDCCR_DCBLUE_SHIFT 0 +#define LTDC_LxDCCR_DCBLUE_MASK 1 + +/* LTDC_LxBFCR - Blending factors - BF1 */ +#define LTDC_LxBFCR_BF1_CONST_ALPHA (0b100) +#define LTDC_LxBFCR_BF1_PIXEL_ALPHA_x_CONST_ALPHA (0b110) +/* LTDC_LxBFCR - Blending factors - BF2 */ +#define LTDC_LxBFCR_BF2_CONST_ALPHA (0b101) +#define LTDC_LxBFCR_BF2_PIXEL_ALPHA_x_CONST_ALPHA (0b111) + +/* --- LTDC_LxCFBAR values ------------------------------------------------- */ + +/* Color Frame Buffer Start Address */ +#define LTDC_LxCFBAR_CFBAR_SHIFT 0 +#define LTDC_LxCFBAR_CFBAR_MASK 0xffffffff + +/* --- LTDC_LxCFBLR values ------------------------------------------------- */ + +/* Color Frame Buffer Pitch */ +#define LTDC_LxCFBLR_CFBP_SHIFT 16 +#define LTDC_LxCFBLR_CFBP_MASK 0x1fff + +/* Color Frame Buffer Line Length */ +#define LTDC_LxCFBLR_CFBLL_SHIFT 0 +#define LTDC_LxCFBLR_CFBLL_MASK 0x1fff + +/* --- LTDC_LxCFBLNR values ------------------------------------------------ */ + +/* Frame Buffer Line Number */ +#define LTDC_LxCFBLNR_CFBLNBR_SHIFT 0 +#define LTDC_LxCFBLNR_CFBLNBR_MASK 0x3ff + +/* --- LTDC_LxCLUTWR values ------------------------------------------------ */ + +/* CLUT Address */ +#define LTDC_LxCLUTWR_CLUTADD_SHIFT 24 +#define LTDC_LxCLUTWR_CLUTADD_MASK 0xff + +/* Red */ +#define LTDC_LxCLUTWR_RED_SHIFT 16 +#define LTDC_LxCLUTWR_RED_MASK 0xff + +/* Green */ +#define LTDC_LxCLUTWR_GREEN_SHIFT 8 +#define LTDC_LxCLUTWR_GREEN_MASK 0xff + +/* Blue */ +#define LTDC_LxCLUTWR_BLUE_SHIFT 0 +#define LTDC_LxCLUTWR_BLUE_MASK 0xff + +/** + * simple helper macros + */ + +/* global */ +static inline void ltdc_ctrl_enable(uint32_t ctrl_flags) +{ + LTDC_GCR |= ctrl_flags; +} + +static inline void ltdc_ctrl_disable(uint32_t ctrl_flags) +{ + LTDC_GCR &= ~(ctrl_flags); +} + +static inline void ltdc_reload(uint32_t reload_flags) +{ + LTDC_SRCR = reload_flags; +} + +static inline void ltdc_set_background_color(uint8_t r, uint8_t g, uint8_t b) +{ + LTDC_BCCR = (((r)&255)<<16) | + (((g)&255)<<8) | + (((b)&255)<<0); +} + +static inline void ltdc_get_current_position(uint16_t *x, uint16_t *y) +{ + uint32_t tmp = LTDC_CPSR; + *x = tmp >> 16; + *y = tmp &= 0xFFFF; +} + +static inline uint16_t ltdc_get_current_position_x(void) +{ + return LTDC_CPSR >> 16; +} + +static inline uint16_t ltdc_get_current_position_y(void) +{ + return LTDC_CPSR & 0xffff; +} + +static inline uint32_t ltdc_get_display_status(uint32_t status_flags) +{ + return LTDC_CDSR & status_flags; +} + +/* layers */ +static inline void ltdc_layer_ctrl_enable(uint32_t layer, uint32_t ctrl_flags) +{ + LTDC_LxCR(layer) |= ctrl_flags; +} + +static inline void ltdc_layer_ctrl_disable(uint32_t layer, uint32_t ctrl_flags) +{ + LTDC_LxCR(layer) &= ~(ctrl_flags); +} + +static inline void ltdc_set_color_key(uint32_t layer, + uint8_t r, uint8_t g, uint8_t b) +{ + LTDC_LxCKCR(layer) = ((((r)&255)<<16) | + (((g)&255)<<8) | + (((b)&255)<<0)); +} + +static inline void ltdc_set_pixel_format(uint32_t layer, uint32_t format) +{ + LTDC_LxPFCR(layer) = format; +} + +static inline void ltdc_set_constant_alpha(uint32_t layer, uint8_t alpha) +{ + LTDC_LxCACR(layer) = ((alpha)&255); +} + +static inline void ltdc_set_default_colors(uint32_t layer, + uint8_t a, + uint8_t r, uint8_t g, uint8_t b) +{ + LTDC_LxDCCR(layer) = ((((a)&255)<<24) | + (((r)&255)<<16) | + (((g)&255)<<8) | + (((b)&255)<<0)); +} + +static inline void ltdc_set_blending_factors(uint32_t layer, + uint8_t bf1, uint8_t bf2) +{ + LTDC_LxBFCR(layer) = ((bf1)<<8) | ((bf2)<<0); +} + +static inline void ltdc_set_fbuffer_address(uint32_t layer, uint32_t address) +{ + LTDC_LxCFBAR(layer) = (uint32_t)address; +} + +static inline uint32_t ltdc_get_fbuffer_address(uint32_t layer) +{ + return LTDC_LxCFBAR(layer); +} + +static inline void ltdc_set_fb_line_length(uint32_t layer, + uint16_t len, uint16_t pitch) +{ + LTDC_LxCFBLR(layer) = ((((pitch)&0x1FFF)<<16) | (((len)&0x1FFF)<<0)); +} + +static inline void ltdc_set_fb_line_count(uint32_t layer, uint16_t linecount) +{ + LTDC_LxCFBLNR(layer) = (((linecount)&0x3FF)<<0); +} + +/** + * more complicated helper functions + */ +void ltdc_set_tft_sync_timings( + uint16_t sync_width, uint16_t sync_height, + uint16_t h_back_porch, uint16_t v_back_porch, + uint16_t active_width, uint16_t active_height, + uint16_t h_front_porch, uint16_t v_front_porch +); +void ltdc_setup_windowing( + uint8_t layer_number, + uint16_t h_back_porch, uint16_t v_back_porch, + uint16_t active_width, uint16_t active_height +); + + + +/** + * Helper function to wait for SRCR reload to complete or so + */ + +static inline bool LTDC_SRCR_IS_RELOADING(void) +{ + return (LTDC_SRCR & (LTDC_SRCR_RELOAD_VBR | + LTDC_SRCR_RELOAD_IMR)) != 0; +} + +/** + * color conversion helper function + * (simulate the ltdc color conversion) + */ + +static inline uint32_t ltdc_get_rgb888_from_rgb565(uint16_t rgb565) +{ + uint32_t rgb565_32 = (uint32_t)rgb565; + return ((((rgb565_32) & 0xF800) >> (11-8))/31)<<16 + | ((((rgb565_32) & 0x07E0) << (8-5))/63)<<8 + | ((((rgb565_32) & 0x001F) << (8-0))/31)<<0; +} + +/** @cond */ +#endif /* LIBOPENCM3_STM32_COMMON_LTDC_COMMON_F47_H_ */ +/** @endcond */ +/**@}*/ + diff --git a/include/libopencm3/stm32/common/rtc_common_l1f024.h b/include/libopencm3/stm32/common/rtc_common_l1f024.h index 9d577f36..0de52e8c 100644 --- a/include/libopencm3/stm32/common/rtc_common_l1f024.h +++ b/include/libopencm3/stm32/common/rtc_common_l1f024.h @@ -152,9 +152,9 @@ specific memorymap.h header before including this header file.*/ /** Weekday units mask */ #define RTC_DR_WDU_MASK (0x7) /** Month tens in BCD format shift */ -#define RTC_DR_MT (1<<12) -/** Month tens in BCD format mask */ #define RTC_DR_MT_SHIFT (12) +/** Month tens in BCD format mask */ +#define RTC_DR_MT_MASK (1<<12) /** Month units in BCD format shift */ #define RTC_DR_MU_SHIFT (8) /** Month units in BCD format mask */ diff --git a/include/libopencm3/stm32/common/spi_common_v2.h b/include/libopencm3/stm32/common/spi_common_v2.h index 2f2e204b..dd81b6cb 100644 --- a/include/libopencm3/stm32/common/spi_common_v2.h +++ b/include/libopencm3/stm32/common/spi_common_v2.h @@ -59,6 +59,12 @@ specific memorymap.h header before including this header file.*/ /* FRXTH: FIFO reception threshold */ #define SPI_CR2_FRXTH (1 << 12) +/* FRF: Frame format */ +/* Note: Not used in I2S mode. */ +#define SPI_CR2_FRF (1 << 4) +#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) +#define SPI_CR2_FRF_TI_MODE (1 << 4) + /* DS: Data size */ /****************************************************************************/ /** @defgroup spi_ds SPI data size @@ -98,6 +104,9 @@ specific memorymap.h header before including this header file.*/ #define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) #define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) +/* FRE : TI frame format error */ +#define SPI_SR_FRE (1 << 8) + /* --- Function prototypes ------------------------------------------------- */ BEGIN_DECLS diff --git a/include/libopencm3/stm32/common/syscfg_common_l1f234.h b/include/libopencm3/stm32/common/syscfg_common_l1f234.h index 776e12da..5e7f2d42 100644 --- a/include/libopencm3/stm32/common/syscfg_common_l1f234.h +++ b/include/libopencm3/stm32/common/syscfg_common_l1f234.h @@ -50,6 +50,10 @@ specific memorymap.h header before including this header file.*/ #define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) +/* --- SYSCFG_EXTICR Values -------------------------------------------------*/ + +#define SYSCFG_EXTICR_FIELDSIZE 4 + #endif /**@}*/ diff --git a/include/libopencm3/stm32/common/timer_common_all.h b/include/libopencm3/stm32/common/timer_common_all.h index f3f21158..4dbfcc4f 100644 --- a/include/libopencm3/stm32/common/timer_common_all.h +++ b/include/libopencm3/stm32/common/timer_common_all.h @@ -39,8 +39,6 @@ specific memorymap.h header before including this header file.*/ /* Timer register base addresses (for convenience) */ /****************************************************************************/ /** @defgroup tim_reg_base Timer register base addresses -@ingroup timer_defines - @{*/ #define TIM1 TIM1_BASE #define TIM2 TIM2_BASE @@ -81,6 +79,12 @@ specific memorymap.h header before including this header file.*/ #if defined(TIM17_BASE) # define TIM17 TIM17_BASE #endif +#if defined(TIM21_BASE) +# define TIM21 TIM21_BASE +#endif +#if defined(TIM22_BASE) +# define TIM22 TIM22_BASE +#endif /**@}*/ /* --- Timer registers ----------------------------------------------------- */ @@ -388,8 +392,6 @@ specific memorymap.h header before including this header file.*/ /****************************************************************************/ /** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio -@ingroup timer_defines - @{*/ /* CKD[1:0]: Clock division */ #define TIM_CR1_CKD_CK_INT (0x0 << 8) @@ -404,8 +406,6 @@ specific memorymap.h header before including this header file.*/ /* CMS[1:0]: Center-aligned mode selection */ /****************************************************************************/ /** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection -@ingroup timer_defines - @{*/ #define TIM_CR1_CMS_EDGE (0x0 << 5) #define TIM_CR1_CMS_CENTER_1 (0x1 << 5) @@ -417,8 +417,6 @@ specific memorymap.h header before including this header file.*/ /* DIR: Direction */ /****************************************************************************/ /** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction -@ingroup timer_defines - @{*/ #define TIM_CR1_DIR_UP (0 << 4) #define TIM_CR1_DIR_DOWN (1 << 4) @@ -440,8 +438,6 @@ specific memorymap.h header before including this header file.*/ /****************************************************************************/ /** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values -@ingroup timer_defines - @{*/ /* OIS4:*//** Output idle state 4 (OC4 output) */ #define TIM_CR2_OIS4 (1 << 14) @@ -472,8 +468,6 @@ specific memorymap.h header before including this header file.*/ /* MMS[2:0]: Master mode selection */ /****************************************************************************/ /** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection -@ingroup timer_defines - @{*/ #define TIM_CR2_MMS_RESET (0x0 << 4) #define TIM_CR2_MMS_ENABLE (0x1 << 4) @@ -533,9 +527,7 @@ specific memorymap.h header before including this header file.*/ #define TIM_SMCR_MSM (1 << 7) /* TS[2:0]: Trigger selection */ -/** @defgroup tim_ts TS Trigger selection -@ingroup timer_defines - +/** @defgroup tim_ts TIMx_SMCR TS Trigger selection @{*/ /** Internal Trigger 0 (ITR0) */ #define TIM_SMCR_TS_ITR0 (0x0 << 4) @@ -557,9 +549,7 @@ specific memorymap.h header before including this header file.*/ /**@}*/ /* SMS[2:0]: Slave mode selection */ -/** @defgroup tim_sms SMS Slave mode selection -@ingroup timer_defines - +/** @defgroup tim_sms TIMx_SMCR SMS Slave mode selection @{*/ /** Slave mode disabled */ #define TIM_SMCR_SMS_OFF (0x0 << 0) @@ -593,8 +583,6 @@ depending on the level of the complementary input. */ /****************************************************************************/ /** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values -@ingroup timer_defines - @{*/ /* TDE:*//** Trigger DMA request enable */ #define TIM_DIER_TDE (1 << 14) @@ -645,8 +633,6 @@ depending on the level of the complementary input. */ /* --- TIMx_SR values ------------------------------------------------------ */ /****************************************************************************/ /** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags -@ingroup timer_defines - @{*/ /* CC4OF:*//** Capture/compare 4 overcapture flag */ @@ -690,8 +676,6 @@ depending on the level of the complementary input. */ /****************************************************************************/ /** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values -@ingroup timer_defines - @{*/ /* BG:*//** Break generation */ @@ -1053,8 +1037,6 @@ depending on the level of the complementary input. */ /* LOCK[1:0]: Lock configuration */ /****************************************************************************/ /** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values -@ingroup timer_defines - @{*/ #define TIM_BDTR_LOCK_OFF (0x0 << 8) #define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) diff --git a/include/libopencm3/stm32/common/usart_common_f124.h b/include/libopencm3/stm32/common/usart_common_f124.h index 41ce2999..cd5c7122 100644 --- a/include/libopencm3/stm32/common/usart_common_f124.h +++ b/include/libopencm3/stm32/common/usart_common_f124.h @@ -39,7 +39,6 @@ specific memorymap.h header before including this header file.*/ /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ diff --git a/include/libopencm3/stm32/common/usart_common_f24.h b/include/libopencm3/stm32/common/usart_common_f24.h index e8d9f7f0..9edb640b 100644 --- a/include/libopencm3/stm32/common/usart_common_f24.h +++ b/include/libopencm3/stm32/common/usart_common_f24.h @@ -38,9 +38,14 @@ specific memorymap.h header before including this header file.*/ /* --- Convenience macros -------------------------------------------------- */ +/** @addtogroup usart_reg_base USART register base addresses + * Holds all the U(S)ART peripherals supported. + * @{ + */ #define USART6 USART6_BASE #define UART7 UART7_BASE #define UART8 UART8_BASE +/**@}*/ /* --- USART registers ----------------------------------------------------- */ diff --git a/include/libopencm3/stm32/crc.h b/include/libopencm3/stm32/crc.h index 8e97231d..65c6803e 100644 --- a/include/libopencm3/stm32/crc.h +++ b/include/libopencm3/stm32/crc.h @@ -30,10 +30,14 @@ # include <libopencm3/stm32/f3/crc.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/crc.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/crc.h> #elif defined(STM32L1) # include <libopencm3/stm32/l1/crc.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/crc.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/crc.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/dac.h b/include/libopencm3/stm32/dac.h index 0f348bb4..6a17a738 100644 --- a/include/libopencm3/stm32/dac.h +++ b/include/libopencm3/stm32/dac.h @@ -30,8 +30,12 @@ # include <libopencm3/stm32/f3/dac.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/dac.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/dac.h> #elif defined(STM32L1) # include <libopencm3/stm32/l1/dac.h> +#elif defined(STM32L4) +# include <libopencm3/stm32/l4/dac.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/dma.h b/include/libopencm3/stm32/dma.h index e4a4ea16..8ed90c27 100644 --- a/include/libopencm3/stm32/dma.h +++ b/include/libopencm3/stm32/dma.h @@ -30,6 +30,8 @@ # include <libopencm3/stm32/f3/dma.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/dma.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/dma.h> #elif defined(STM32L0) # include <libopencm3/stm32/l0/dma.h> #elif defined(STM32L1) diff --git a/include/libopencm3/stm32/dma2d.h b/include/libopencm3/stm32/dma2d.h index 178c1b07..ab4e1f28 100644 --- a/include/libopencm3/stm32/dma2d.h +++ b/include/libopencm3/stm32/dma2d.h @@ -22,6 +22,8 @@ #if defined(STM32F4) # include <libopencm3/stm32/f4/dma2d.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/dma2d.h> #else # error "dma2d.h not available for this family." #endif diff --git a/include/libopencm3/stm32/dsi.h b/include/libopencm3/stm32/dsi.h index a6074781..b811f10c 100644 --- a/include/libopencm3/stm32/dsi.h +++ b/include/libopencm3/stm32/dsi.h @@ -19,6 +19,8 @@ #if defined(STM32F4) # include <libopencm3/stm32/f4/dsi.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/dsi.h> #else # error "dsi.h not available for this family." #endif diff --git a/include/libopencm3/stm32/exti.h b/include/libopencm3/stm32/exti.h index a612c6eb..e34b7f09 100644 --- a/include/libopencm3/stm32/exti.h +++ b/include/libopencm3/stm32/exti.h @@ -32,12 +32,16 @@ # include <libopencm3/stm32/f3/exti.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/exti.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/exti.h> #elif defined(STM32L0) # include <libopencm3/stm32/l0/exti.h> #elif defined(STM32L1) # include <libopencm3/stm32/l1/exti.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/exti.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/exti.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/f0/adc.h b/include/libopencm3/stm32/f0/adc.h index f277dcdc..573da943 100644 --- a/include/libopencm3/stm32/f0/adc.h +++ b/include/libopencm3/stm32/f0/adc.h @@ -175,6 +175,7 @@ void adc_clear_watchdog_flag(uint32_t adc); void adc_enable_eoc_sequence_interrupt(uint32_t adc); void adc_disable_eoc_sequence_interrupt(uint32_t adc); bool adc_get_eoc_sequence_flag(uint32_t adc); +void adc_clear_eoc_sequence_flag(uint32_t adc); /* Basic configuration */ void adc_set_clk_source(uint32_t adc, uint32_t source); diff --git a/include/libopencm3/stm32/f0/dma.h b/include/libopencm3/stm32/f0/dma.h index 42b4687d..d309bf71 100644 --- a/include/libopencm3/stm32/f0/dma.h +++ b/include/libopencm3/stm32/f0/dma.h @@ -32,6 +32,7 @@ #define LIBOPENCM3_DMA_H #include <libopencm3/stm32/common/dma_common_l1f013.h> +#include <libopencm3/stm32/common/dma_common_csel.h> #endif diff --git a/include/libopencm3/stm32/f0/doc-stm32f0.h b/include/libopencm3/stm32/f0/doc-stm32f0.h index 9acbc159..84d2fa08 100644 --- a/include/libopencm3/stm32/f0/doc-stm32f0.h +++ b/include/libopencm3/stm32/f0/doc-stm32f0.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32F0 +/** @page libopencm3 STM32F0 * * @version 1.0.0 * diff --git a/include/libopencm3/stm32/f0/exti.h b/include/libopencm3/stm32/f0/exti.h index 3a99f5bb..0a3aebad 100644 --- a/include/libopencm3/stm32/f0/exti.h +++ b/include/libopencm3/stm32/f0/exti.h @@ -35,6 +35,9 @@ /**@{*/ #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> + + /**@}*/ #endif diff --git a/include/libopencm3/stm32/f0/irq.json b/include/libopencm3/stm32/f0/irq.json index 8a407dc2..ab7c9f8f 100644 --- a/include/libopencm3/stm32/f0/irq.json +++ b/include/libopencm3/stm32/f0/irq.json @@ -10,8 +10,8 @@ "exti4_15", "tsc", "dma1_channel1", - "dma1_channel2_3", - "dma1_channel4_5", + "dma1_channel2_3_dma2_channel1_2", + "dma1_channel4_7_dma2_channel3_5", "adc_comp", "tim1_brk_up_trg_com", "tim1_cc", diff --git a/include/libopencm3/stm32/f0/memorymap.h b/include/libopencm3/stm32/f0/memorymap.h index ccb26ae8..12e6c58e 100644 --- a/include/libopencm3/stm32/f0/memorymap.h +++ b/include/libopencm3/stm32/f0/memorymap.h @@ -54,6 +54,7 @@ #define USART2_BASE (PERIPH_BASE_APB + 0x4400) #define USART3_BASE (PERIPH_BASE_APB + 0x4800) #define USART4_BASE (PERIPH_BASE_APB + 0x4C00) +#define USART5_BASE (PERIPH_BASE_APB + 0x5000) #define I2C1_BASE (PERIPH_BASE_APB + 0x5400) #define I2C2_BASE (PERIPH_BASE_APB + 0x5800) @@ -69,6 +70,10 @@ #define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000) #define EXTI_BASE (PERIPH_BASE_APB + 0x10400) +#define USART6_BASE (PERIPH_BASE_APB + 0x11400) +#define USART7_BASE (PERIPH_BASE_APB + 0x11800) +#define USART8_BASE (PERIPH_BASE_APB + 0x11C00) + #define ADC_BASE (PERIPH_BASE_APB + 0x12400) #define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) #define SPI1_BASE (PERIPH_BASE_APB + 0x13000) @@ -84,6 +89,7 @@ #define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000) /* DMA is the name in the F0 refman, but all other stm32's use DMA1 */ #define DMA1_BASE DMA_BASE +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) #define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) diff --git a/include/libopencm3/stm32/f0/rcc.h b/include/libopencm3/stm32/f0/rcc.h index ab066ea7..3bd4f58f 100644 --- a/include/libopencm3/stm32/f0/rcc.h +++ b/include/libopencm3/stm32/f0/rcc.h @@ -108,6 +108,9 @@ Control</b> #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT) +/** @defgroup rcc_cfgr_pmf PLLMUL: PLL multiplication factor + * @{ + */ #define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT) @@ -123,28 +126,42 @@ Control</b> #define RCC_CFGR_PLLMUL_MUL14 (0x0C << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL15 (0x0D << RCC_CFGR_PLLMUL_SHIFT) #define RCC_CFGR_PLLMUL_MUL16 (0x0E << RCC_CFGR_PLLMUL_SHIFT) +/**@}*/ #define RCC_CFGR_PLLXTPRE (1<<17) +/** @defgroup rcc_cfgr_hsepre PLLXTPRE: HSE divider for PLL source + * @{ + */ #define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 #define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 +/**@}*/ #define RCC_CFGR_PLLSRC (1<<16) +/** @defgroup rcc_cfgr_pcs PLLSRC: PLL Clock source + * @{ + */ #define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 #define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +/**@}*/ #define RCC_CFGR_PLLSRC0 (1<<15) #define RCC_CFGR_ADCPRE (1<<14) #define RCC_CFGR_PPRE_SHIFT 8 #define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT) +/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB prescale Factors +@{*/ #define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV2 (4 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV4 (5 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV8 (6 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_DIV16 (7 << RCC_CFGR_PPRE_SHIFT) +/**@}*/ #define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT) +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors +@{*/ #define RCC_CFGR_HPRE_NODIV (0x0 << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV2 (0x8 << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV4 (0x9 << RCC_CFGR_HPRE_SHIFT) @@ -154,6 +171,7 @@ Control</b> #define RCC_CFGR_HPRE_DIV128 (0xd << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV256 (0xe << RCC_CFGR_HPRE_SHIFT) #define RCC_CFGR_HPRE_DIV512 (0xf << RCC_CFGR_HPRE_SHIFT) +/**@}*/ #define RCC_CFGR_SWS_SHIFT 2 #define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) @@ -195,8 +213,8 @@ Control</b> #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_DBGMCURST (1 << 22) #define RCC_APB2RSTR_TIM17RST (1 << 18) #define RCC_APB2RSTR_TIM16RST (1 << 17) @@ -205,10 +223,15 @@ Control</b> #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_TIM1RST (1 << 11) #define RCC_APB2RSTR_ADCRST (1 << 9) +#define RCC_APB2RSTR_USART8RST (1 << 7) +#define RCC_APB2RSTR_USART7RST (1 << 6) +#define RCC_APB2RSTR_USART6RST (1 << 5) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_CECRST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) @@ -217,6 +240,7 @@ Control</b> #define RCC_APB1RSTR_USBRST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART5RST (1 << 20) #define RCC_APB1RSTR_USART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) @@ -227,9 +251,10 @@ Control</b> #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_AHBENR values --------------------------------------------------- */ - +/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values +@{*/ #define RCC_AHBENR_TSCEN (1 << 24) #define RCC_AHBENR_GPIOFEN (1 << 22) #define RCC_AHBENR_GPIOEEN (1 << 21) @@ -240,10 +265,13 @@ Control</b> #define RCC_AHBENR_CRCEN (1 << 6) #define RCC_AHBENR_FLTFEN (1 << 4) #define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMAEN (1 << 0) - -/* --- RCC_APB2ENR values -------------------------------------------------- */ +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) +#define RCC_AHBENR_DMAEN RCC_AHBENR_DMA1EN /* compatibility alias */ +/**@}*/ +/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values +@{*/ #define RCC_APB2ENR_DBGMCUEN (1 << 22) #define RCC_APB2ENR_TIM17EN (1 << 18) #define RCC_APB2ENR_TIM16EN (1 << 17) @@ -252,10 +280,14 @@ Control</b> #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_ADCEN (1 << 9) +#define RCC_APB2ENR_USART8EN (1 << 7) +#define RCC_APB2ENR_USART7EN (1 << 6) +#define RCC_APB2ENR_USART6EN (1 << 5) #define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0) +/**@}*/ -/* --- RCC_APB1ENR values -------------------------------------------------- */ - +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@{*/ #define RCC_APB1ENR_CECEN (1 << 30) #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) @@ -264,6 +296,7 @@ Control</b> #define RCC_APB1ENR_USBEN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) #define RCC_APB1ENR_USART4EN (1 << 19) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) @@ -274,6 +307,7 @@ Control</b> #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ /* --- RCC_BDCR values ----------------------------------------------------- */ @@ -312,8 +346,8 @@ Control</b> #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) -/* --- RCC_AHBRSTR values -------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values +@{*/ #define RCC_AHBRSTR_TSCRST (1 << 24) #define RCC_AHBRSTR_IOPFRST (1 << 22) #define RCC_AHBRSTR_IOPERST (1 << 21) @@ -321,6 +355,7 @@ Control</b> #define RCC_AHBRSTR_IOPCRST (1 << 19) #define RCC_AHBRSTR_IOPBRST (1 << 18) #define RCC_AHBRSTR_IOPARST (1 << 17) +/**@}*/ /* --- RCC_CFGR2 values ---------------------------------------------------- */ @@ -418,6 +453,9 @@ enum rcc_periph_clken { /* APB2 peripherals */ RCC_SYSCFG_COMP = _REG_BIT(0x18, 0), + RCC_USART6 = _REG_BIT(0x18, 5), + RCC_USART7 = _REG_BIT(0x18, 6), + RCC_USART8 = _REG_BIT(0x18, 7), RCC_ADC = _REG_BIT(0x18, 9), RCC_ADC1 = _REG_BIT(0x18, 9), /* Compatibility alias */ RCC_TIM1 = _REG_BIT(0x18, 11), @@ -439,6 +477,7 @@ enum rcc_periph_clken { RCC_USART2 = _REG_BIT(0x1C, 17), RCC_USART3 = _REG_BIT(0x1C, 18), RCC_USART4 = _REG_BIT(0x1C, 19), + RCC_USART5 = _REG_BIT(0x1C, 20), RCC_I2C1 = _REG_BIT(0x1C, 21), RCC_I2C2 = _REG_BIT(0x1C, 22), RCC_USB = _REG_BIT(0x1C, 23), diff --git a/include/libopencm3/stm32/f0/syscfg.h b/include/libopencm3/stm32/f0/syscfg.h index 7e796a05..fcfb74ab 100644 --- a/include/libopencm3/stm32/f0/syscfg.h +++ b/include/libopencm3/stm32/f0/syscfg.h @@ -91,7 +91,7 @@ /* SYSCFG_EXTICR Values -- --------------------------------------------------*/ -#define SYSCFG_EXTICR_SKIP 4 +#define SYSCFG_EXTICR_FIELDSIZE 4 #define SYSCFG_EXTICR_GPIOA 0 #define SYSCFG_EXTICR_GPIOB 1 #define SYSCFG_EXTICR_GPIOC 2 diff --git a/include/libopencm3/stm32/f0/usart.h b/include/libopencm3/stm32/f0/usart.h index 72d82836..869f4843 100644 --- a/include/libopencm3/stm32/f0/usart.h +++ b/include/libopencm3/stm32/f0/usart.h @@ -34,14 +34,25 @@ #include <libopencm3/stm32/common/usart_common_all.h> #include <libopencm3/stm32/common/usart_common_v2.h> +/**@{*/ + /*****************************************************************************/ /* Module definitions */ /*****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses + * Holds all the U(S)ART peripherals supported. + * @{ + */ #define USART1 USART1_BASE #define USART2 USART2_BASE #define USART3 USART3_BASE #define USART4 USART4_BASE +#define USART5 USART5_BASE +#define USART6 USART6_BASE +#define USART7 USART7_BASE +#define USART8 USART8_BASE +/**@}*/ /*****************************************************************************/ /* Register values */ @@ -55,5 +66,7 @@ BEGIN_DECLS END_DECLS +/**@}*/ + #endif diff --git a/include/libopencm3/stm32/f1/doc-stm32f1.h b/include/libopencm3/stm32/f1/doc-stm32f1.h index 21d1bb9c..55c9b9f0 100644 --- a/include/libopencm3/stm32/f1/doc-stm32f1.h +++ b/include/libopencm3/stm32/f1/doc-stm32f1.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32F1 +/** @page libopencm3 STM32F1 @version 1.0.0 diff --git a/include/libopencm3/stm32/f1/exti.h b/include/libopencm3/stm32/f1/exti.h index 10882107..8fe1862a 100644 --- a/include/libopencm3/stm32/f1/exti.h +++ b/include/libopencm3/stm32/f1/exti.h @@ -37,5 +37,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h index 2de19ce9..e8b42506 100644 --- a/include/libopencm3/stm32/f1/gpio.h +++ b/include/libopencm3/stm32/f1/gpio.h @@ -933,10 +933,10 @@ Line Devices only /**@}*/ -/* --- AFIO_EXTICR1 values ------------------------------------------------- */ -/* --- AFIO_EXTICR2 values ------------------------------------------------- */ -/* --- AFIO_EXTICR3 values ------------------------------------------------- */ -/* --- AFIO_EXTICR4 values ------------------------------------------------- */ +/* --- AFIO_EXTICRx values ------------------------------------------------- */ + +/** EXTICR port selection bits */ +#define AFIO_EXTICR_FIELDSIZE 4 /** @defgroup afio_exti Alternate Function EXTI pin number @ingroup gpio_defines diff --git a/include/libopencm3/stm32/f2/doc-stm32f2.h b/include/libopencm3/stm32/f2/doc-stm32f2.h index 813ce747..0b928b85 100644 --- a/include/libopencm3/stm32/f2/doc-stm32f2.h +++ b/include/libopencm3/stm32/f2/doc-stm32f2.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32F2 +/** @page libopencm3 STM32F2 @version 1.0.0 diff --git a/include/libopencm3/stm32/f2/exti.h b/include/libopencm3/stm32/f2/exti.h index d21a921a..5015cde7 100644 --- a/include/libopencm3/stm32/f2/exti.h +++ b/include/libopencm3/stm32/f2/exti.h @@ -37,5 +37,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h index 7e2be9c6..f0c13535 100644 --- a/include/libopencm3/stm32/f2/rcc.h +++ b/include/libopencm3/stm32/f2/rcc.h @@ -208,8 +208,10 @@ #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) -/* --- RCC_AHB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) +@{*/ +/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values +@{*/ #define RCC_AHB1RSTR_OTGHSRST (1 << 29) #define RCC_AHB1RSTR_ETHMACRST (1 << 25) #define RCC_AHB1RSTR_DMA2RST (1 << 22) @@ -224,6 +226,7 @@ #define RCC_AHB1RSTR_GPIOCRST (1 << 2) #define RCC_AHB1RSTR_GPIOBRST (1 << 1) #define RCC_AHB1RSTR_GPIOARST (1 << 0) +/**@}*/ /** @addtogroup deprecated_201802_rcc Deprecated 2018 * @deprecated replace zzz_IOPxRST with zzz_GPIOxRST @@ -240,20 +243,23 @@ #define RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST /**@}*/ -/* --- RCC_AHB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values +@{*/ #define RCC_AHB2RSTR_OTGFSRST (1 << 7) #define RCC_AHB2RSTR_RNGRST (1 << 6) #define RCC_AHB2RSTR_HASHRST (1 << 5) #define RCC_AHB2RSTR_CRYPRST (1 << 4) #define RCC_AHB2RSTR_DCMIRST (1 << 0) +/**@}*/ -/* --- RCC_AHB3RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values +@{*/ #define RCC_AHB3RSTR_FSMCRST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) #define RCC_APB1RSTR_CAN2RST (1 << 26) @@ -277,9 +283,10 @@ #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_TIM11RST (1 << 18) #define RCC_APB2RSTR_TIM10RST (1 << 17) #define RCC_APB2RSTR_TIM9RST (1 << 16) @@ -291,9 +298,12 @@ #define RCC_APB2RSTR_USART1RST (1 << 4) #define RCC_APB2RSTR_TIM8RST (1 << 1) #define RCC_APB2RSTR_TIM1RST (1 << 0) +/**@}*/ -/* --- RCC_AHB1ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) +@{*/ +/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values +@{*/ #define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) #define RCC_AHB1ENR_OTGHSEN (1 << 29) #define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) @@ -313,6 +323,7 @@ #define RCC_AHB1ENR_GPIOCEN (1 << 2) #define RCC_AHB1ENR_GPIOBEN (1 << 1) #define RCC_AHB1ENR_GPIOAEN (1 << 0) +/**@}*/ /** @addtogroup deprecated_201802_rcc Deprecated 2018 * @deprecated replace zzz_IOPxEN with zzz_GPIOxEN @@ -329,20 +340,23 @@ #define RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN /**@}*/ -/* --- RCC_AHB2ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values +@{*/ #define RCC_AHB2ENR_OTGFSEN (1 << 7) #define RCC_AHB2ENR_RNGEN (1 << 6) #define RCC_AHB2ENR_HASHEN (1 << 5) #define RCC_AHB2ENR_CRYPEN (1 << 4) #define RCC_AHB2ENR_DCMIEN (1 << 0) +/**@}*/ -/* --- RCC_AHB3ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values +@{*/ #define RCC_AHB3ENR_FSMCEN (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1ENR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@{*/ #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_CAN2EN (1 << 26) @@ -366,9 +380,10 @@ #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ -/* --- RCC_APB2ENR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@{*/ #define RCC_APB2ENR_TIM11EN (1 << 18) #define RCC_APB2ENR_TIM10EN (1 << 17) #define RCC_APB2ENR_TIM9EN (1 << 16) @@ -382,6 +397,7 @@ #define RCC_APB2ENR_USART1EN (1 << 4) #define RCC_APB2ENR_TIM8EN (1 << 1) #define RCC_APB2ENR_TIM1EN (1 << 0) +/**@}*/ /* --- RCC_AHB1LPENR values ------------------------------------------------- */ diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index 0e8ef4e1..041562f4 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -37,6 +37,8 @@ #include <libopencm3/stm32/common/adc_common_v2.h> #include <libopencm3/stm32/common/adc_common_v2_multi.h> +/**@{*/ + /** @defgroup adc_reg_base ADC register base addresses @ingroup STM32xx_adc_defines @{*/ @@ -551,5 +553,6 @@ bool adc_awd(uint32_t adc); END_DECLS +/**@}*/ #endif diff --git a/include/libopencm3/stm32/f3/doc-stm32f3.h b/include/libopencm3/stm32/f3/doc-stm32f3.h index a562f11d..8732388e 100644 --- a/include/libopencm3/stm32/f3/doc-stm32f3.h +++ b/include/libopencm3/stm32/f3/doc-stm32f3.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32F3 +/** @page libopencm3 STM32F3 * * @version 1.0.0 * diff --git a/include/libopencm3/stm32/f3/exti.h b/include/libopencm3/stm32/f3/exti.h index d94916db..c5ef4e93 100644 --- a/include/libopencm3/stm32/f3/exti.h +++ b/include/libopencm3/stm32/f3/exti.h @@ -38,6 +38,7 @@ /**@{*/ #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> /* --- EXTI registers ------------------------------------------------------ */ #define EXTI_IMR2 MMIO32(EXTI_BASE + 0x18) diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h index c9624333..c83b2ac6 100644 --- a/include/libopencm3/stm32/f3/rcc.h +++ b/include/libopencm3/stm32/f3/rcc.h @@ -201,8 +201,8 @@ #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_TIM20RST (1 << 20) #define RCC_APB2RSTR_TIM17RST (1 << 18) #define RCC_APB2RSTR_TIM16RST (1 << 17) @@ -213,9 +213,10 @@ #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_TIM1RST (1 << 11) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_I2C3RST (1 << 30) #define RCC_APB1RSTR_DAC1RST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) @@ -236,8 +237,10 @@ #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_AHBENR values --------------------------------------------------- */ +/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values + *@{*/ #define RCC_AHBENR_ADC34EN (1 << 29) #define RCC_AHBENR_ADC12EN (1 << 28) #define RCC_AHBENR_TSCEN (1 << 24) @@ -255,9 +258,10 @@ #define RCC_AHBENR_SRAMEN (1 << 2) #define RCC_AHBENR_DMA2EN (1 << 1) #define RCC_AHBENR_DMA1EN (1 << 0) +/*@}*/ -/* --- RCC_APB2ENR values -------------------------------------------------- */ - +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@{*/ #define RCC_APB2ENR_TIM20EN (1 << 20) #define RCC_APB2ENR_TIM17EN (1 << 18) #define RCC_APB2ENR_TIM16EN (1 << 17) @@ -268,9 +272,10 @@ #define RCC_APB2ENR_SPI1EN (1 << 12) #define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_SYSCFGEN (1 << 0) +/**@}*/ -/* --- RCC_APB1ENR values -------------------------------------------------- */ - +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@{*/ #define RCC_APB1ENR_I2C3EN (1 << 30) #define RCC_APB1ENR_DAC1EN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) @@ -291,6 +296,7 @@ #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ /* --- RCC_BDCR values ----------------------------------------------------- */ @@ -315,7 +321,8 @@ #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) -/* --- RCC_AHBRSTR values -------------------------------------------------- */ +/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) +@{*/ #define RCC_AHBRSTR_ADC34RST (1 << 29) #define RCC_AHBRSTR_ADC12RST (1 << 28) #define RCC_AHBRSTR_TSCRST (1 << 24) @@ -328,6 +335,7 @@ #define RCC_AHBRSTR_IOPARST (1 << 17) #define RCC_AHBRSTR_IOPHRST (1 << 16) #define RCC_AHBRSTR_FMCRST (1 << 5) +/**@}*/ /* --- RCC_CFGR2 values ---------------------------------------------------- */ /* ADCxxPRES: ADCxx prescaler */ diff --git a/include/libopencm3/stm32/f3/usart.h b/include/libopencm3/stm32/f3/usart.h index dc180950..860eba09 100644 --- a/include/libopencm3/stm32/f3/usart.h +++ b/include/libopencm3/stm32/f3/usart.h @@ -34,9 +34,9 @@ #include <libopencm3/stm32/common/usart_common_all.h> #include <libopencm3/stm32/common/usart_common_v2.h> +/**@{*/ /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ @@ -51,5 +51,7 @@ BEGIN_DECLS END_DECLS +/**@}*/ + #endif diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h index a2de1f66..6c502488 100644 --- a/include/libopencm3/stm32/f4/adc.h +++ b/include/libopencm3/stm32/f4/adc.h @@ -7,7 +7,7 @@ Converters</b> @version 1.0.0 -@author @htmlonly © @endhtmlonly 2012 +@author @htmlonly © @endhtmlonly 2019 Matthew Lai <m@matthewlai.ca> @author @htmlonly © @endhtmlonly 2009 Edward Cheeseman <evbuilder@users.sourceforge.net> @@ -19,7 +19,7 @@ LGPL License Terms @ref lgpl_license /* * This file is part of the libopencm3 project. * - * Copyright (C) 2012 Matthew Lai <m@matthewlai.ca> + * Copyright (C) 2019 Matthew Lai <m@matthewlai.ca> * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net> * * This library is free software: you can redistribute it and/or modify @@ -39,9 +39,7 @@ LGPL License Terms @ref lgpl_license #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H -#include <libopencm3/stm32/common/adc_common_v1.h> - -/* --- Convenience macros -------------------------------------------------- */ +#include <libopencm3/stm32/common/adc_common_v1_multi.h> /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ #define ADC_JOFR1(block) MMIO32((block) + 0x14) @@ -76,14 +74,6 @@ LGPL License Terms @ref lgpl_license /* ADC regular data register (ADC_DR) */ #define ADC_DR(block) MMIO32((block) + 0x4c) -/* ADC common (shared) registers */ -#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) -#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) -#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) -#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) - -/* --- ADC Channels ------------------------------------------------------- */ - /** @defgroup adc_channel ADC Channel Numbers * @ingroup adc_defines * Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18! @@ -94,60 +84,12 @@ LGPL License Terms @ref lgpl_license #define ADC_CHANNEL_VBAT 18 /**@}*/ -/* --- ADC_SR values ------------------------------------------------------- */ - -/** @defgroup adc_sr_values ADC Status Register Flags - * @ingroup adc_defines - *@{*/ - -/* OVR:*//** Overrun */ -#define ADC_SR_OVR (1 << 5) -/**@}*/ - -/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */ - -/* OVRIE: Overrun interrupt enable */ -#define ADC_CR1_OVRIE (1 << 26) - -/* RES[1:0]: Resolution */ -/****************************************************************************/ -/** @defgroup adc_cr1_res ADC Resolution. -@ingroup adc_defines - -@{*/ -#define ADC_CR1_RES_12BIT (0x0 << 24) -#define ADC_CR1_RES_10BIT (0x1 << 24) -#define ADC_CR1_RES_8BIT (0x2 << 24) -#define ADC_CR1_RES_6BIT (0x3 << 24) -/**@}*/ -#define ADC_CR1_RES_MASK (0x3 << 24) -#define ADC_CR1_RES_SHIFT 24 - -/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ /* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ #define ADC_CR1_AWDCH_MAX 18 -/* --- ADC_CR2 values ------------------------------------------------------ */ - -/* SWSTART: Start conversion of regular channels. */ -#define ADC_CR2_SWSTART (1 << 30) - -/* EXTEN[1:0]: External trigger enable for regular channels. */ -/****************************************************************************/ -/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity -@ingroup adc_defines - -@{*/ -#define ADC_CR2_EXTEN_DISABLED (0x0 << 28) -#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28) -#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28) -#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28) -/**@}*/ -#define ADC_CR2_EXTEN_MASK (0x3 << 28) -#define ADC_CR2_EXTEN_SHIFT 28 - +/* --- Convenience macros -------------------------------------------------- */ /* EXTSEL[3:0]: External event selection for regular group. */ /****************************************************************************/ /** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group @@ -187,27 +129,6 @@ LGPL License Terms @ref lgpl_license /** EXTI Line 11 Event */ #define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) /**@}*/ -#define ADC_CR2_EXTSEL_MASK (0xF << 24) -#define ADC_CR2_EXTSEL_SHIFT 24 - -/* Bit 23 is reserved */ - -/* JSWSTART: Start conversion of injected channels. */ -#define ADC_CR2_JSWSTART (1 << 22) - -/* JEXTEN[1:0]: External trigger enable for injected channels. */ -/****************************************************************************/ -/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity -@ingroup adc_defines - -@{*/ -#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) -#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20) -#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20) -#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20) -/**@}*/ -#define ADC_CR2_JEXTEN_MASK (0x3 << 20) -#define ADC_CR2_JEXTEN_SHIFT 20 /* JEXTSEL[3:0]: External event selection for injected group. */ /****************************************************************************/ @@ -232,80 +153,7 @@ LGPL License Terms @ref lgpl_license #define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) #define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16) /**@}*/ -#define ADC_CR2_JEXTSEL_MASK (0xF << 16) -#define ADC_CR2_JEXTSEL_SHIFT 16 -/* ALIGN: Data alignement. */ -#define ADC_CR2_ALIGN_RIGHT (0 << 11) -#define ADC_CR2_ALIGN_LEFT (1 << 11) -#define ADC_CR2_ALIGN (1 << 11) - -/* EOCS: End of conversion selection. */ -#define ADC_CR2_EOCS (1 << 10) - -/* DDS: DMA disable selection */ -#define ADC_CR2_DDS (1 << 9) - -/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ -#define ADC_CR2_DMA (1 << 8) - -/* Note: Bits [7:2] are reserved and must be kept at reset value. */ - -/* CONT: Continuous conversion. */ -#define ADC_CR2_CONT (1 << 1) - -/* ADON: A/D converter On/Off. */ -/* Note: If any other bit in this register apart from ADON is changed at the - * same time, then conversion is not triggered. This is to prevent triggering - * an erroneous conversion. - * Conclusion: Must be separately written. - */ -#define ADC_CR2_ADON (1 << 0) - -/* --- ADC_SMPR1 values ---------------------------------------------------- */ - -#define ADC_SMPR1_SMP17_LSB 21 -#define ADC_SMPR1_SMP16_LSB 18 -#define ADC_SMPR1_SMP15_LSB 15 -#define ADC_SMPR1_SMP14_LSB 12 -#define ADC_SMPR1_SMP13_LSB 9 -#define ADC_SMPR1_SMP12_LSB 6 -#define ADC_SMPR1_SMP11_LSB 3 -#define ADC_SMPR1_SMP10_LSB 0 -#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMPR1_SMP17_LSB) -#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMPR1_SMP16_LSB) -#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMPR1_SMP15_LSB) -#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMPR1_SMP14_LSB) -#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMPR1_SMP13_LSB) -#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMPR1_SMP12_LSB) -#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMPR1_SMP11_LSB) -#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMPR1_SMP10_LSB) - -/* --- ADC_SMPR2 values ---------------------------------------------------- */ - -#define ADC_SMPR2_SMP9_LSB 27 -#define ADC_SMPR2_SMP8_LSB 24 -#define ADC_SMPR2_SMP7_LSB 21 -#define ADC_SMPR2_SMP6_LSB 18 -#define ADC_SMPR2_SMP5_LSB 15 -#define ADC_SMPR2_SMP4_LSB 12 -#define ADC_SMPR2_SMP3_LSB 9 -#define ADC_SMPR2_SMP2_LSB 6 -#define ADC_SMPR2_SMP1_LSB 3 -#define ADC_SMPR2_SMP0_LSB 0 -#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMPR2_SMP9_LSB) -#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMPR2_SMP8_LSB) -#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMPR2_SMP7_LSB) -#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMPR2_SMP6_LSB) -#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMPR2_SMP5_LSB) -#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMPR2_SMP4_LSB) -#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMPR2_SMP3_LSB) -#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMPR2_SMP2_LSB) -#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMPR2_SMP1_LSB) -#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMPR2_SMP0_LSB) - -/* --- ADC_SMPRx values --------------------------------------------------- */ -/****************************************************************************/ /* ADC_SMPRG ADC Sample Time Selection for Channels */ /** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels @ingroup adc_defines @@ -322,127 +170,9 @@ LGPL License Terms @ref lgpl_license /**@}*/ /* --- ADC_SQR1 values ----------------------------------------------------- */ - -#define ADC_SQR_MAX_CHANNELS_REGULAR 16 - -#define ADC_SQR1_SQ16_LSB 15 -#define ADC_SQR1_SQ15_LSB 10 -#define ADC_SQR1_SQ14_LSB 5 -#define ADC_SQR1_SQ13_LSB 0 #define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) -#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) -#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) -#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) -#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) - -/* --- ADC_SQR2 values ----------------------------------------------------- */ - -#define ADC_SQR2_SQ12_LSB 25 -#define ADC_SQR2_SQ11_LSB 20 -#define ADC_SQR2_SQ10_LSB 15 -#define ADC_SQR2_SQ9_LSB 10 -#define ADC_SQR2_SQ8_LSB 5 -#define ADC_SQR2_SQ7_LSB 0 -#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) -#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) -#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) -#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) -#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) -#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) - -/* --- ADC_SQR3 values ----------------------------------------------------- */ - -#define ADC_SQR3_SQ6_LSB 25 -#define ADC_SQR3_SQ5_LSB 20 -#define ADC_SQR3_SQ4_LSB 15 -#define ADC_SQR3_SQ3_LSB 10 -#define ADC_SQR3_SQ2_LSB 5 -#define ADC_SQR3_SQ1_LSB 0 -#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) -#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) -#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) -#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) -#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) -#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) - -/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ - -#define ADC_JDATA_LSB 0 -#define ADC_DATA_LSB 0 -#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) -#define ADC_DATA_MSK (0xffff << ADC_DA) - -/* --- Common Registers ---------------------------------------------------- */ - -/* --- ADC_CSR values (read only images) ------------------------------------ */ - -/* OVR3: Overrun ADC3. */ -#define ADC_CSR_OVR3 (1 << 21) -/* STRT3: Regular channel start ADC3. */ -#define ADC_CSR_STRT3 (1 << 20) - -/* JSTRT3: Injected channel start ADC3. */ -#define ADC_CSR_JSTRT3 (1 << 19) - -/* JEOC3: Injected channel end of conversion ADC3. */ -#define ADC_CSR_JEOC3 (1 << 18) - -/* EOC3: Regular channel end of conversion ADC3. */ -#define ADC_CSR_EOC3 (1 << 17) - -/* EOC3: Regular channel end of conversion ADC3. */ -#define ADC_CSR_AWD3 (1 << 16) - -/* Bits 15:14 Reserved, must be kept at reset value */ - -/* OVR2: Overrun ADC2. */ -#define ADC_CSR_OVR2 (1 << 13) - -/* STRT2: Regular channel start ADC2. */ -#define ADC_CSR_STRT2 (1 << 12) - -/* JSTRT2: Injected channel start ADC2. */ -#define ADC_CSR_JSTRT2 (1 << 11) - -/* JEOC2: Injected channel end of conversion ADC2. */ -#define ADC_CSR_JEOC2 (1 << 10) - -/* EOC2: Regular channel end of conversion ADC2. */ -#define ADC_CSR_EOC2 (1 << 9) - -/* EOC2: Regular channel end of conversion ADC2. */ -#define ADC_CSR_AWD2 (1 << 8) - -/* Bits 7:6 Reserved, must be kept at reset value */ - -/* OVR1: Overrun ADC1. */ -#define ADC_CSR_OVR1 (1 << 5) - -/* STRT1: Regular channel start ADC1. */ -#define ADC_CSR_STRT1 (1 << 4) - -/* JSTRT1: Injected channel start ADC1. */ -#define ADC_CSR_JSTRT1 (1 << 3) - -/* JEOC1: Injected channel end of conversion ADC1. */ -#define ADC_CSR_JEOC1 (1 << 2) - -/* EOC1: Regular channel end of conversion ADC1. */ -#define ADC_CSR_EOC1 (1 << 1) - -/* EOC1: Regular channel end of conversion ADC1. */ -#define ADC_CSR_AWD1 (1 << 0) - -/* --- ADC_CCR values ------------------------------------------------------ */ - -/* TSVREFE: Temperature sensor and Vrefint enable. */ -#define ADC_CCR_TSVREFE (1 << 23) - -/* VBATE: VBat enable. */ -#define ADC_CCR_VBATE (1 << 22) - -/* Bit 18:21 reserved, must be kept at reset value. */ +#define ADC_SQR_MAX_CHANNELS_REGULAR 16 /* ADCPRE: ADC prescaler. */ /****************************************************************************/ @@ -458,140 +188,13 @@ LGPL License Terms @ref lgpl_license #define ADC_CCR_ADCPRE_MASK (0x3 << 16) #define ADC_CCR_ADCPRE_SHIFT 16 -/* DMA: Direct memory access mode for multi ADC mode. */ -/****************************************************************************/ -/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode -@ingroup adc_defines - -@{*/ -#define ADC_CCR_DMA_DISABLE (0x0 << 14) -#define ADC_CCR_DMA_MODE_1 (0x1 << 14) -#define ADC_CCR_DMA_MODE_2 (0x2 << 14) -#define ADC_CCR_DMA_MODE_3 (0x3 << 14) -/**@}*/ -#define ADC_CCR_DMA_MASK (0x3 << 14) -#define ADC_CCR_DMA_SHIFT 14 - -/* DDS: DMA disable selection (for multi-ADC mode). */ -#define ADC_CCR_DDS (1 << 13) - -/* Bit 12 reserved, must be kept at reset value */ - -/* DELAY: Delay between 2 sampling phases. */ -/****************************************************************************/ -/** @defgroup adc_delay ADC Delay between 2 sampling phases -@ingroup adc_defines - -@{*/ -#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) -#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) -#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) -#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) -#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) -#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) -#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) -#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) -#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) -#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) -#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) -#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) -#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) -#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) -#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) -#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) -/**@}*/ -#define ADC_CCR_DELAY_MASK (0xf << 8) -#define ADC_CCR_DELAY_SHIFT 8 - -/* Bit 7:5 reserved, must be kept at reset value */ - -/* MULTI: Multi ADC mode selection. */ -/****************************************************************************/ -/** @defgroup adc_multi_mode ADC Multi mode selection -@ingroup adc_defines - -@{*/ - -/** All ADCs independent */ -#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) - -/* Dual modes (ADC1 + ADC2) */ -/** - * Dual modes (ADC1 + ADC2) Combined regular simultaneous + - * injected simultaneous mode. - */ -#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) -/** - * Dual modes (ADC1 + ADC2) Combined regular simultaneous + - * alternate trigger mode. - */ -#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) -/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) -/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) -/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ -#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) -/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ -#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) - -/* Triple modes (ADC1 + ADC2 + ADC3) */ -/** - * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + - * injected simultaneous mode. - */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) -/** - * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + - * alternate trigger mode. - */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ -#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) -/**@}*/ - -#define ADC_CCR_MULTI_MASK (0x1f << 0) -#define ADC_CCR_MULTI_SHIFT 0 - -/* --- ADC_CDR values ------------------------------------------------------ */ - -#define ADC_CDR_DATA2_MASK (0xffff << 16) -#define ADC_CDR_DATA2_SHIFT 16 - -#define ADC_CDR_DATA1_MASK (0xffff << 0) -#define ADC_CDR_DATA1_SHIFT 0 BEGIN_DECLS -void adc_set_clk_prescale(uint32_t prescaler); void adc_set_multi_mode(uint32_t mode); -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_set_resolution(uint32_t adc, uint32_t resolution); -void adc_enable_overrun_interrupt(uint32_t adc); -void adc_disable_overrun_interrupt(uint32_t adc); -bool adc_get_overrun_flag(uint32_t adc); -void adc_clear_overrun_flag(uint32_t adc); -bool adc_awd(uint32_t adc); -void adc_eoc_after_each(uint32_t adc); -void adc_eoc_after_group(uint32_t adc); -void adc_set_dma_continue(uint32_t adc); -void adc_set_dma_terminate(uint32_t adc); -void adc_enable_temperature_sensor(void); -void adc_disable_temperature_sensor(void); void adc_enable_vbat_sensor(void); void adc_disable_vbat_sensor(void); END_DECLS -/**@}*/ - #endif diff --git a/include/libopencm3/stm32/f4/crypto.h b/include/libopencm3/stm32/f4/crypto.h index 3dd433f7..5e6d4e46 100644 --- a/include/libopencm3/stm32/f4/crypto.h +++ b/include/libopencm3/stm32/f4/crypto.h @@ -1,6 +1,6 @@ /** @defgroup crypto_defines CRYPTO Defines * - * @brief <b>Defined constants and Types for the STM32F4xx Crypto Coprocessor + * @brief <b>Defined constants and Types for the STM32F4xx Crypto Coprocessor</b> * * @ingroup STM32F4xx_defines * diff --git a/include/libopencm3/stm32/f4/dac.h b/include/libopencm3/stm32/f4/dac.h index f7714f3d..3a384032 100644 --- a/include/libopencm3/stm32/f4/dac.h +++ b/include/libopencm3/stm32/f4/dac.h @@ -34,4 +34,3 @@ LGPL License Terms @ref lgpl_license #include <libopencm3/stm32/common/dac_common_all.h> #endif - diff --git a/include/libopencm3/stm32/f4/dma2d.h b/include/libopencm3/stm32/f4/dma2d.h index 7d6e1abc..80c23599 100644 --- a/include/libopencm3/stm32/f4/dma2d.h +++ b/include/libopencm3/stm32/f4/dma2d.h @@ -1,20 +1,8 @@ /** @defgroup dma2d_defines DMA2D Defines - * + * @brief <b>Defined Constants and Types for the STM32F4xx DMA2D Peripheral</b> * @ingroup STM32F4xx_defines - * - * @brief Defined Constants and Macros for the STM32x4xx DMA2D Peripheral - * - * @version 1.0.0 - * - * @date 15 August 2016 - * LGPL License Terms @ref lgpl_license */ - /* - * STM32F4 DMA2D Register defines - * - * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com> - * * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify @@ -29,159 +17,14 @@ * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. - * */ - -#include <libopencm3/stm32/memorymap.h> -#include <stdint.h> - -#ifndef DMA2D_H -#define DMA2D_H - /**@{*/ -/** DMA2D Control Register */ -#define DMA2D_CR MMIO32(DMA2D_BASE + 0x0U) -#define DMA2D_CR_MODE_SHIFT 16 -#define DMA2D_CR_MODE_MASK 0x3 -#define DMA2D_CR_MODE_M2M 0 /* memory to memory */ -#define DMA2D_CR_MODE_M2MWPFC 1 /* memory to memory with pix convert */ -#define DMA2D_CR_MODE_M2MWB 2 /* memory to memory with blend */ -#define DMA2D_CR_MODE_R2M 3 /* register to memory */ -#define DMA2D_CR_CEIE (1 << 13) -#define DMA2D_CR_CTCIE (1 << 12) -#define DMA2D_CR_CAEIE (1 << 11) -#define DMA2D_CR_TWIE (1 << 10) -#define DMA2D_CR_TCIE (1 << 9) -#define DMA2D_CR_TEIE (1 << 8) -#define DMA2D_CR_ABORT (1 << 2) -#define DMA2D_CR_SUSP (1 << 1) -#define DMA2D_CR_START (1 << 0) - -/** DMA2D Interrupt Status Register */ -#define DMA2D_ISR MMIO32(DMA2D_BASE + 0x4U) -#define DMA2D_ISR_CEIF (1 << 5) -#define DMA2D_ISR_CTCIF (1 << 4) -#define DMA2D_ISR_CAEIF (1 << 3) -#define DMA2D_ISR_TWIF (1 << 2) -#define DMA2D_ISR_TCIF (1 << 1) -#define DMA2D_ISR_TEIF (1 << 0) - -/** DMA2D Interrupt Flag Clear Register */ -#define DMA2D_IFCR MMIO32(DMA2D_BASE + 0x8U) -#define DMA2D_IFCR_CCEIF (1 << 5) -#define DMA2D_IFCR_CCTCIF (1 << 4) -#define DMA2D_IFCR_CCAEIF (1 << 3) -#define DMA2D_IFCR_CTWIF (1 << 2) -#define DMA2D_IFCR_CTCIF (1 << 1) -#define DMA2D_IFCR_CTEIF (1 << 0) - -/** DMA2D Foreground Memory Address Register */ -#define DMA2D_FGMAR MMIO32(DMA2D_BASE + 0xCU) - -/** DMA2D Foreground Offset Register */ -#define DMA2D_FGOR MMIO32(DMA2D_BASE + 0x10U) -#define DMA2D_FGOR_LO_SHIFT 0 -#define DMA2D_FGOR_LO_MASK 0x3fff - -/** DMA2D Background Memory Address Register */ -#define DMA2D_BGMAR MMIO32(DMA2D_BASE + 0x14U) - -/** DMA2D Background Offset Register */ -#define DMA2D_BGOR MMIO32(DMA2D_BASE + 0x18U) -#define DMA2D_BGOR_LO_SHIFT 0 -#define DMA2D_BGOR_LO_MASK 0x3fff - -/** DMA2D Foreground and Background PFC Control Register */ -#define DMA2D_FGPFCCR MMIO32(DMA2D_BASE + 0x1cU) -#define DMA2D_BGPFCCR MMIO32(DMA2D_BASE + 0x24U) - -#define DMA2D_xPFCCR_ALPHA_SHIFT 24 -#define DMA2D_xPFCCR_ALPHA_MASK 0xff -#define DMA2D_xPFCCR_AM_SHIFT 16 -#define DMA2D_xPFCCR_AM_MASK 0x3 -#define DMA2D_xPFCCR_AM_NONE 0 -#define DMA2D_xPFCCR_AM_FORCE 1 -#define DMA2D_xPFCCR_AM_PRODUCT 2 -#define DMA2D_xPFCCR_CS_SHIFT 8 -#define DMA2D_xPFCCR_CS_MASK 0xff -#define DMA2D_xPFCCR_START (1 << 5) -#define DMA2D_xPFCCR_CCM_ARGB8888 (0 << 4) -#define DMA2D_xPFCCR_CCM_RGB888 (1 << 4) -#define DMA2D_xPFCCR_CM_SHIFT 0 -#define DMA2D_xPFCCR_CM_MASK 0xf -#define DMA2D_xPFCCR_CM_ARGB8888 0 -#define DMA2D_xPFCCR_CM_RGB888 1 -#define DMA2D_xPFCCR_CM_RGB565 2 -#define DMA2D_xPFCCR_CM_ARGB1555 3 -#define DMA2D_xPFCCR_CM_ARGB4444 4 -#define DMA2D_xPFCCR_CM_L8 5 -#define DMA2D_xPFCCR_CM_AL44 6 -#define DMA2D_xPFCCR_CM_AL88 7 -#define DMA2D_xPFCCR_CM_L4 8 -#define DMA2D_xPFCCR_CM_A8 9 -#define DMA2D_xPFCCR_CM_A4 10 - -/** DMA2D Foreground and Background Color Register */ -#define DMA2D_FGCOLR MMIO32(DMA2D_BASE + 0x20U) -#define DMA2D_BGCOLR MMIO32(DMA2D_BASE + 0x28U) -#define DMA2D_xCOLR_RED_SHIFT 16 -#define DMA2D_xCOLR_RED_MASK 0xff -#define DMA2D_xCOLR_GREEN_SHIFT 8 -#define DMA2D_xCOLR_GREEN_MASK 0xff -#define DMA2D_xCOLR_BLUE_SHIFT 0 -#define DMA2D_xCOLR_BLUE_MASK 0xff - -/** DMA2D Foreground CLUT Memory Address Register */ -#define DMA2D_FGCMAR MMIO32(DMA2D_BASE + 0x2CU) - -/** DMA2D Background CLUT Memory Address Register */ -#define DMA2D_BGCMAR MMIO32(DMA2D_BASE + 0x30U) - -/** DMA2D Output PFC Control Register */ -#define DMA2D_OPFCCR MMIO32(DMA2D_BASE + 0x34U) -#define DMA2D_OPFCCR_CM_SHIFT 0 -#define DMA2D_OPFCCR_CM_MASK 0x3 -#define DMA2D_OPFCCR_CM_ARGB8888 0 -#define DMA2D_OPFCCR_CM_RGB888 1 -#define DMA2D_OPFCCR_CM_RGB565 2 -#define DMA2D_OPFCCR_CM_ARGB4444 3 - -/** DMA2D Output Color Register */ -/* The format of this register depends on PFC control above */ -#define DMA2D_OCOLR MMIO32(DMA2D_BASE + 0x38U) - -/** DMA2D Output Memory Address Register */ -#define DMA2D_OMAR MMIO32(DMA2D_BASE + 0x3CU) - -/** DMA2D Output offset Register */ -#define DMA2D_OOR MMIO32(DMA2D_BASE + 0x40U) -#define DMA2D_OOR_LO_SHIFT 0 -#define DMA2D_OOR_LO_MASK 0x3fff - -/** DMA2D Number of Lines Register */ -#define DMA2D_NLR MMIO32(DMA2D_BASE + 0x44U) -#define DMA2D_NLR_PL_SHIFT 16 -#define DMA2D_NLR_PL_MASK 0x3fff -#define DMA2D_NLR_NL_SHIFT 0 -#define DMA2D_NLR_NL_MASK 0xffff - -/** DMA2D Line Watermark Register */ -#define DMA2D_LWR MMIO32(DMA2D_BASE + 0x48U) -#define DMA2D_LWR_LW_SHIFT 0 -#define DMA2D_LWR_LW_MASK 0xffff - -/** DMA2D AHB Master Timer Config Register */ -#define DMA2D_AMTCR MMIO32(DMA2D_BASE + 0x4CU) -#define DMA2D_AMTCR_DT_SHIFT 8 -#define DMA2D_AMTCR_DT_MASK 0xff -#define DMA2D_AMTCR_EN (1 << 0) +#ifndef LIBOPENCM3_STM32_F4_DMA2D_H_ +#define LIBOPENCM3_STM32_F4_DMA2D_H_ -/** DMA2D Foreground Color Lookup table */ -#define DMA2D_FG_CLUT (uint32_t *)(DMA2D_BASE + 0x400U) +#include <libopencm3/stm32/common/dma2d_common_f47.h> -/** DMA2D Background Color Lookup table */ -#define DMA2D_BG_CLUT (uint32_t *)(DMA2D_BASE + 0x800U) +#endif /* LIBOPENCM3_STM32_F4_DMA2D_H_ */ /**@}*/ -#endif diff --git a/include/libopencm3/stm32/f4/doc-stm32f4.h b/include/libopencm3/stm32/f4/doc-stm32f4.h index f0868ab8..1c17a1fa 100644 --- a/include/libopencm3/stm32/f4/doc-stm32f4.h +++ b/include/libopencm3/stm32/f4/doc-stm32f4.h @@ -1,10 +1,10 @@ -/** @mainpage libopencm3 STM32F4 +/** @page libopencm3 STM32F4 @version 1.0.0 @date 7 September 2012 -API documentation for ST Microelectronics STM32F4 Cortex M3 series. +API documentation for ST Microelectronics STM32F4 Cortex M4F series. LGPL License Terms @ref lgpl_license */ diff --git a/include/libopencm3/stm32/f4/dsi.h b/include/libopencm3/stm32/f4/dsi.h index cf70c001..dc8a639a 100644 --- a/include/libopencm3/stm32/f4/dsi.h +++ b/include/libopencm3/stm32/f4/dsi.h @@ -1,21 +1,9 @@ /** @defgroup dsi_defines DSI Defines - * + * @brief <b>Defines Constants and Macros for the STM32F4xx Display Serial + * Interface Host and Wrapper</b> * @ingroup STM32F4xx_defines - * - * @brief Defined Constants and Macros for the STM32F4xx DSI Peripheral - * - * @version 1.0.0 - * - * @date 7 July 2016 - * - * LGPL License Terms @ref lgpl_license */ - /* - * STM32F4 DSI Host Defines - * - * Copyright (C) 2016, Chuck McManis <cmcmanis@mcmanis.com> - * * This file is part of the libopencm3 project. * * This library is free software: you can redistribute it and/or modify @@ -30,788 +18,14 @@ * * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. - * */ - -#include <libopencm3/cm3/common.h> -#include <libopencm3/stm32/memorymap.h> - -#ifndef DSI_H -#define DSI_H - /**@{*/ +#ifndef LIBOPENCM3_STM32_F4_DSI_H_ +#define LIBOPENCM3_STM32_F4_DSI_H_ -/** - * DSI Host Version Register - */ -#define DSI_VR MMIO32(DSI_BASE + 0x0U) - -/** - * DSI Host Control Register - */ -#define DSI_CR MMIO32(DSI_BASE + 0x4U) -#define DSI_CR_EN (1 << 0) - -/** - * DSI Host Clock Control Register - */ -#define DSI_CCR MMIO32(DSI_BASE + 0x8U) -#define DSI_CCR_TOCKDIV_SHIFT 8 -#define DSI_CCR_TOCKDIV_MASK 0xff -#define DSI_CCR_TXECKDIV_SHIFT 0 -#define DSI_CCR_TXECKDIV_MASK 0xff - -/** - * DSI Host LTDC VCID Register - */ -#define DSI_LVCIDR MMIO32(DSI_BASE + 0xcU) -#define DSI_LVCIDR_VCID_SHIFT 0 -#define DSI_LVCIDR_VCID_MASK 0x3 - -/** - * DSI Host LTDC Color Coding Register - */ -#define DSI_LCOLCR MMIO32(DSI_BASE + 0x10U) -#define DSI_LCOLCR_LPE (1 << 8) -#define DSI_LCOLCR_COLC_SHIFT 0 -#define DSI_LCOLCR_COLC_MASK 0xf - -/** - * DSI Host LTDC Polarity Configuration Register - */ -#define DSI_LPCR MMIO32(DSI_BASE + 0x14U) -#define DSI_LPCR_HSP (1 << 2) -#define DSI_LPCR_VSP (1 << 1) -#define DSI_LPCR_DEP (1 << 0) - -/** - * DSI Host Low-power Configuration Register - */ -#define DSI_LPMCR MMIO32(DSI_BASE + 0x18U) -#define DSI_LPMCR_LPSIZE_SHIFT 16 -#define DSI_LPMCR_LPSIZE_MASK 0xff -#define DSI_LPMCR_VLPSIZE_SHIFT 0 -#define DSI_LPMCR_VLPSIZE_MASK 0xff - -/** - * DSI Host Protocol Configuration Register - */ -#define DSI_PCR MMIO32(DSI_BASE + 0x2cU) -#define DSI_PCR_CRCRXE (1 << 4) -#define DSI_PCR_ECCRXE (1 << 3) -#define DSI_PCR_BTAE (1 << 2) -#define DSI_PCR_ETRXE (1 << 1) -#define DSI_PCR_ETTXE (1 << 0) - -/** - * DSI Host Generic VCID Register - */ -#define DSI_GVCIDR MMIO32(DSI_BASE + 0x30U) -#define DSI_GVCIDR_VCID_SHIFT 0 -#define DSI_GVCIDR_VCID_MASK 0x3 - -/** - * DSI Host mode Configuration Register - */ -#define DSI_MCR MMIO32(DSI_BASE + 0x34U) -#define DSI_MCR_CMDM (1 << 0) - -/** - * DSI Host Video mode Configuration Register - */ -#define DSI_VMCR MMIO32(DSI_BASE + 0x38U) -#define DSI_VMCR_PGO (1 << 24) -#define DSI_VMCR_PGM (1 << 20) -#define DSI_VMCR_PGE (1 << 16) -#define DSI_VMCR_LPCE (1 << 15) -#define DSI_VMCR_FBTAAE (1 << 14) -#define DSI_VMCR_LPHFE (1 << 13) -#define DSI_VMCR_LPHBPE (1 << 12) -#define DSI_VMCR_LPVAE (1 << 11) -#define DSI_VMCR_LPVFPE (1 << 10) -#define DSI_VMCR_LPVBPE (1 << 9) -#define DSI_VMCR_LPVSAE (1 << 8) -#define DSI_VMCR_VMT_SHIFT 0 -#define DSI_VMCR_VMT_MASK 0x3 -#define DSI_VMCR_VMT_NON_BURST_PULSE 0x0 -#define DSI_VMCR_VMT_NON_BURSE_EVENT 0x1 -#define DSI_VMCR_VMT_BURST 0x2 - -/** - * DSI Host Video Packet Configuration Register - */ -#define DSI_VPCR MMIO32(DSI_BASE + 0x3CU) -#define DSI_VPCR_VPSIZE_SHIFT 0 -#define DSI_VPCR_VPSIZE_MASK 0x3fff - -/** - * DSI Host Video Chunks Configuration Register - */ -#define DSI_VCCR MMIO32(DSI_BASE + 0x40U) -#define DSI_VCCR_NUMC_SHIFT 0 -#define DSI_VCCR_NUMC_MASK 0x1fff - -/** - * DSI Host Video Null Packet Configuration Register - */ -#define DSI_VNPCR MMIO32(DSI_BASE + 0x44U) -#define DSI_VNPCR_NPSIZE_SHIFT 0 -#define DSI_VNPCR_NPSIZE_MASK 0x1fff - -/** - * DSI Host Video HSA Configuration Register - */ -#define DSI_VHSACR MMIO32(DSI_BASE + 0x48U) -#define DSI_VHSACR_HSA_SHIFT 0 -#define DSI_VHSACR_HSA_MASK 0xfff - -/** - * DSI Host Video HBP Configuration Register - */ -#define DSI_VHBPCR MMIO32(DSI_BASE + 0x4CU) -#define DSI_VHBPCR_HBP_SHIFT 0 -#define DSI_VHBPCR_HBP_MASK 0xfff - -/** - * DSI Host Video Line Configuration Register - */ -#define DSI_VLCR MMIO32(DSI_BASE + 0x50U) -#define DSI_VLCR_HLINE_SHIFT 0 -#define DSI_VLCR_HLINE_MASK 0x7fff - -/** - * DSI Host Video VSA Configuration Register - */ -#define DSI_VVSACR MMIO32(DSI_BASE + 0x54U) -#define DSI_VVSACR_VSA_SHIFT 0 -#define DSI_VVSACR_VSA_MASK 0x3ff - -/** - * DSI Host Video VBP Configuration Register - */ -#define DSI_VVBPCR MMIO32(DSI_BASE + 0x58U) -#define DSI_VVBPCR_VBP_SHIFT 0 -#define DSI_VVBPCR_VBP_MASK 0x3ff - -/** - * DSI Host Video VFP Configuration Register - */ -#define DSI_VVFPCR MMIO32(DSI_BASE + 0x5CU) -#define DSI_VVFPCR_VFP_SHIFT 0 -#define DSI_VVFPCR_VFP_MASK 0x3ff - -/** - * DSI Host Video VA Configuration Register - */ -#define DSI_VVACR MMIO32(DSI_BASE + 0x60U) -#define DSI_VVACR_VA_SHIFT 0 -#define DSI_VVACR_VA_MASK 0x3fff - -/** - * DSI Host LTDC Command Configuration Register - */ -#define DSI_LCCR MMIO32(DSI_BASE + 0x64U) -#define DSI_LCCR_CMDSIZE_SHIFT 0 -#define DSI_LCCR_CMDSIZE_MASK 0xffff - -/** - * DSI Host Command mode Configuration Register - */ -#define DSI_CMCR MMIO32(DSI_BASE + 0x68U) -#define DSI_CMCR_MRDPS (1 << 24) -#define DSI_CMCR_DLWTX (1 << 19) -#define DSI_CMCR_DSR0TX (1 << 18) -#define DSI_CMCR_DSW1TX (1 << 17) -#define DSI_CMCR_DSW0TX (1 << 16) -/* Bit 15 reserved */ -#define DSI_CMCR_GLWTX (1 << 14) -#define DSI_CMCR_GSR2TX (1 << 13) -#define DSI_CMCR_GSR1TX (1 << 12) -#define DSI_CMCR_GSR0TX (1 << 11) -#define DSI_CMCR_GSW2TX (1 << 10) -#define DSI_CMCR_GSW1TX (1 << 9) -#define DSI_CMCR_GSW0TX (1 << 8) -/* Bits 7:2 Reserved */ -#define DSI_CMCR_ARE (1 << 1) -#define DSI_CMCR_TEARE (1 << 0) - -/** - * DSI Host Generic Header Configuration Register - */ -#define DSI_GHCR MMIO32(DSI_BASE + 0x6CU) -#define DSI_GHCR_WCMSB_SHIFT 16 -#define DSI_GHCR_WCMSB_MASK 0xff -#define DSI_GHCR_WCLSB_SHIFT 8 -#define DSI_GHCR_WCLSB_MASK 0xff -#define DSI_GHCR_DATA1_SHIFT 16 /* data 1 in 'short' mode */ -#define DSI_GHCR_DATA1_MASK 0xff -#define DSI_GHCR_DATA0_SHIFT 8 /* data 0 in 'short' mode */ -#define DSI_GHCR_DATA0_MASK 0xff -#define DSI_GHCR_VCID_SHIFT 6 -#define DSI_GHCR_VCID_MASK 0x3 -#define DSI_GHCR_DT_SHIFT 0 -#define DSI_GHCR_DT_MASK 0x3f - -/** - * DSI Host Generic Payload Data Register - */ -#define DSI_GPDR MMIO32(DSI_BASE + 0x70U) -#define DSI_GPDR_BYTE4_SHIFT 24 -#define DSI_GPDR_BYTE4_MASK 0xff -#define DSI_GPDR_BYTE3_SHIFT 16 -#define DSI_GPDR_BYTE3_MASK 0xff -#define DSI_GPDR_BYTE2_SHIFT 8 -#define DSI_GPDR_BYTE2_MASK 0xff -#define DSI_GPDR_BYTE1_SHIFT 0 -#define DSI_GPDR_BYTE1_MASK 0xff - -/** - * DSI Host Generate Packet Status Register - */ -#define DSI_GPSR MMIO32(DSI_BASE + 0x74U) -/* Reserved 31:7 */ -#define DSI_GPSR_RCB (1 << 6) -#define DSI_GPSR_PRDFF (1 << 5) -#define DSI_GPSR_PRDFE (1 << 4) -#define DSI_GPSR_PWRFF (1 << 3) -#define DSI_GPSR_PWRFE (1 << 2) -#define DSI_GPSR_CMDFF (1 << 1) -#define DSI_GPSR_CMDFE (1 << 0) - -/** - * DSI Host Timeout Counter Configuration Register - */ -#define DSI_TCCR0 MMIO32(DSI_BASE + 0x78U) -#define DSI_TCCR0_HSTX_TOCNT_SHIFT 16 -#define DSI_TCCR0_HSTX_TOCNT_MASK 0xffff -#define DSI_TCCR0_LPRX_TOCNT_SHIFT 0 -#define DSI_TCCR0_LPRX_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 1 - */ -#define DSI_TCCR1 MMIO32(DSI_BASE + 0x7CU) -#define DSI_TCCR1_HSRD_TOCNT_SHIFT 0 -#define DSI_TCCR1_HSRD_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 2 - */ -#define DSI_TCCR2 MMIO32(DSI_BASE + 0x80U) -#define DSI_TCCR2_LPRD_TOCNT_SHIFT 0 -#define DSI_TCCR2_LPRD_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 3 - */ -#define DSI_TCCR3 MMIO32(DSI_BASE + 0x84U) -#define DSI_TCCR3_PM (1 << 24) -#define DSI_TCCR3_HSWR_TOCNT_SHIFT 0 -#define DSI_TCCR3_HSWR_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 4 - */ -#define DSI_TCCR4 MMIO32(DSI_BASE + 0x88U) -#define DSI_TCCR4_LSWR_TOCNT_SHIFT 0 -#define DSI_TCCR4_LSWR_TOCNT_MASK 0xffff - -/** - * DSI Host Timeout Counter Configuration Register 5 - */ -#define DSI_TCCR5 MMIO32(DSI_BASE + 0x8CU) -#define DSI_TCCR5_BTA_TOCNT_SHIFT 0 -#define DSI_TCCR5_BTA_TOCNT_MASK 0xffff - -/** - * DSI Host Clock Lane Configuration Register - */ -#define DSI_CLCR MMIO32(DSI_BASE + 0x94U) -#define DSI_CLCR_ACR (1 << 1) -#define DSI_CLCR_DPCC (1 << 0) - -/** - * DSI Host Clock Lane Timer Configuration Register - */ -#define DSI_CLTCR MMIO32(DSI_BASE + 0x98U) -#define DSI_CLTCR_HS2LP_TIME_SHIFT 16 -#define DSI_CLTCR_HS2LP_TIME_MASK 0x3ff -#define DSI_CLTCR_LP2HS_TIME_SHIFT 0 -#define DSI_CLTCR_LP2HS_TIME_MASK 0x3ff - -/** - * DSI Host Data Lane Time Configuration Register - */ -#define DSI_DLTCR MMIO32(DSI_BASE + 0x9CU) -#define DSI_DLTCR_HS2LP_TIME_SHIFT 24 -#define DSI_DLTCR_HS2LP_TIME_MASK 0xff -#define DSI_DLTCR_LP2HS_TIME_SHIFT 16 -#define DSI_DLTCR_LP2HS_TIME_MASK 0xff -#define DSI_DLTCR_MRD_TIME_SHIFT 0 -#define DSI_DLTCR_MRD_TIME_MASK 0x7fff - -/** - * DSI Host PHY Control Register - */ -#define DSI_PCTLR MMIO32(DSI_BASE + 0xA0U) -#define DSI_PCTLR_CKE (1 << 2) -#define DSI_PCTLR_DEN (1 << 1) - -/** - * DSI Host PHY Configuration Register - */ -#define DSI_PCONFR MMIO32(DSI_BASE + 0xA4U) -#define DSI_PCONFR_SW_TIME_SHIFT 8 -#define DSI_PCONFR_SW_TIME_MASK 0xff -#define DSI_PCONFR_NL_SHIFT 0 -#define DSI_PCONFR_NL_MASK 0x3 -#define DSI_PCONFR_NL_1LANE 0 -#define DSI_PCONFR_NL_2LANE 1 - -/** - * DSI Host PHY ULPS Control Register - */ -#define DSI_PUCR MMIO32(DSI_BASE + 0xA8U) -#define DSI_PUCR_UEDL (1 << 3) -#define DSI_PUCR_URDL (1 << 2) -#define DSI_PUCR_UECL (1 << 1) -#define DSI_PUCR_URCL (1 << 0) - -/** - * DSI Host PHY TX Triggers Configuration Register - */ -#define DSI_PTTCR MMIO32(DSI_BASE + 0xACU) -#define DSI_PTTCR_TX_TRIG_SHIFT 0 -#define DSI_PTTCR_TX_TRIG_MASK 0xf -#define DSI_PTTCR_TX_TRIG_1 0x1 -#define DSI_PTTCR_TX_TRIG_2 0x2 -#define DSI_PTTCR_TX_TRIG_3 0x4 -#define DSI_PTTCR_TX_TRIG_4 0x8 - -/** - * DSI Host PHY Status Register - */ -#define DSI_PSR MMIO32(DSI_BASE + 0xB0U) -#define DSI_PSR_UAN1 (1 << 8) -#define DSI_PSR_PSS1 (1 << 7) -#define DSI_PSR_RUE0 (1 << 6) -#define DSI_PSR_UAN0 (1 << 5) -#define DSI_PSR_PSS0 (1 << 4) -#define DSI_PSR_UANC (1 << 3) -#define DSI_PSR_PSSC (1 << 2) -#define DSI_PSR_PD (1 << 1) - -/** - * DSI Host Interrupt & Status Register 0 - */ -#define DSI_ISR0 MMIO32(DSI_BASE + 0xBCU) -#define DSI_ISR0_PE4 (1 << 20) -#define DSI_ISR0_PE3 (1 << 19) -#define DSI_ISR0_PE2 (1 << 18) -#define DSI_ISR0_PE1 (1 << 17) -#define DSI_ISR0_PE0 (1 << 16) -#define DSI_ISR0_AE15 (1 << 15) -#define DSI_ISR0_AE14 (1 << 14) -#define DSI_ISR0_AE13 (1 << 13) -#define DSI_ISR0_AE12 (1 << 12) -#define DSI_ISR0_AE11 (1 << 11) -#define DSI_ISR0_AE10 (1 << 10) -#define DSI_ISR0_AE9 (1 << 9) -#define DSI_ISR0_AE8 (1 << 8) -#define DSI_ISR0_AE7 (1 << 7) -#define DSI_ISR0_AE6 (1 << 6) -#define DSI_ISR0_AE5 (1 << 5) -#define DSI_ISR0_AE4 (1 << 4) -#define DSI_ISR0_AE3 (1 << 3) -#define DSI_ISR0_AE2 (1 << 2) -#define DSI_ISR0_AE1 (1 << 1) -#define DSI_ISR0_AE0 (1 << 0) - -/** - * DSI Host Interrupt & Status Register 1 - */ -#define DSI_ISR1 MMIO32(DSI_BASE + 0xC0U) -#define DSI_ISR1_GPRXE (1 << 12) -#define DSI_ISR1_GPRDE (1 << 11) -#define DSI_ISR1_GPTXE (1 << 10) -#define DSI_ISR1_GPWRE (1 << 9) -#define DSI_ISR1_GCWRE (1 << 8) -#define DSI_ISR1_LPWRE (1 << 7) -#define DSI_ISR1_EOTPE (1 << 6) -#define DSI_ISR1_PSE (1 << 5) -#define DSI_ISR1_CRCE (1 << 4) -#define DSI_ISR1_ECCME (1 << 3) -#define DSI_ISR1_ECCSE (1 << 2) -#define DSI_ISR1_TOLPRX (1 << 1) -#define DSI_ISR1_TOHSTX (1 << 0) - -/** - * DSI Host Interrupt Enable Register 0 - */ -#define DSI_IER0 MMIO32(DSI_BASE + 0xC4U) -#define DSI_IER0_PE4IE (1 << 20) -#define DSI_IER0_PE3IE (1 << 19) -#define DSI_IER0_PE2IE (1 << 18) -#define DSI_IER0_PE1IE (1 << 17) -#define DSI_IER0_PE0IE (1 << 16) -#define DSI_IER0_AE15IE (1 << 15) -#define DSI_IER0_AE14IE (1 << 14) -#define DSI_IER0_AE13IE (1 << 13) -#define DSI_IER0_AE12IE (1 << 12) -#define DSI_IER0_AE11IE (1 << 11) -#define DSI_IER0_AE10IE (1 << 10) -#define DSI_IER0_AE9IE (1 << 9) -#define DSI_IER0_AE8IE (1 << 8) -#define DSI_IER0_AE7IE (1 << 7) -#define DSI_IER0_AE6IE (1 << 6) -#define DSI_IER0_AE5IE (1 << 5) -#define DSI_IER0_AE4IE (1 << 4) -#define DSI_IER0_AE3IE (1 << 3) -#define DSI_IER0_AE2IE (1 << 2) -#define DSI_IER0_AE1IE (1 << 1) -#define DSI_IER0_AE0IE (1 << 0) - -/** - * DSI Host Interrupt Enable Register 1 - */ -#define DSI_IER1 MMIO32(DSI_BASE + 0xC8U) -#define DSI_IER1_GPRXEIE (1 << 12) -#define DSI_IER1_GPRDEIE (1 << 11) -#define DSI_IER1_GPTXEIE (1 << 10) -#define DSI_IER1_GPWREIE (1 << 9) -#define DSI_IER1_GCWREIE (1 << 8) -#define DSI_IER1_LPWREIE (1 << 7) -#define DSI_IER1_EOTPEIE (1 << 6) -#define DSI_IER1_PSEIE (1 << 5) -#define DSI_IER1_CRCEIE (1 << 4) -#define DSI_IER1_ECCMEIE (1 << 3) -#define DSI_IER1_ECCSEIE (1 << 2) -#define DSI_IER1_TOLPRXIE (1 << 1) -#define DSI_IER1_TOHSTXIE (1 << 0) - -/** - * DSI Host Force Interrupt Register 0 - */ -#define DSI_FIR0 MMIO32(DSI_BASE + 0xD8U) -#define DSI_FIR0_FPE4 (1 << 20) -#define DSI_FIR0_FPE3 (1 << 19) -#define DSI_FIR0_FPE2 (1 << 18) -#define DSI_FIR0_FPE1 (1 << 17) -#define DSI_FIR0_FPE0 (1 << 16) -#define DSI_FIR0_FAE15 (1 << 15) -#define DSI_FIR0_FAE14 (1 << 14) -#define DSI_FIR0_FAE13 (1 << 13) -#define DSI_FIR0_FAE12 (1 << 12) -#define DSI_FIR0_FAE11 (1 << 11) -#define DSI_FIR0_FAE10 (1 << 10) -#define DSI_FIR0_FAE9 (1 << 9) -#define DSI_FIR0_FAE8 (1 << 8) -#define DSI_FIR0_FAE7 (1 << 7) -#define DSI_FIR0_FAE6 (1 << 6) -#define DSI_FIR0_FAE5 (1 << 5) -#define DSI_FIR0_FAE4 (1 << 4) -#define DSI_FIR0_FAE3 (1 << 3) -#define DSI_FIR0_FAE2 (1 << 2) -#define DSI_FIR0_FAE1 (1 << 1) -#define DSI_FIR0_FAE0 (1 << 0) - -/** - * DSI Host Force Interrupt Register 1 - */ -#define DSI_FIR1 MMIO32(DSI_BASE + 0xDCU) -#define DSI_FIR1_FGPRXE (1 << 12) -#define DSI_FIR1_FGPRDE (1 << 11) -#define DSI_FIR1_FGPTXE (1 << 10) -#define DSI_FIR1_FGPWRE (1 << 9) -#define DSI_FIR1_FGCWRE (1 << 8) -#define DSI_FIR1_FLPWRE (1 << 7) -#define DSI_FIR1_FEOTPE (1 << 6) -#define DSI_FIR1_FPSE (1 << 5) -#define DSI_FIR1_FCRCE (1 << 4) -#define DSI_FIR1_FECCME (1 << 3) -#define DSI_FIR1_FECCSE (1 << 2) -#define DSI_FIR1_FTOLPRX (1 << 1) -#define DSI_FIR1_FTOHSTX (1 << 0) - -/** - * DSI Host Video Shadow Control Register - */ -#define DSI_VSCR MMIO32(DSI_BASE + 0x100U) -#define DSI_VSCR_UR (1 << 8) -#define DSI_VSCR_EN (1 << 0) - -/** - * DSI Host LTDC Current VCID Register - */ -#define DSI_LCVCIDR MMIO32(DSI_BASE + 0x10CU) -#define DSI_LCVCIDR_VCID_SHIFT 0 -#define DSI_LCVCIDR_VCID_MASK 0x3 - -/** - * DSI Host LTCD Current Color Coding Register - */ -#define DSI_LCCCR MMIO32(DSI_BASE + 0x110U) -#define DSI_LCCR_LPE (1 << 8) -#define DSI_LCCR_COLC_SHIFT 0 -#define DSI_LCCR_COLC_MASK 0xf - -/** - * DSI Host Low-power mode Current Configuration Register - */ -#define DSI_LPMCCR MMIO32(DSI_BASE + 0x118U) -#define DSI_LPMCCR_LPSIZE_SHIFT 16 -#define DSI_LPMCCR_LPSIZE_MASK 0xff -#define DSI_LPMCCR_VLPSIZE_SHIFT 0 -#define DSI_LPMCCR_VLPSIZE_MASK 0xff - -/** - * DSI Host Video mode Current Configuration Register - */ -#define DSI_VMCCR MMIO32(DSI_BASE + 0x138U) -#define DSI_VMCCR_LPCE (1 << 9) -#define DSI_VMCCR_FBTAAE (1 << 8) -#define DSI_VMCCR_LPHFE (1 << 7) -#define DSI_VMCCR_LPHBPE (1 << 6) -#define DSI_VMCCR_LPVAE (1 << 5) -#define DSI_VMCCR_LPVFPE (1 << 4) -#define DSI_VMCCR_LPVBPE (1 << 3) -#define DSI_VMCCR_LPVSAE (1 << 2) -#define DSI_VMCCR_VMT_SHIFT 0 -#define DSI_VMCCR_VMT_MASK 0x3 - -/** - * DSI Host Video Packet Current Configuration Register - */ -#define DSI_VPCCR MMIO32(DSI_BASE + 0x13CU) -#define DSI_VPCCR_VPSIZE_SHIFT 0 -#define DSI_VPCCR_VPSIZE_MASK 0x3fff - -/** - * DSI Host Video Chunks Current Configuration Register - */ -#define DSI_VCCCR MMIO32(DSI_BASE + 0x140U) -#define DSI_VCCCR_NUMC_SHIFT 0 -#define DSI_VCCCR_NUMC_MASK 0x1fff - -/** - * DSI Host Video Null Packet Current Configuration Register - */ -#define DSI_VNPCCR MMIO32(DSI_BASE + 0x144U) -#define DSI_VNPCCR_NPSIZE_SHIFT 0 -#define DSI_VNPCCR_NPSIZE_MASK 0x1fff - -/** - * DSI Host Video HSA Current Configuration Register - */ -#define DSI_VHSACCR MMIO32(DSI_BASE + 0x148U) -#define DSI_VHSACCR_HSA_SHIFT 0 -#define DSI_VHSACCR_HSA_MASK 0xfff - -/** - * DSI Host Video HBP Current Configuration Register - */ -#define DSI_VHBPCCR MMIO32(DSI_BASE + 0x14CU) -#define DSI_VHBPCCR_HBP_SHIFT 0 -#define DSI_VHBPCCR_HBP_MASK 0xfff - -/** - * DSI Host Video Line Current Configuration Register - */ -#define DSI_VLCCR MMIO32(DSI_BASE + 0x150U) -#define DSI_VLCCR_HLINE_SHIFT 0 -#define DSI_VLCCR_HLINE_MASK 0x7fff - -/** - * DSI Host Video VSA Current Configuration Register - */ -#define DSI_VVSACCR MMIO32(DSI_BASE + 0x154U) -#define DSI_VVSACCR_VSA_SHIFT 0 -#define DSI_VVSACCR_VSA_MASK 0x3ff - -/** - * DSI Host Video VBP Current Configuration Register - */ -#define DSI_VVBPCCR MMIO32(DSI_BASE + 0x0158U) -#define DSI_VVBPCCR_VBP_SHIFT 0 -#define DSI_VVBPCCR_VBP_MAST 0x3ff - -/** - * DSI Host Video VFP Current Configuration Register - */ -#define DSI_VVFPCCR MMIO32(DSI_BASE + 0x15CU) -#define DSI_VVFPCCR_VFP_SHIFT 0 -#define DSI_VVFPCCR_VFP_MASK 0x3ff - -/** - * DSI Host Video VA Current Configuration Register - */ -#define DSI_VVACCR MMIO32(DSI_BASE + 0x160U) -#define DSI_VVACCR_VA_SHIFT 0 -#define DSI_VVACCR_VA_MASK 0x3fff - -/** - * DSI Wrapper Configuration Register - */ -#define DSI_WCFGR MMIO32(DSI_BASE + 0x400U) -#define DSI_WCFGR_VSPOL (1 << 7) -#define DSI_WCFGR_AR (1 << 6) -#define DSI_WCFGR_TEPOL (1 << 5) -#define DSI_WCFGR_TESRC (1 << 4) -#define DSI_WCFGR_COLMUX_SHIFT 1 -#define DSI_WCFGR_COLMUX_MASK 7 -#define DSI_WCFGR_DSIM (1 << 0) - -/** - * DSI Wrapper Control Register - */ -#define DSI_WCR MMIO32(DSI_BASE + 0x404U) -#define DSI_WCR_DSIEN (1 << 3) -#define DSI_WCR_LTDCEN (1 << 2) -#define DSI_WCR_SHTDN (1 << 1) -#define DSI_SCR_COLM (1 << 0) - -/** - * DSI Wrapper Interrupt Enable Register - */ -#define DSI_WIER MMIO32(DSI_BASE + 0x408U) -#define DSI_WIER_RRIE (1 << 13) -#define DSI_WIER_PLLUIE (1 << 10) -#define DSI_WIER_PLLLIE (1 << 9) -#define DSI_WIER_ERIE (1 << 1) -#define DSI_WIER_TEIE (1 << 0) - -/** - * DSI Wrapper Interrupt & Status Register - */ -#define DSI_WISR MMIO32(DSI_BASE + 0x40CU) -/* reserved 31:14 */ -#define DSI_WISR_RRIF (1 << 13) -#define DSI_WISR_RRS (1 << 12) -#define DSI_WISR_PLLUIF (1 << 10) -#define DSI_WISR_PLLLIF (1 << 9) -#define DSI_WISR_PLLLS (1 << 8) -/* reserved 7:3 */ -#define DSI_WISR_BUSY (1 << 2) -#define DSI_WISR_ERIF (1 << 1) -#define DSI_WISR_TEIF (1 << 0) - -/** - * DSI Wrapper Interrupt Flag Clear Register - */ -#define DSI_WIFCR MMIO32(DSI_BASE + 0x410U) -/* reserved 31:14 */ -#define DSI_WIFCR_CRRIF (1 << 13) -/* reserved 12:11 */ -#define DSI_WIFCR_CPLLUIF (1 << 10) -#define DSI_WIFCR_CPLLLIF (1 << 9) -/* reserved 8:2 */ -#define DSI_WIFCR_CERIF (1 << 1) -#define DSI_WIFCR_CTEIF (1 << 0) - -/** - * DSI Wrapper PHY Configuration Register 0 - */ -#define DSI_WPCR0 MMIO32(DSI_BASE + 0x418U) -#define DSI_WPCR0_TCLKPOSTEN (1 << 27) -#define DSI_WPCR0_TLPXCEN (1 << 26) -#define DSI_WPCR0_THSEXITEN (1 << 25) -#define DSI_WPCR0_TLPXDEN (1 << 24) -#define DSI_WPCR0_THSZEROEN (1 << 23) -#define DSI_WPCR0_THSTRAILEN (1 << 22) -#define DSI_WPCR0_THSPREPEN (1 << 21) -#define DSI_WPCR0_TCLKZEROEN (1 << 20) -#define DSI_WPCR0_TCLKPREPEN (1 << 19) -#define DSI_WPCR0_PDEN (1 << 18) -#define DSI_WPCR0_TDDL (1 << 16) -#define DSI_WPCR0_CDOFFDL (1 << 14) -#define DSI_WPCR0_FTXSMDL (1 << 13) -#define DSI_WPCR0_FTXSMCL (1 << 12) -#define DSI_WPCR0_HSIDL1 (1 << 11) -#define DSI_WPCR0_HSIDL0 (1 << 10) -#define DSI_WPCR0_HSICL (1 << 9) -#define DSI_WPCR0_SWDL1 (1 << 8) -#define DSI_WPCR0_SWDL0 (1 << 7) -#define DSI_WPCR0_SWCL (1 << 6) -#define DSI_WPCR0_UIX4_SHIFT 0 -#define DSI_WPCR0_UIX4_MASK 0x3f - -/** - * DSI Wrapper PHY Configration Register 1 - */ -#define DSI_WPCR1 MMIO32(DSI_BASE + 0x41CU) -#define DSI_WPCR1_LPRXFT_SHIFT 25 -#define DSI_WPCR1_LPRXFT_MASK 0x3 -#define DSI_WPCR1_FLPRXLPM (1 << 22) -#define DSI_WPCR1_HSTXSRCDL_SHIFT 18 -#define DSI_WPCR1_HSTXSRCDL_MASK 0x3 -#define DSI_WPCR1_HSTXSRCCL_SHIFT 16 -#define DSI_WPCR1_HSTXSRCCL_MASK 0x3 -#define DSI_WPCR1_SDDC (1 << 12) -#define DSI_WPCR1_LPSRCDL_SHIFT 8 -#define DSI_WPCR1_LPSRCDL_MASK 0x3 -#define DSI_WPCR1_HSTXDDL_SHIFT 2 -#define DSI_WPCR1_HSTXDDL_MASK 0x3 -#define DSI_WPCR1_HSTXDCL_SHIFT 0 -#define DSI_WPCR1_HSTXDCL_MASK 0x3 - -/** - * DSI Wrapper PHY Configuration Register 2 - */ -#define DSI_WPCR2 MMIO32(DSI_BASE + 0x420U) -#define DSI_WPCR2_THSTRAIL_SHIFT 24 -#define DSI_WPCR2_THSTRAIL_MASK 0xff -#define DSI_WPCR2_THSPREP_SHIFT 16 -#define DSI_WPCR2_THSPREP_MASK 0xff -#define DSI_WPCR2_TCLKZERO_SHIFT 8 -#define DSI_WPCR2_TCLKZERO_MASK 0xff -#define DSI_WPCR2_TCLKPREP_SHIF 0 -#define DSI_WPCR2_TCLKPREP_MASK 0xff - -/** - * DSI Wrapper PHY Configuration Register 3 - */ -#define DSI_WPCR3 MMIO32(DSI_BASE + 0x424U) -#define DSI_WPCR3_TLPXC_SHIFT 24 -#define DSI_WPCR3_TLPXC_MASK 0xff -#define DSI_WPCR3_THSEXIT_SHIFT 16 -#define DSI_WPCR3_THSEXIT_MASK 0xff -#define DSI_WPCR3_TLPXD_SHIFT 8 -#define DSI_WPCR3_TLPXD_MASK 0xff -#define DSI_WPCR3_THSZERO_SHIFT 0 -#define DSI_WPCR3_THSZERO_MASK 0xff - -/** - * DSI Wrapper PHY Configuration Register 4 - */ -#define DSI_WPCR4 MMIO32(DSI_BASE + 0x428U) -#define DSI_WPCR4_TCLKPOST_SHIFT 0 -#define DSI_WPCR4_TCLKPOST_MASK 0xff - -/** - * DSI Wrapper Regulator and PLL Control Register - */ -#define DSI_WRPCR MMIO32(DSI_BASE + 0x430U) -#define DSI_WRPCR_REGEN (1 << 24) -#define DSI_WRPCR_ODF_SHIFT 16 -#define DSI_WRPCR_ODF_MASK 0x3 -#define DSI_WRPCR_ODF_DIV_1 0 -#define DSI_WRPCR_ODF_DIV_2 1 -#define DSI_WRPCR_ODF_DIV_4 2 -#define DSI_WRPCR_ODF_DIV_8 3 -#define DSI_WRPCR_IDF_SHIFT 11 -#define DSI_WRPCR_IDF_MASK 0xf -#define DSI_WRPCR_IDF_DIV_1 1 -#define DSI_WRPCR_IDF_DIV_2 2 -#define DSI_WRPCR_IDF_DIV_3 3 -#define DSI_WRPCR_IDF_DIV_4 4 -#define DSI_WRPCR_IDF_DIV_5 5 -#define DSI_WRPCR_IDF_DIV_6 6 -#define DSI_WRPCR_IDF_DIV_7 7 -/* valid NDIV values 10 - 125 all other reserved */ -#define DSI_WRPCR_NDIV_SHIFT 2 -#define DSI_WRPCR_NDIV_MASK 0x7f -#define DSI_WRPCR_PLLEN (1 << 0) +#include <libopencm3/stm32/common/dsi_common_f47.h> #endif -/**}@*/ + +/**@}*/ diff --git a/include/libopencm3/stm32/f4/exti.h b/include/libopencm3/stm32/f4/exti.h index b9106787..8557dd7d 100644 --- a/include/libopencm3/stm32/f4/exti.h +++ b/include/libopencm3/stm32/f4/exti.h @@ -37,5 +37,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/f4/fmc.h b/include/libopencm3/stm32/f4/fmc.h index fda08f6d..920daa1a 100644 --- a/include/libopencm3/stm32/f4/fmc.h +++ b/include/libopencm3/stm32/f4/fmc.h @@ -1,8 +1,11 @@ +/** @defgroup fmc_defines FMC Defines + * @brief <b>Defined Constants and Types for the STM32F4xx Flexible Memory + * Controller</b> + * @ingroup STM32F4xx_defines + */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com> - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -16,234 +19,17 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. */ +/**@{*/ -#ifndef LIBOPENCM3_FMC_H -#define LIBOPENCM3_FMC_H +#ifndef LIBOPENCM3_F4_FMC_H +#define LIBOPENCM3_F4_FMC_H #ifndef LIBOPENCM3_FSMC_H -error "This file should not be included directly, it is included with fsmc.h" +#error "This file should not be included directly, it is included with fsmc.h" #endif -/* --- Convenience macros -------------------------------------------------- */ - -#define FMC_BANK5_BASE 0xa0000000U -#define FMC_BANK6_BASE 0xb0000000U -#define FMC_BANK7_BASE 0xc0000000U -#define FMC_BANK8_BASE 0xd0000000U - -/* --- FMC registers ------------------------------------------------------ */ - -/* SDRAM Control Registers 1 .. 2 */ -#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x)) -#define FMC_SDCR1 FMC_SDCR(0) -#define FMC_SDCR2 FMC_SDCR(1) - - -/* SDRAM Timing Registers 1 .. 2 */ -#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x)) -#define FMC_SDTR1 FMC_SDTR(0) -#define FMC_SDTR2 FMC_SDTR(1) - -/* SDRAM Command Mode Register */ -#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150) - -/* SDRAM Refresh Timer Register */ -#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154) - -/* SDRAM Status Register */ -#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158) - -/* --- FMC_SDCRx values ---------------------------------------------------- */ - -/* Bits [31:15]: Reserved. */ - -/* RPIPE: Read Pipe */ -#define FMC_SDCR_RPIPE_SHIFT 13 -#define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT) -#define FMC_SDCR_RPIPE_NONE (0 << FMC_SDCR_RPIPE_SHIFT) -#define FMC_SDCR_RPIPE_1CLK (1 << FMC_SDCR_RPIPE_SHIFT) -#define FMC_SDCR_RPIPE_2CLK (2 << FMC_SDCR_RPIPE_SHIFT) - -/* RBURST: Burst Read */ -#define FMC_SDCR_RBURST (1 << 12) - -/* SDCLK: SDRAM Clock Configuration */ -#define FMC_SDCR_SDCLK_SHIFT 10 -#define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT) -#define FMC_SDCR_SDCLK_DISABLE (0 << FMC_SDCR_SDCLK_SHIFT) -#define FMC_SDCR_SDCLK_2HCLK (2 << FMC_SDCR_SDCLK_SHIFT) -#define FMC_SDCR_SDCLK_3HCLK (3 << FMC_SDCR_SDCLK_SHIFT) - -/* WP: Write Protect */ -#define FMC_SDCR_WP_ENABLE (1 << 9) - -/* CAS: CAS Latency */ -#define FMC_SDCR_CAS_SHIFT 7 -#define FMC_SDCR_CAS_1CYC (1 << FMC_SDCR_CAS_SHIFT) -#define FMC_SDCR_CAS_2CYC (2 << FMC_SDCR_CAS_SHIFT) -#define FMC_SDCR_CAS_3CYC (3 << FMC_SDCR_CAS_SHIFT) - -/* NB: Number of Internal banks */ -#define FMC_SDCR_NB2 0 -#define FMC_SDCR_NB4 (1 << 6) - -/* MWID: Memory width */ -#define FMC_SDCR_MWID_SHIFT 4 -#define FMC_SDCR_MWID_8b (0 << FMC_SDCR_MWID_SHIFT) -#define FMC_SDCR_MWID_16b (1 << FMC_SDCR_MWID_SHIFT) -#define FMC_SDCR_MWID_32b (2 << FMC_SDCR_MWID_SHIFT) - -/* NR: Number of rows */ -#define FMC_SDCR_NR_SHIFT 2 -#define FMC_SDCR_NR_11 (0 << FMC_SDCR_NR_SHIFT) -#define FMC_SDCR_NR_12 (1 << FMC_SDCR_NR_SHIFT) -#define FMC_SDCR_NR_13 (2 << FMC_SDCR_NR_SHIFT) - -/* NC: Number of Columns */ -#define FMC_SDCR_NC_SHIFT 0 -#define FMC_SDCR_NC_8 (0 << FMC_SDCR_NC_SHIFT) -#define FMC_SDCR_NC_9 (1 << FMC_SDCR_NC_SHIFT) -#define FMC_SDCR_NC_10 (2 << FMC_SDCR_NC_SHIFT) -#define FMC_SDCR_NC_11 (3 << FMC_SDCR_NC_SHIFT) - -/* --- FMC_SDTRx values --------------------------------------------------- */ - -/* Bits [31:28]: Reserved. */ - -/* TRCD: Row to Column Delay */ -#define FMC_SDTR_TRCD_SHIFT 24 -#define FMC_SDTR_TRCD_MASK (15 << FMC_SDTR_TRCD_SHIFT) - -/* TRP: Row Precharge Delay */ -#define FMC_SDTR_TRP_SHIFT 20 -#define FMC_SDTR_TRP_MASK (15 << FMC_SDTR_TRP_SHIFT) - -/* TWR: Recovery Delay */ -#define FMC_SDTR_TWR_SHIFT 16 -#define FMC_SDTR_TWR_MASK (15 << FMC_SDTR_TWR_SHIFT) - -/* TRC: Row Cycle Delay */ -#define FMC_SDTR_TRC_SHIFT 12 -#define FMC_SDTR_TRC_MASK (15 << FMC_SDTR_TRC_SHIFT) - -/* TRAS: Self Refresh Time */ -#define FMC_SDTR_TRAS_SHIFT 8 -#define FMC_SDTR_TRAS_MASK (15 << FMC_SDTR_TRAS_SHIFT) +#include <libopencm3/stm32/common/fmc_common_f47.h> -/* TXSR: Exit Self-refresh Delay */ -#define FMC_SDTR_TXSR_SHIFT 4 -#define FMC_SDTR_TXSR_MASK (15 << FMC_SDTR_TXSR_SHIFT) - -/* TRMD: Load Mode Register to Active */ -#define FMC_SDTR_TMRD_SHIFT 0 -#define FMC_SDTR_TMRD_MASK (15 << FMC_SDTR_TMRD_SHIFT) - -/* - * Some config bits only count in CR1 or TR1, even if you - * are just configuring bank 2, so these masks let you copy - * out those bits after you have computed values for CR2 and - * TR2 and put them into CR1 and TR1 - */ -#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK) -#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \ - FMC_SDCR_RPIPE_MASK | \ - FMC_SDCR_RBURST) - -/* --- FMC_SDCMR values --------------------------------------------------- */ - -/* Bits [31:22]: Reserved. */ - -/* MRD: Mode Register Definition */ -#define FMC_SDCMR_MRD_SHIFT 9 -#define FMC_SDCMR_MRD_MASK (0x1fff << FMC_SDCMR_MRD_SHIFT) - -/* NRFS: Number of Auto-refresh */ -#define FMC_SDCMR_NRFS_SHIFT 5 -#define FMC_SDCMR_NRFS_MASK (15 << FMC_SDCMR_NRFS_SHIFT) - -/* CTB1: Command Target Bank 1 */ -#define FMC_SDCMR_CTB1 (1 << 4) - -/* CTB2: Command Target Bank 2 */ -#define FMC_SDCMR_CTB2 (1 << 3) - -/* MODE: Command Mode */ -#define FMC_SDCMR_MODE_SHIFT 0 -#define FMC_SDCMR_MODE_MASK 7 -#define FMC_SDCMR_MODE_NORMAL 0 -#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1 -#define FMC_SDCMR_MODE_PALL 2 -#define FMC_SDCMR_MODE_AUTO_REFRESH 3 -#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4 -#define FMC_SDCMR_MODE_SELF_REFRESH 5 -#define FMC_SDCMR_MODE_POWER_DOWN 6 - -/* --- FMC_SDRTR values ---------------------------------------------------- */ - -/* Bits [31:15]: Reserved. */ - -/* REIE: Refresh Error Interrupt Enable */ -#define FMC_SDRTR_REIE (1 << 14) - -/* COUNT: Refresh Timer Count */ -#define FMC_SDRTR_COUNT_SHIFT 1 -#define FMC_SDRTR_COUNT_MASK (0x1fff << FMC_SDRTR_COUNT_SHIFT) - -/* CRE: Clear Refresh Error Flag */ -#define FMC_SDRTR_CRE (1 << 0) - -/* --- FMC_SDSR values ---------------------------------------------------- */ - -/* Bits [31:6]: Reserved. */ - -/* BUSY: Set if the SDRAM is working on the command */ -#define FMC_SDSR_BUSY (1 << 5) - -/* MODES: Status modes */ -#define FMC_SDSR_MODE_NORMAL 0 -#define FMC_SDSR_MODE_SELF_REFRESH 1 -#define FMC_SDSR_MODE_POWER_DOWN 2 - -/* Mode shift */ -#define FMC_SDSR_MODE2_SHIFT 3 -#define FMC_SDSR_MODE1_SHIFT 1 - -/* RE: Refresh Error */ -#define FMC_SDSR_RE (1 << 0) - -/* Helper function for setting the timing parameters */ -struct sdram_timing { - int trcd; /* RCD Delay */ - int trp; /* RP Delay */ - int twr; /* Write Recovery Time */ - int trc; /* Row Cycle Delay */ - int tras; /* Self Refresh TIme */ - int txsr; /* Exit Self Refresh Time */ - int tmrd; /* Load to Active delay */ -}; - -/* Mode register parameters */ -#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS }; -enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL, - SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE, - SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN }; - -/* Send an array of timing parameters (indices above) to create SDTR register - * value - */ -uint32_t sdram_timing(struct sdram_timing *t); -void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd, - int autorefresh, int modereg); #endif + +/**@}*/ diff --git a/lib/stm32/f1/pwr.c b/include/libopencm3/stm32/f4/lptimer.h index 167f920d..97203ad9 100644 --- a/lib/stm32/f1/pwr.c +++ b/include/libopencm3/stm32/f4/lptimer.h @@ -1,25 +1,17 @@ -/** @defgroup pwr_file PWR +/** @defgroup lptimer_defines LPTIM Defines * - * @ingroup STM32F1xx - * - * @brief <b>libopencm3 STM32F1xx Power Control</b> + * @ingroup STM32F4xx_defines + * + * @brief <b>libopencm3 Defined Constants and Types for the STM32F4xx Low Power Timer</b> * * @version 1.0.0 * - * @author @htmlonly © @endhtmlonly 2012 - * Ken Sarkies <ksarkies@internode.on.net> - * - * @date 18 August 2012 - * - * This library supports the power control system for the - * STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics. - * * LGPL License Terms @ref lgpl_license - */ + * */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -35,9 +27,20 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ +#ifndef LIBOPENCM3_LPTIMER_H +#define LIBOPENCM3_LPTIMER_H /**@{*/ -#include <libopencm3/stm32/pwr.h> +#include <libopencm3/stm32/common/lptimer_common_all.h> +/** @defgroup lptim_reg_base Low Power Timer register base addresses +@{*/ +#define LPTIM1 LPTIM1_BASE /**@}*/ +BEGIN_DECLS + +END_DECLS + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/f4/ltdc.h b/include/libopencm3/stm32/f4/ltdc.h index 9a3abc07..810772b8 100644 --- a/include/libopencm3/stm32/f4/ltdc.h +++ b/include/libopencm3/stm32/f4/ltdc.h @@ -1,8 +1,11 @@ +/** @defgroup ltdc_defines LTDC Defines + * @brief <b>Defined Constants and Types for the STM32F4xx LCD TFT Display + * Controller</b> + * @ingroup STM32F4xx_defines + */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2014 Oliver Meier <h2obrain@gmail.com> - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -16,495 +19,13 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. */ - +/**@{*/ #ifndef LIBOPENCM3_STM32_F4_LTDC_H_ #define LIBOPENCM3_STM32_F4_LTDC_H_ - -#include <stdint.h> -#include <libopencm3/stm32/rcc.h> - -/** - * LTDC - */ - - -#define LTDC_SSCR (MMIO32(LTDC_BASE + 0x08)) -#define LTDC_BPCR (MMIO32(LTDC_BASE + 0x0C)) -#define LTDC_AWCR (MMIO32(LTDC_BASE + 0x10)) -#define LTDC_TWCR (MMIO32(LTDC_BASE + 0x14)) -#define LTDC_GCR (MMIO32(LTDC_BASE + 0x18)) -#define LTDC_SRCR (MMIO32(LTDC_BASE + 0x24)) -#define LTDC_BCCR (MMIO32(LTDC_BASE + 0x2C)) -#define LTDC_IER (MMIO32(LTDC_BASE + 0x34)) -#define LTDC_ISR (MMIO32(LTDC_BASE + 0x38)) -#define LTDC_ICR (MMIO32(LTDC_BASE + 0x3C)) -#define LTDC_LIPCR (MMIO32(LTDC_BASE + 0x40)) -#define LTDC_CPSR (MMIO32(LTDC_BASE + 0x44)) -#define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) - -/* x == LTDC_LAYER_x */ -#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) -#define LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) -#define LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) - -#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) -#define LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) -#define LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) - -#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) -#define LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) -#define LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) - -#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) -#define LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) -#define LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) - -#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) -#define LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) -#define LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) - -#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) -#define LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) -#define LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) - -#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) -#define LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) -#define LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) - -#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) -#define LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) -#define LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) - -#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) -#define LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) -#define LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) - -#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) -#define LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) -#define LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) - -#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) -#define LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) -#define LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) - -#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) -#define LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) -#define LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) - - -#define LTDC_LAYER_1 1 -#define LTDC_LAYER_2 2 - -/* --- LTDC_SSCR values ---------------------------------------------------- */ - -/* Horizontal Synchronization Width */ -#define LTDC_SSCR_HSW_SHIFT 16 -#define LTDC_SSCR_HSW_MASK 0xfff - -/* Vertical Synchronization Height */ -#define LTDC_SSCR_VSH_SHIFT 0 -#define LTDC_SSCR_VSH_MASK 0x7ff - -/* --- LTDC_BPCR values ---------------------------------------------------- */ - -/* Accumulated Horizontal Back Porch */ -#define LTDC_BPCR_AHBP_SHIFT 16 -#define LTDC_BPCR_AHBP_MASK 0xfff - -/* Accumulated Vertical Back Porch */ -#define LTDC_BPCR_AVBP_SHIFT 0 -#define LTDC_BPCR_AVBP_MASK 0x7FF - -/* --- LTDC_AWCR values ---------------------------------------------------- */ - -/* Accumulated Active Width */ -#define LTDC_AWCR_AAW_SHIFT 16 -#define LTDC_AWCR_AAW_MASK 0xfff - -/* Accumulated Active Height */ -#define LTDC_AWCR_AAH_SHIFT 0 -#define LTDC_AWCR_AAH_MASK 0x7ff - -/* --- LTDC_TWCR values ---------------------------------------------------- */ - -/* Total Width */ -#define LTDC_TWCR_TOTALW_SHIFT 16 -#define LTDC_TWCR_TOTALW_MASK 0xfff - -/* Total Height */ -#define LTDC_TWCR_TOTALH_SHIFT 0 -#define LTDC_TWCR_TOTALH_MASK 0x7ff - -/* GCR - control register */ -#define LTDC_GCR_LTDC_ENABLE (1<<0) -#define LTDC_GCR_DITHER_ENABLE (1<<16) - -#define LTDC_GCR_PCPOL_ACTIVE_LOW (0<<28) -#define LTDC_GCR_PCPOL_ACTIVE_HIGH (1<<28) - -#define LTDC_GCR_DEPOL_ACTIVE_LOW (0<<29) -#define LTDC_GCR_DEPOL_ACTIVE_HIGH (1<<29) - -#define LTDC_GCR_VSPOL_ACTIVE_LOW (0<<30) -#define LTDC_GCR_VSPOL_ACTIVE_HIGH (1<<30) - -#define LTDC_GCR_HSPOL_ACTIVE_LOW (0<<31) -#define LTDC_GCR_HSPOL_ACTIVE_HIGH (1<<31) - -/* GCR - register bit defines (no semantics) */ -#define LTDC_GCR_HSPOL (1 << 31) -#define LTDC_GCR_VSPOL (1 << 30) -#define LTDC_GCR_DEPOL (1 << 29) -#define LTDC_GCR_PCPOL (1 << 28) -#define LTDC_GCR_DITHER (1 << 16) -#define LTDC_GCR_LTDCEN (1 << 0) - -/* --- LTDC_SRCR values ---------------------------------------------------- */ - -/* Vertical Blanking Reload */ -#define LTDC_SRCR_VBR (1 << 1) - -/* Immediate Reload */ -#define LTDC_SRCR_IMR (1 << 0) - -/* LTDC_BCCR - reload control */ -#define LTDC_SRCR_RELOAD_IMR (1<<0) -#define LTDC_SRCR_RELOAD_VBR (1<<1) - -/* --- LTDC_IER values ----------------------------------------------------- */ - -/* Register Reload Interrupt Enable */ -#define LTDC_IER_RRIE (1 << 3) - -/* Transfer Error Interrupt Enable */ -#define LTDC_IER_TERRIE (1 << 2) - -/* FIFO Underrun Interrupt Enable */ -#define LTDC_IER_FUIE (1 << 1) - -/* Line Interrupt Enable */ -#define LTDC_IER_LIE (1 << 0) - -/* --- LTDC_ISR values ----------------------------------------------------- */ - -/* Register Reload Interrupt Flag */ -#define LTDC_ISR_RRIF (1 << 3) - -/* Transfer Error Interrupt Flag */ -#define LTDC_ISR_TERRIF (1 << 2) - -/* FIFO Underrun Interrupt Flag */ -#define LTDC_ISR_FUIF (1 << 1) - -/* Line Interrupt Flag */ -#define LTDC_ISR_LIF (1 << 0) - -/* --- LTDC_ICR values ----------------------------------------------------- */ - -/* Clears Register Reload Interrupt Flag */ -#define LTDC_ICR_CRRIF (1 << 3) - -/* Clears Transfer Error Interrupt Flag */ -#define LTDC_ICR_CTERRIF (1 << 2) - -/* Clears FIFO Underrun Interrupt Flag */ -#define LTDC_ICR_CFUIF (1 << 1) - -/* Clears Line Interrupt Flag */ -#define LTDC_ICR_CLIF (1 << 0) - -/* --- LTDC_LIPCR values --------------------------------------------------- */ - -/* Line Interrupt Position */ -#define LTDC_LIPCR_LIPOS_SHIFT 0 -#define LTDC_LIPCR_LIPOS_MASK 0x7ff - -/* --- LTDC_CPSR values ---------------------------------------------------- */ - -/* Current X Position */ -#define LTDC_CPSR_CXPOS_SHIFT 16 -#define LTDC_CPSR_CXPOS_MASK 0xffff - -/* Current Y Position */ -#define LTDC_CPSR_CYPOS_SHIFT 0 -#define LTDC_CPSR_CYPOS_MASK 0xffff - -/* LTDC_CDSR - display status register */ -#define LTDC_CDSR_VDES (1<<0) -#define LTDC_CDSR_HDES (1<<1) -#define LTDC_CDSR_VSYNCS (1<<2) -#define LTDC_CDSR_HSYNCS (1<<3) - -/* LTDC_LxCR - layer control */ -#define LTDC_LxCR_LAYER_ENABLE (1<<0) -#define LTDC_LxCR_COLKEY_ENABLE (1<<1) -#define LTDC_LxCR_COLTAB_ENABLE (1<<4) - -/* --- LTDC_LxWHPCR values ------------------------------------------------- */ - -/* Window Horizontal Stop Position */ -#define LTDC_LxWHPCR_WHSPPOS_SHIFT 16 -#define LTDC_LxWHPCR_WHSPPOS_MASK 0xfff - -/* Window Horizontal Start Position */ -#define LTDC_LxWHPCR_WHSTPOS_SHIFT 0 -#define LTDC_LxWHPCR_WHSTPOS_MASK 0xfff - -/* --- LTDC_LxWVPCR values ------------------------------------------------- */ - -/* Window Vertical Stop Position */ -#define LTDC_LxWVPCR_WVSPPOS_SHIFT 16 -#define LTDC_LxWVPCR_WVSPPOS_MASK 0x7ff - -/* Window Vertical Start Position */ -#define LTDC_LxWVPCR_WVSTPOS_SHIFT 0 -#define LTDC_LxWVPCR_WVSTPOS_MASK 0x7ff - -/* --- LTDC_LxCKCR values -------------------------------------------------- */ - -/* Color Key Red */ -#define LTDC_LxCKCR_CKRED_SHIFT 16 -#define LTDC_LxCKCR_CKRED_MASK 0xff - -/* Color Key Green */ -#define LTDC_LxCKCR_CKGREEN_SHIFT 16 -#define LTDC_LxCKCR_CKGREEN_MASK 0xff - -/* Color Key Blue */ -#define LTDC_LxCKCR_CKBLUE_SHIFT 16 -#define LTDC_LxCKCR_CKBLUE_MASK 0xff - -/* LTDC_LxPFCR - Pixel formats */ -#define LTDC_LxPFCR_ARGB8888 (0b000) -#define LTDC_LxPFCR_RGB888 (0b001) -#define LTDC_LxPFCR_RGB565 (0b010) -#define LTDC_LxPFCR_ARGB1555 (0b011) -#define LTDC_LxPFCR_ARGB4444 (0b100) -#define LTDC_LxPFCR_L8 (0b101) -#define LTDC_LxPFCR_AL44 (0b110) -#define LTDC_LxPFCR_AL88 (0b111) - -/* --- LTDC_LxCACR values -------------------------------------------------- */ - -/* Constant Alpha */ -#define LTDC_LxCACR_CONSTA_SHIFT 0 -#define LTDC_LxCACR_CONSTA_MASK 0xff - -/* --- LTDC_LxDCCR values -------------------------------------------------- */ - -/* Default Color Alpha */ -#define LTDC_LxDCCR_DCALPHA_SHIFT 24 -#define LTDC_LxDCCR_DCALPHA_MASK 1 - -/* Default Color Red */ -#define LTDC_LxDCCR_DCRED_SHIFT 16 -#define LTDC_LxDCCR_DCRED_MASK 1 - -/* Default Color Green */ -#define LTDC_LxDCCR_DCGREEN_SHIFT 8 -#define LTDC_LxDCCR_DCGREEN_MASK 1 - -/* Default Color Blue */ -#define LTDC_LxDCCR_DCBLUE_SHIFT 0 -#define LTDC_LxDCCR_DCBLUE_MASK 1 - -/* LTDC_LxBFCR - Blending factors - BF1 */ -#define LTDC_LxBFCR_BF1_CONST_ALPHA (0b100) -#define LTDC_LxBFCR_BF1_PIXEL_ALPHA_x_CONST_ALPHA (0b110) -/* LTDC_LxBFCR - Blending factors - BF2 */ -#define LTDC_LxBFCR_BF2_CONST_ALPHA (0b101) -#define LTDC_LxBFCR_BF2_PIXEL_ALPHA_x_CONST_ALPHA (0b111) - -/* --- LTDC_LxCFBAR values ------------------------------------------------- */ - -/* Color Frame Buffer Start Address */ -#define LTDC_LxCFBAR_CFBAR_SHIFT 0 -#define LTDC_LxCFBAR_CFBAR_MASK 0xffffffff - -/* --- LTDC_LxCFBLR values ------------------------------------------------- */ - -/* Color Frame Buffer Pitch */ -#define LTDC_LxCFBLR_CFBP_SHIFT 16 -#define LTDC_LxCFBLR_CFBP_MASK 0x1fff - -/* Color Frame Buffer Line Length */ -#define LTDC_LxCFBLR_CFBLL_SHIFT 0 -#define LTDC_LxCFBLR_CFBLL_MASK 0x1fff - -/* --- LTDC_LxCFBLNR values ------------------------------------------------ */ - -/* Frame Buffer Line Number */ -#define LTDC_LxCFBLNR_CFBLNBR_SHIFT 0 -#define LTDC_LxCFBLNR_CFBLNBR_MASK 0x3ff - -/* --- LTDC_LxCLUTWR values ------------------------------------------------ */ - -/* CLUT Address */ -#define LTDC_LxCLUTWR_CLUTADD_SHIFT 24 -#define LTDC_LxCLUTWR_CLUTADD_MASK 0xff - -/* Red */ -#define LTDC_LxCLUTWR_RED_SHIFT 16 -#define LTDC_LxCLUTWR_RED_MASK 0xff - -/* Green */ -#define LTDC_LxCLUTWR_GREEN_SHIFT 8 -#define LTDC_LxCLUTWR_GREEN_MASK 0xff - -/* Blue */ -#define LTDC_LxCLUTWR_BLUE_SHIFT 0 -#define LTDC_LxCLUTWR_BLUE_MASK 0xff - -/** - * simple helper macros - */ - -/* global */ -static inline void ltdc_ctrl_enable(uint32_t ctrl_flags) -{ - LTDC_GCR |= ctrl_flags; -} - -static inline void ltdc_ctrl_disable(uint32_t ctrl_flags) -{ - LTDC_GCR &= ~(ctrl_flags); -} - -static inline void ltdc_reload(uint32_t reload_flags) -{ - LTDC_SRCR = reload_flags; -} - -static inline void ltdc_set_background_color(uint8_t r, uint8_t g, uint8_t b) -{ - LTDC_BCCR = (((r)&255)<<16) | - (((g)&255)<<8) | - (((b)&255)<<0); -} - -static inline void ltdc_get_current_position(uint16_t *x, uint16_t *y) -{ - uint32_t tmp = LTDC_CPSR; - *x = tmp >> 16; - *y = tmp &= 0xFFFF; -} - -static inline uint16_t ltdc_get_current_position_x(void) -{ - return LTDC_CPSR >> 16; -} - -static inline uint16_t ltdc_get_current_position_y(void) -{ - return LTDC_CPSR & 0xffff; -} - -static inline uint32_t ltdc_get_display_status(uint32_t status_flags) -{ - return LTDC_CDSR & status_flags; -} - -/* layers */ -static inline void ltdc_layer_ctrl_enable(uint32_t layer, uint32_t ctrl_flags) -{ - LTDC_LxCR(layer) |= ctrl_flags; -} - -static inline void ltdc_layer_ctrl_disable(uint32_t layer, uint32_t ctrl_flags) -{ - LTDC_LxCR(layer) &= ~(ctrl_flags); -} - -static inline void ltdc_set_color_key(uint32_t layer, - uint8_t r, uint8_t g, uint8_t b) -{ - LTDC_LxCKCR(layer) = ((((r)&255)<<16) | - (((g)&255)<<8) | - (((b)&255)<<0)); -} - -static inline void ltdc_set_pixel_format(uint32_t layer, uint32_t format) -{ - LTDC_LxPFCR(layer) = format; -} - -static inline void ltdc_set_constant_alpha(uint32_t layer, uint8_t alpha) -{ - LTDC_LxCACR(layer) = ((alpha)&255); -} - -static inline void ltdc_set_default_colors(uint32_t layer, - uint8_t a, - uint8_t r, uint8_t g, uint8_t b) -{ - LTDC_LxDCCR(layer) = ((((a)&255)<<24) | - (((r)&255)<<16) | - (((g)&255)<<8) | - (((b)&255)<<0)); -} - -static inline void ltdc_set_blending_factors(uint32_t layer, - uint8_t bf1, uint8_t bf2) -{ - LTDC_LxBFCR(layer) = ((bf1)<<8) | ((bf2)<<0); -} - -static inline void ltdc_set_fbuffer_address(uint32_t layer, uint32_t address) -{ - LTDC_LxCFBAR(layer) = (uint32_t)address; -} - -static inline void ltdc_set_fb_line_length(uint32_t layer, - uint16_t len, uint16_t pitch) -{ - LTDC_LxCFBLR(layer) = ((((pitch)&0x1FFF)<<16) | (((len)&0x1FFF)<<0)); -} - -static inline void ltdc_set_fb_line_count(uint32_t layer, uint16_t linecount) -{ - LTDC_LxCFBLNR(layer) = (((linecount)&0x3FF)<<0); -} - -/** - * more complicated helper functions - */ -void ltdc_set_tft_sync_timings( - uint16_t sync_width, uint16_t sync_height, - uint16_t h_back_porch, uint16_t v_back_porch, - uint16_t active_width, uint16_t active_height, - uint16_t h_front_porch, uint16_t v_front_porch -); -void ltdc_setup_windowing( - uint8_t layer_number, - uint16_t h_back_porch, uint16_t v_back_porch, - uint16_t active_width, uint16_t active_height -); - - - -/** - * Helper function to wait for SRCR reload to complete or so - */ - -static inline bool LTDC_SRCR_IS_RELOADING(void) -{ - return (LTDC_SRCR & (LTDC_SRCR_RELOAD_VBR | - LTDC_SRCR_RELOAD_IMR)) != 0; -} - -/** - * color conversion helper function - * (simulate the ltdc color conversion) - */ - -static inline uint16_t ltdc_get_rgb888_from_rgb565(uint16_t rgb888) -{ - return ((((rgb888) & 0xF800) >> (11-8))/31)<<16 - | ((((rgb888) & 0x07E0) << (8-5))/63)<<8 - | ((((rgb888) & 0x001F) << (8-0))/31)<<0; -} - +#include <libopencm3/stm32/common/ltdc_common_f47.h> #endif /* LIBOPENCM3_STM32_F4_LTDC_H_ */ + +/**@}*/ diff --git a/include/libopencm3/stm32/f4/memorymap.h b/include/libopencm3/stm32/f4/memorymap.h index fc2c59df..759e477f 100644 --- a/include/libopencm3/stm32/f4/memorymap.h +++ b/include/libopencm3/stm32/f4/memorymap.h @@ -44,7 +44,7 @@ #define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) #define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) #define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) -/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x2400) #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index 60366b69..698780f0 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -185,6 +185,10 @@ #define RCC_CFGR_MCOPRE_DIV_4 0x6 #define RCC_CFGR_MCOPRE_DIV_5 0x7 +/* PLLSRC: PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI_CLK 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 + /* I2SSRC: I2S clock selection */ #define RCC_CFGR_I2SSRC (1 << 23) @@ -278,12 +282,10 @@ #define RCC_CIR_LSIRDYF (1 << 0) /*@}*/ -/** @defgroup rcc_AxBY_reset_values AHB/APB reset bits - * @ingroup rcc_registers - * @brief Reset bits for the AHB/APB peripherals +/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) +@{*/ +/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values @{*/ -/* --- RCC_AHB1RSTR values ------------------------------------------------- */ - #define RCC_AHB1RSTR_OTGHSRST (1 << 29) #define RCC_AHB1RSTR_ETHMACRST (1 << 25) #define RCC_AHB1RSTR_DMA2DRST (1 << 23) @@ -301,6 +303,7 @@ #define RCC_AHB1RSTR_GPIOCRST (1 << 2) #define RCC_AHB1RSTR_GPIOBRST (1 << 1) #define RCC_AHB1RSTR_GPIOARST (1 << 0) +/**@}*/ /** @addtogroup deprecated_201802_rcc Deprecated 2018 * @deprecated replace zzz_IOPxRST with zzz_GPIOxRST @@ -319,21 +322,24 @@ #define RCC_AHB1RSTR_IOPARST RCC_AHB1RSTR_GPIOARST /**@}*/ -/* --- RCC_AHB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values +@{*/ #define RCC_AHB2RSTR_OTGFSRST (1 << 7) #define RCC_AHB2RSTR_RNGRST (1 << 6) #define RCC_AHB2RSTR_HASHRST (1 << 5) #define RCC_AHB2RSTR_CRYPRST (1 << 4) #define RCC_AHB2RSTR_DCMIRST (1 << 0) +/**@}*/ -/* --- RCC_AHB3RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values +@{*/ #define RCC_AHB3RSTR_QSPIRST (1 << 1) #define RCC_AHB3RSTR_FSMCRST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_UART8RST (1 << 31) #define RCC_APB1RSTR_UART7RST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) @@ -359,9 +365,10 @@ #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_DSIRST (1 << 27) #define RCC_APB2RSTR_LTDCRST (1 << 26) #define RCC_APB2RSTR_SAI1RST (1 << 22) @@ -379,14 +386,12 @@ #define RCC_APB2RSTR_USART1RST (1 << 4) #define RCC_APB2RSTR_TIM8RST (1 << 1) #define RCC_APB2RSTR_TIM1RST (1 << 0) -/*@}*/ +/**@}*/ -/** @defgroup rcc_AxBY_reset_values AHB/APB enable bits - * @ingroup rcc_registers - * @brief Enable bits for the AHB/APB peripherals +/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) +@{*/ +/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values @{*/ -/* --- RCC_AHB1ENR values ------------------------------------------------- */ - #define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) #define RCC_AHB1ENR_OTGHSEN (1 << 29) #define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) @@ -428,23 +433,26 @@ #define RCC_AHB1ENR_IOPAEN RCC_AHB1ENR_GPIOAEN /**@}*/ -/* --- RCC_AHB2ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values +@{*/ #define RCC_AHB2ENR_OTGFSEN (1 << 7) #define RCC_AHB2ENR_RNGEN (1 << 6) #define RCC_AHB2ENR_HASHEN (1 << 5) #define RCC_AHB2ENR_CRYPEN (1 << 4) #define RCC_AHB2ENR_DCMIEN (1 << 0) +/**@}*/ -/* --- RCC_AHB3ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values +@{*/ #define RCC_AHB3ENR_QSPIEN (1 << 1) #define RCC_AHB3ENR_FSMCEN (1 << 0) /* Alternate now that F429 has DRAM controller as well */ #define RCC_AHB3ENR_FMCEN (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1ENR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@{*/ #define RCC_APB1ENR_UART8EN (1 << 31) #define RCC_APB1ENR_UART7EN (1 << 30) #define RCC_APB1ENR_DACEN (1 << 29) @@ -470,9 +478,10 @@ #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ -/* --- RCC_APB2ENR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@{*/ #define RCC_APB2ENR_DSIEN (1 << 27) #define RCC_APB2ENR_LTDCEN (1 << 26) #define RCC_APB2ENR_SAI1EN (1 << 22) @@ -492,6 +501,7 @@ #define RCC_APB2ENR_USART1EN (1 << 4) #define RCC_APB2ENR_TIM8EN (1 << 1) #define RCC_APB2ENR_TIM1EN (1 << 0) +/**@}*/ /* --- RCC_AHB1LPENR values ------------------------------------------------- */ @@ -766,10 +776,9 @@ extern uint32_t rcc_apb2_frequency; /* --- Function prototypes ------------------------------------------------- */ enum rcc_clock_3v3 { - RCC_CLOCK_3V3_48MHZ, RCC_CLOCK_3V3_84MHZ, - RCC_CLOCK_3V3_120MHZ, RCC_CLOCK_3V3_168MHZ, + RCC_CLOCK_3V3_180MHZ, RCC_CLOCK_3V3_END }; @@ -779,6 +788,7 @@ struct rcc_clock_scale { uint8_t pllp; uint8_t pllq; uint8_t pllr; + uint8_t pll_source; uint32_t flash_config; uint8_t hpre; uint8_t ppre1; @@ -789,6 +799,7 @@ struct rcc_clock_scale { uint32_t apb2_frequency; }; +extern const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END]; extern const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END]; @@ -1094,7 +1105,8 @@ void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr); uint32_t rcc_system_clock_source(void); -void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); +void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); +void __attribute__((deprecated("Use rcc_clock_setup_pll as direct replacement"))) rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock); END_DECLS diff --git a/include/libopencm3/stm32/f7/adc.h b/include/libopencm3/stm32/f7/adc.h new file mode 100644 index 00000000..d97a1883 --- /dev/null +++ b/include/libopencm3/stm32/f7/adc.h @@ -0,0 +1,194 @@ +/** @defgroup adc_defines ADC Defines + +@brief <b>Defined Constants and Types for the STM32F7xx Analog to Digital +Converters</b> + +@ingroup STM32F7xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2019 +Matthew Lai <m@matthewlai.ca> +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman <evbuilder@users.sourceforge.net> + +@date 31 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Matthew Lai <m@matthewlai.ca> + * Copyright (C) 2009 Edward Cheeseman <evbuilder@users.sourceforge.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include <libopencm3/stm32/common/adc_common_v1_multi.h> + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32((block) + 0x14) +#define ADC_JOFR2(block) MMIO32((block) + 0x18) +#define ADC_JOFR3(block) MMIO32((block) + 0x1c) +#define ADC_JOFR4(block) MMIO32((block) + 0x20) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32((block) + 0x24) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32((block) + 0x28) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32((block) + 0x2c) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32((block) + 0x30) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32((block) + 0x34) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32((block) + 0x38) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32((block) + 0x3c) +#define ADC_JDR2(block) MMIO32((block) + 0x40) +#define ADC_JDR3(block) MMIO32((block) + 0x44) +#define ADC_JDR4(block) MMIO32((block) + 0x48) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32((block) + 0x4c) + +/** @defgroup adc_channel ADC Channel Numbers + * @ingroup adc_defines + *@{*/ +#define ADC_CHANNEL_TEMP 18 +#define ADC_CHANNEL_VREF 17 +#define ADC_CHANNEL_VBAT 18 +/**@}*/ + + +/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ +#define ADC_CR1_AWDCH_MAX 18 + +/* --- Convenience macros -------------------------------------------------- */ +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group +@ingroup adc_defines + +@{*/ +/** Timer 1 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) +/** Timer 1 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) +/** Timer 2 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) +/** Timer 5 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM5_TRGO (0x4 << 24) +/** Timer 4 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 24) +/** Timer 3 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM3_CC4 (0x6 << 24) +/** Timer 8 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM8_TRGO (0x7 << 24) +/** Timer 8 TRGO2 Event */ +#define ADC_CR2_EXTSEL_TIM8_TRGO2 (0x8 << 24) +/** Timer 1 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM1_TRGO (0x9 << 24) +/** Timer 1 TRGO2 Event */ +#define ADC_CR2_EXTSEL_TIM1_TRGO2 (0xA << 24) +/** Timer 2 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM2_TRGO (0xB << 24) +/** Timer 4 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM4_TRGO (0xC << 24) +/** Timer 6 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM6_TRGO (0xD << 24) +/** EXTI Line 11 Event */ +#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) +/**@}*/ + +/* JEXTSEL[3:0]: External event selection for injected group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group +@ingroup adc_defines + +@{*/ +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 16) +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 16) +#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 16) +#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 16) +#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 16) +/* 0x6 undefined */ +#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x7 << 16) +#define ADC_CR2_JEXTSEL_TIM1_TRGO2 (0x8 << 16) +#define ADC_CR2_JEXTSEL_TIM8_TRGO (0x9 << 16) +#define ADC_CR2_JEXTSEL_TIM8_TRGO2 (0xA << 16) +#define ADC_CR2_JEXTSEL_TIM3_cc3 (0xB << 16) +#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xC << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC1 (0xD << 16) +#define ADC_CR2_JEXTSEL_TIM6_TRGO (0xE << 16) +/* 0xf undefined */ +/**@}*/ + +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels +@ingroup adc_defines + +@{*/ +#define ADC_SMPR_SMP_3CYC 0x0 +#define ADC_SMPR_SMP_15CYC 0x1 +#define ADC_SMPR_SMP_28CYC 0x2 +#define ADC_SMPR_SMP_56CYC 0x3 +#define ADC_SMPR_SMP_84CYC 0x4 +#define ADC_SMPR_SMP_112CYC 0x5 +#define ADC_SMPR_SMP_144CYC 0x6 +#define ADC_SMPR_SMP_480CYC 0x7 +/**@}*/ + +/* --- ADC_SQR1 values ----------------------------------------------------- */ +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) + +#define ADC_SQR_MAX_CHANNELS_REGULAR 16 + +/* ADCPRE: ADC prescaler. */ +/****************************************************************************/ +/** @defgroup adc_ccr_adcpre ADC Prescale +@ingroup adc_defines + +@{*/ +#define ADC_CCR_ADCPRE_BY2 (0x0 << 16) +#define ADC_CCR_ADCPRE_BY4 (0x1 << 16) +#define ADC_CCR_ADCPRE_BY6 (0x2 << 16) +#define ADC_CCR_ADCPRE_BY8 (0x3 << 16) +/**@}*/ +#define ADC_CCR_ADCPRE_MASK (0x3 << 16) +#define ADC_CCR_ADCPRE_SHIFT 16 + +BEGIN_DECLS + +void adc_set_multi_mode(uint32_t mode); +void adc_enable_vbat_sensor(void); +void adc_disable_vbat_sensor(void); + +END_DECLS + +#endif diff --git a/lib/stm32/f0/timer.c b/include/libopencm3/stm32/f7/crc.h index 88006834..ae6d4677 100644 --- a/lib/stm32/f0/timer.c +++ b/include/libopencm3/stm32/f7/crc.h @@ -1,21 +1,19 @@ -/** @defgroup timer_file Timers +/** @defgroup crc_defines CRC Defines * - * @ingroup STM32F0xx + * @brief <b>libopencm3 Defined Constants and Types for the STM32F7xx CRC + * Generator </b> * - * @brief <b>libopencm3 STM32F0xx Timers</b> + * @ingroup STM32F7xx_defines * * @version 1.0.0 * - * @date 11 July 2013 + * @date 11 Apr 2019 * + *LGPL License Terms @ref lgpl_license */ - /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org> - * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -30,5 +28,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/timer.h> +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include <libopencm3/stm32/common/crc_v2.h> +#endif diff --git a/lib/stm32/f1/dma.c b/include/libopencm3/stm32/f7/dac.h index 70193659..1e5607e4 100644 --- a/lib/stm32/f1/dma.c +++ b/include/libopencm3/stm32/f7/dac.h @@ -1,15 +1,15 @@ -/** @defgroup dma_file DMA +/** @defgroup dac_defines DAC Defines -@ingroup STM32F1xx +@brief <b>Defined Constants and Types for the STM32F7xx DAC</b> -@brief <b>libopencm3 STM32F1xx DMA</b> +@ingroup STM32F7xx_defines @version 1.0.0 -@date 18 August 2012 +@date 6 May 2019 LGPL License Terms @ref lgpl_license -*/ + */ /* * This file is part of the libopencm3 project. @@ -28,4 +28,9 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/dma.h> +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include <libopencm3/stm32/common/dac_common_all.h> + +#endif diff --git a/lib/stm32/f1/dac.c b/include/libopencm3/stm32/f7/dma.h index fa599bb7..01a7e18d 100644 --- a/lib/stm32/f1/dac.c +++ b/include/libopencm3/stm32/f7/dma.h @@ -1,15 +1,13 @@ -/** @defgroup dac_file DAC +/** @defgroup dma_defines DMA Defines -@ingroup STM32F1xx +@ingroup STM32F7xx_defines -@brief <b>libopencm3 STM32F1xx DAC</b> +@brief Defined Constants and Types for the STM32F7xx DMA Controller @version 1.0.0 -@date 18 August 2012 - LGPL License Terms @ref lgpl_license -*/ + */ /* * This file is part of the libopencm3 project. @@ -28,4 +26,9 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/dac.h> +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include <libopencm3/stm32/common/dma_common_f24.h> + +#endif
\ No newline at end of file diff --git a/include/libopencm3/stm32/f7/dma2d.h b/include/libopencm3/stm32/f7/dma2d.h new file mode 100644 index 00000000..47b26478 --- /dev/null +++ b/include/libopencm3/stm32/f7/dma2d.h @@ -0,0 +1,30 @@ +/** @defgroup dma2d_defines DMA2D Defines + * @brief <b>Defined Constants and Types for the STM32F7xx DMA2D Peripheral</b> + * @ingroup STM32F7xx_defines + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_STM32_F7_DMA2D_H_ +#define LIBOPENCM3_STM32_F7_DMA2D_H_ + +#include <libopencm3/stm32/common/dma2d_common_f47.h> + +#endif /* LIBOPENCM3_STM32_F7_DMA2D_H_ */ + +/**@}*/ diff --git a/include/libopencm3/stm32/f7/doc-stm32f7.h b/include/libopencm3/stm32/f7/doc-stm32f7.h index ba6318d3..cd024982 100644 --- a/include/libopencm3/stm32/f7/doc-stm32f7.h +++ b/include/libopencm3/stm32/f7/doc-stm32f7.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32F7 +/** @page libopencm3 STM32F7 @version 1.0.0 diff --git a/include/libopencm3/stm32/f7/dsi.h b/include/libopencm3/stm32/f7/dsi.h new file mode 100644 index 00000000..45f727ee --- /dev/null +++ b/include/libopencm3/stm32/f7/dsi.h @@ -0,0 +1,31 @@ +/** @defgroup dsi_defines DSI Defines + * @brief <b>Defines Constants and Macros for the STM32F7xx Display Serial + * Interface Host and Wrapper</b> + * @ingroup STM32F7xx_defines + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_STM32_F7_DSI_H_ +#define LIBOPENCM3_STM32_F7_DSI_H_ + +#include <libopencm3/stm32/common/dsi_common_f47.h> + +#endif + +/**@}*/ diff --git a/include/libopencm3/stm32/f7/exti.h b/include/libopencm3/stm32/f7/exti.h new file mode 100644 index 00000000..edb26485 --- /dev/null +++ b/include/libopencm3/stm32/f7/exti.h @@ -0,0 +1,33 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief <b>Defined Constants and Types for the STM32F7xx External Interrupts + * </b> + * + * @ingroup STM32F7xx_defines + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> + +#endif diff --git a/include/libopencm3/stm32/f7/flash.h b/include/libopencm3/stm32/f7/flash.h index d9af802c..f5e68d7a 100644 --- a/include/libopencm3/stm32/f7/flash.h +++ b/include/libopencm3/stm32/f7/flash.h @@ -1,7 +1,6 @@ -#ifndef LIBOPENCM3_FLASH_H -#define LIBOPENCM3_FLASH_H - -/** @addtogroup flash_defines +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32F7xx_defines * * @author @htmlonly © @endhtmlonly 2017 * Matthew Lai <m@matthewlai.ca> @@ -32,6 +31,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + #include <libopencm3/stm32/common/flash_common_all.h> #include <libopencm3/stm32/common/flash_common_f.h> #include <libopencm3/stm32/common/flash_common_f24.h> diff --git a/include/libopencm3/stm32/f7/fmc.h b/include/libopencm3/stm32/f7/fmc.h new file mode 100644 index 00000000..8eef83ae --- /dev/null +++ b/include/libopencm3/stm32/f7/fmc.h @@ -0,0 +1,38 @@ +/** @defgroup fmc_defines FMC Defines + * @brief <b>Defined Constants and Types for the STM32F7xx Flexible Memory + * Controller</b> + * @ingroup STM32F7xx_defines + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_F7_FMC_H +#define LIBOPENCM3_F7_FMC_H + +#ifndef LIBOPENCM3_FSMC_H +#error "This file should not be included directly, it is included with fsmc.h" +#endif + +#include <libopencm3/stm32/common/fmc_common_f47.h> + +/* --- Convenience macros -------------------------------------------------- */ +#define FSMC_BASE FMCC_BASE + +#endif + +/**@}*/ diff --git a/lib/stm32/f0/gpio.c b/include/libopencm3/stm32/f7/i2c.h index f60b4289..23b7d6bf 100644 --- a/lib/stm32/f0/gpio.c +++ b/include/libopencm3/stm32/f7/i2c.h @@ -1,16 +1,15 @@ -/** @defgroup gpio_file GPIO +/** @defgroup i2c_defines I2C Defines * - * @ingroup STM32F0xx + * @brief <b>Defined Constants and Types for the STM32F7xx I2C</b> * - * @brief <b>libopencm3 STM32F0xx General Purpose I/O</b> + * @ingroup STM32F7xx_defines * * @version 1.0.0 * - * @date 18 August 2012 + * @date 04 April 2019 * * LGPL License Terms @ref lgpl_license */ - /* * This file is part of the libopencm3 project. * @@ -28,4 +27,10 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/gpio.h> +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include <libopencm3/stm32/common/i2c_common_v2.h> + +#endif + diff --git a/include/libopencm3/stm32/f7/irq.json b/include/libopencm3/stm32/f7/irq.json index 79e1ee62..31bbe61c 100644 --- a/include/libopencm3/stm32/f7/irq.json +++ b/include/libopencm3/stm32/f7/irq.json @@ -93,9 +93,17 @@ "dma2d", "sai2", "quadspi", + "lp_timer1", + "hdmi_cec", "i2c4_ev", "i2c4_er", - "spdifrx" + "spdifrx", + "dsihost", + "dfsdm1_flt0", + "dfsdm1_flt1", + "dfsdm1_flt2", + "dfsdm1_flt3", + "sdmmc2" ], "partname_humanreadable": "STM32 F7 series", "partname_doxygen": "STM32F7", diff --git a/include/libopencm3/stm32/f7/iwdg.h b/include/libopencm3/stm32/f7/iwdg.h new file mode 100644 index 00000000..c70f20df --- /dev/null +++ b/include/libopencm3/stm32/f7/iwdg.h @@ -0,0 +1,36 @@ +/** @defgroup iwdg_defines IWDG Defines + * + * @brief <b>Defined Constants and Types for the STM32F7xx Independent Watchdog + * Timer</b> + * + * @ingroup STM32F7xx_defines + * + * @version 1.0.0 + * + * @date 11 April 2018 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include <libopencm3/stm32/common/iwdg_common_v2.h> + +#endif diff --git a/lib/stm32/f3/rtc.c b/include/libopencm3/stm32/f7/lptimer.h index f332765a..4c721af6 100644 --- a/lib/stm32/f3/rtc.c +++ b/include/libopencm3/stm32/f7/lptimer.h @@ -1,23 +1,17 @@ -/** @defgroup rtc_file RTC +/** @defgroup lptimer_defines LPTIM Defines * - * @ingroup STM32F3xx - * - * @brief <b>libopencm3 STM32F3xx Real Time Clock</b> + * @ingroup STM32F7xx_defines + * + * @brief <b>libopencm3 Defined Constants and Types for the STM32F7xx Low Power Timer</b> * * @version 1.0.0 * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies <ksarkies@internode.on.net> - * - * @date 13 January 2014 - * * LGPL License Terms @ref lgpl_license - */ - + * */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net> + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -33,6 +27,20 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/rtc.h> +#ifndef LIBOPENCM3_LPTIMER_H +#define LIBOPENCM3_LPTIMER_H +/**@{*/ + +#include <libopencm3/stm32/common/lptimer_common_all.h> + +/** @defgroup lptim_reg_base Low Power Timer register base addresses +@{*/ +#define LPTIM1 LPTIM1_BASE +/**@}*/ + +BEGIN_DECLS +END_DECLS +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/f7/ltdc.h b/include/libopencm3/stm32/f7/ltdc.h new file mode 100644 index 00000000..37bde226 --- /dev/null +++ b/include/libopencm3/stm32/f7/ltdc.h @@ -0,0 +1,31 @@ +/** @defgroup ltdc_defines LTDC Defines + * @brief <b>Defined Constants and Types for the STM32F7xx LCD TFT Display + * Controller</b> + * @ingroup STM32F7xx_defines + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ + +#ifndef LIBOPENCM3_STM32_F7_LTDC_H_ +#define LIBOPENCM3_STM32_F7_LTDC_H_ + +#include <libopencm3/stm32/common/ltdc_common_f47.h> + +#endif /* LIBOPENCM3_STM32_F7_LTDC_H_ */ + +/**@}*/ diff --git a/include/libopencm3/stm32/f7/memorymap.h b/include/libopencm3/stm32/f7/memorymap.h index 1492974e..0ce998c0 100644 --- a/include/libopencm3/stm32/f7/memorymap.h +++ b/include/libopencm3/stm32/f7/memorymap.h @@ -94,7 +94,11 @@ #define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800) #define SAI2_BASE (PERIPH_BASE_APB2 + 0x5C00) #define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800) -/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 6C00 - 0x4001 FFFF): Reserved */ +#define LTDC_BASE (PERIPH_BASE_APB2 + 0x6800) /* compat. with f4 */ +#define DSI_BASE (PERIPH_BASE_APB2 + 0x6C00) +#define DFSDM1_BASE (PERIPH_BASE_APB2 + 0x7400) +#define MDIOS_BASE (PERIPH_BASE_APB2 + 0x7800) +/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 7C00 - 0x4001 FFFF): Reserved */ /* AHB1 */ #define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) diff --git a/include/libopencm3/stm32/f7/pwr.h b/include/libopencm3/stm32/f7/pwr.h index 87477b44..46055710 100644 --- a/include/libopencm3/stm32/f7/pwr.h +++ b/include/libopencm3/stm32/f7/pwr.h @@ -292,4 +292,6 @@ void pwr_disable_overdrive(void); END_DECLS +/**@}*/ + #endif diff --git a/include/libopencm3/stm32/f7/rcc.h b/include/libopencm3/stm32/f7/rcc.h index 2bb3e76f..20ed3a5d 100644 --- a/include/libopencm3/stm32/f7/rcc.h +++ b/include/libopencm3/stm32/f7/rcc.h @@ -38,6 +38,8 @@ #include <libopencm3/stm32/f7/pwr.h> +/**@{*/ + /* --- RCC registers ------------------------------------------------------- */ #define RCC_CR MMIO32(RCC_BASE + 0x00) @@ -208,8 +210,10 @@ #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) -/* --- RCC_AHB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) +@{*/ +/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values +@{*/ #define RCC_AHB1RSTR_OTGHSRST (1 << 29) #define RCC_AHB1RSTR_ETHMACRST (1 << 25) #define RCC_AHB1RSTR_DMA2DRST (1 << 23) @@ -227,22 +231,26 @@ #define RCC_AHB1RSTR_GPIOCRST (1 << 2) #define RCC_AHB1RSTR_GPIOBRST (1 << 1) #define RCC_AHB1RSTR_GPIOARST (1 << 0) +/**@}*/ -/* --- RCC_AHB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values +@{*/ #define RCC_AHB2RSTR_OTGFSRST (1 << 7) #define RCC_AHB2RSTR_RNGRST (1 << 6) #define RCC_AHB2RSTR_HASHRST (1 << 5) #define RCC_AHB2RSTR_CRYPRST (1 << 4) #define RCC_AHB2RSTR_DCMIRST (1 << 0) +/**@}*/ -/* --- RCC_AHB3RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values +@{*/ #define RCC_AHB3RSTR_QSPIRST (1 << 1) #define RCC_AHB3RSTR_FSMCRST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_UART8RST (1 << 31) #define RCC_APB1RSTR_UART7RST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) @@ -272,9 +280,10 @@ #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_LTDCRST (1 << 26) #define RCC_APB2RSTR_SAI2RST (1 << 23) #define RCC_APB2RSTR_SAI1RST (1 << 22) @@ -292,9 +301,12 @@ #define RCC_APB2RSTR_USART1RST (1 << 4) #define RCC_APB2RSTR_TIM8RST (1 << 1) #define RCC_APB2RSTR_TIM1RST (1 << 0) +/**@}*/ -/* --- RCC_AHB1ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) +@{*/ +/** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values +@{*/ #define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) #define RCC_AHB1ENR_OTGHSEN (1 << 29) #define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) @@ -318,22 +330,26 @@ #define RCC_AHB1ENR_GPIOCEN (1 << 2) #define RCC_AHB1ENR_GPIOBEN (1 << 1) #define RCC_AHB1ENR_GPIOAEN (1 << 0) +/**@}*/ -/* --- RCC_AHB2ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2enr_en RCC_AHB2ENR enable values +@{*/ #define RCC_AHB2ENR_OTGFSEN (1 << 7) #define RCC_AHB2ENR_RNGEN (1 << 6) #define RCC_AHB2ENR_HASHEN (1 << 5) #define RCC_AHB2ENR_CRYPEN (1 << 4) #define RCC_AHB2ENR_DCMIEN (1 << 0) +/**@}*/ -/* --- RCC_AHB3ENR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb3enr_en RCC_AHB3ENR enable values +@{*/ #define RCC_AHB3ENR_QSPIEN (1 << 1) #define RCC_AHB3ENR_FMCEN (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1ENR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@{*/ #define RCC_APB1ENR_UART8EN (1 << 31) #define RCC_APB1ENR_UART7EN (1 << 30) #define RCC_APB1ENR_DACEN (1 << 29) @@ -363,9 +379,10 @@ #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ -/* --- RCC_APB2ENR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@{*/ #define RCC_APB2ENR_LTDCEN (1 << 26) #define RCC_APB2ENR_SAI2EN (1 << 23) #define RCC_APB2ENR_SAI1EN (1 << 22) @@ -385,6 +402,7 @@ #define RCC_APB2ENR_USART1EN (1 << 4) #define RCC_APB2ENR_TIM8EN (1 << 1) #define RCC_APB2ENR_TIM1EN (1 << 0) +/**@}*/ /* --- RCC_AHB1LPENR values ------------------------------------------------- */ @@ -708,8 +726,8 @@ enum rcc_periph_clken { RCC_CEC = _REG_BIT(0x40, 27), RCC_PWR = _REG_BIT(0x40, 28), RCC_DAC = _REG_BIT(0x40, 29), - RCC_USART7 = _REG_BIT(0x40, 30), - RCC_USART8 = _REG_BIT(0x40, 31), + RCC_UART7 = _REG_BIT(0x40, 30), + RCC_UART8 = _REG_BIT(0x40, 31), /* APB2 peripherals */ RCC_TIM1 = _REG_BIT(0x44, 0), @@ -942,4 +960,6 @@ void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz); void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock); END_DECLS +/**@}*/ + #endif diff --git a/include/libopencm3/stm32/f7/spi.h b/include/libopencm3/stm32/f7/spi.h index e99405a1..59528764 100644 --- a/include/libopencm3/stm32/f7/spi.h +++ b/include/libopencm3/stm32/f7/spi.h @@ -31,7 +31,7 @@ LGPL License Terms @ref lgpl_license #ifndef LIBOPENCM3_SPI_H #define LIBOPENCM3_SPI_H -#include <libopencm3/stm32/common/spi_common_v1_frf.h> +#include <libopencm3/stm32/common/spi_common_v2.h> #endif diff --git a/include/libopencm3/stm32/f7/syscfg.h b/include/libopencm3/stm32/f7/syscfg.h new file mode 100644 index 00000000..48735ac9 --- /dev/null +++ b/include/libopencm3/stm32/f7/syscfg.h @@ -0,0 +1,36 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32F7xx_defines + * + * @brief Defined Constants and Types for the STM32F7xx Sysconfig + * + * @version 1.0.0 + * + * @date 11 April 2019 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include <libopencm3/stm32/common/syscfg_common_l1f234.h> + +#endif diff --git a/include/libopencm3/stm32/f7/usart.h b/include/libopencm3/stm32/f7/usart.h index 9f7fed51..df496a0b 100644 --- a/include/libopencm3/stm32/f7/usart.h +++ b/include/libopencm3/stm32/f7/usart.h @@ -34,9 +34,9 @@ #include <libopencm3/stm32/common/usart_common_all.h> #include <libopencm3/stm32/common/usart_common_v2.h> +/**@{*/ /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ @@ -54,5 +54,7 @@ BEGIN_DECLS END_DECLS +/**@}*/ + #endif diff --git a/include/libopencm3/stm32/flash.h b/include/libopencm3/stm32/flash.h index c95ca361..b8057bef 100644 --- a/include/libopencm3/stm32/flash.h +++ b/include/libopencm3/stm32/flash.h @@ -38,6 +38,10 @@ # include <libopencm3/stm32/l1/flash.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/flash.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/flash.h> +#elif defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/flash.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h index 2d8ed6a7..73a666fb 100644 --- a/include/libopencm3/stm32/fsmc.h +++ b/include/libopencm3/stm32/fsmc.h @@ -23,16 +23,17 @@ #include <libopencm3/cm3/common.h> #include <libopencm3/stm32/memorymap.h> -#if defined(STM32F4) +#if defined(STM32F4) # include <libopencm3/stm32/f4/fmc.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/fmc.h> #endif /* --- Convenience macros -------------------------------------------------- */ - #define FSMC_BANK1_BASE 0x60000000U /* NOR / PSRAM */ -#define FSMC_BANK2_BASE 0x70000000U /* NAND flash */ +#define FSMC_BANK2_BASE 0x70000000U /* NAND flash (reserved in F7) */ #define FSMC_BANK3_BASE 0x80000000U /* NAND flash */ -#define FSMC_BANK4_BASE 0x90000000U /* PC card */ +#define FSMC_BANK4_BASE 0x90000000U /* PC card (reserved in F7) */ /* --- FSMC registers ------------------------------------------------------ */ diff --git a/lib/stm32/f0/dma.c b/include/libopencm3/stm32/g0/crc.h index 8f158a81..43d689d9 100644 --- a/lib/stm32/f0/dma.c +++ b/include/libopencm3/stm32/g0/crc.h @@ -1,16 +1,11 @@ -/** @defgroup dma_file DMA +/** @defgroup crc_defines CRC Defines * - * @ingroup STM32F0xx + * @brief <b>Defined Constants and Types for the STM32G0xx CRC Generator </b> * - * @brief <b>libopencm3 STM32F0xx DMA</b> - * - * @version 1.0.0 - * - * @date 10 July 2013 + * @ingroup STM32G0xx_defines * * LGPL License Terms @ref lgpl_license */ - /* * This file is part of the libopencm3 project. * @@ -28,4 +23,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/dma.h> +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include <libopencm3/stm32/common/crc_v2.h> + +#endif diff --git a/include/libopencm3/stm32/g0/doc-stm32g0.h b/include/libopencm3/stm32/g0/doc-stm32g0.h new file mode 100644 index 00000000..66243cac --- /dev/null +++ b/include/libopencm3/stm32/g0/doc-stm32g0.h @@ -0,0 +1,36 @@ +/** @page libopencm3 STM32G0 + +@version 1.0.0 + +@date 30 January 2019 + +API documentation for ST Microelectronics STM32G0 Cortex M0+ series + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + +/** @defgroup STM32G0xx STM32G0xx +Libraries for ST Microelectronics STM32G0xx series. + +@version 1.0.0 + +@date 30 January 2019 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32G0xx_defines STM32G0xx Defines + +@brief Defined Constants and Types for the STM32G0xx series + +@version 1.0.0 + +@date 30 January 2019 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/stm32/g0/exti.h b/include/libopencm3/stm32/g0/exti.h new file mode 100644 index 00000000..88a1c01b --- /dev/null +++ b/include/libopencm3/stm32/g0/exti.h @@ -0,0 +1,85 @@ +/** @defgroup exti_defines EXTI Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx EXTI Control</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include <libopencm3/stm32/common/exti_common_all.h> + +/* --- EXTI registers ------------------------------------------------------ */ +#define EXTI_RTSR1 MMIO32(EXTI_BASE + 0x00) +#define EXTI_RTSR EXTI_RTSR1 + +#define EXTI_FTSR1 MMIO32(EXTI_BASE + 0x04) +#define EXTI_FTSR EXTI_FTSR1 + +#define EXTI_SWIER1 MMIO32(EXTI_BASE + 0x08) +#define EXTI_RPR1 MMIO32(EXTI_BASE + 0x0c) +#define EXTI_FPR1 MMIO32(EXTI_BASE + 0x10) + +#define EXTI_EXTICR(i) MMIO32(EXTI_BASE + 0x60 + (i)*4) +#define EXTI_EXTICR1 MMIO32(EXTI_BASE + 0x60) +#define EXTI_EXTICR2 MMIO32(EXTI_BASE + 0x64) +#define EXTI_EXTICR3 MMIO32(EXTI_BASE + 0x68) +#define EXTI_EXTICR4 MMIO32(EXTI_BASE + 0x6c) + +#define EXTI_IMR1 MMIO32(EXTI_BASE + 0x80) +#define EXTI_IMR EXTI_IMR1 + +#define EXTI_EMR1 MMIO32(EXTI_BASE + 0x84) +#define EXTI_EMR EXTI_EMR1 + +#define EXTI_IMR2 MMIO32(EXTI_BASE + 0x90) +#define EXTI_EMR2 MMIO32(EXTI_BASE + 0x94) + +/* --- EXTI_EXTICR Values -------------------------------------------------*/ + +#define EXTI_EXTICR_FIELDSIZE 8 +#define EXTI_EXTICR_GPIOA 0 +#define EXTI_EXTICR_GPIOB 1 +#define EXTI_EXTICR_GPIOC 2 +#define EXTI_EXTICR_GPIOD 3 +#define EXTI_EXTICR_GPIOF 5 + +BEGIN_DECLS + +uint32_t exti_get_rising_flag_status(uint32_t exti); +uint32_t exti_get_falling_flag_status(uint32_t exti); + +void exti_reset_rising_request(uint32_t extis); +void exti_reset_falling_request(uint32_t extis); + +END_DECLS + +#else +/** @cond */ +#warning "exti_common_v1.h should not be included directly, only via exti.h" +#endif +/** @endcond */ + +/**@}*/ diff --git a/include/libopencm3/stm32/g0/flash.h b/include/libopencm3/stm32/g0/flash.h new file mode 100644 index 00000000..63fded55 --- /dev/null +++ b/include/libopencm3/stm32/g0/flash.h @@ -0,0 +1,201 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx Flash Control</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include <libopencm3/stm32/common/flash_common_all.h> + +/** @defgroup flash_registers FLASH Registers +@{*/ +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0c) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) +#define FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +#define FLASH_PCROP1ASR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24) +#define FLASH_PCROP1AER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28) +#define FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2c) +#define FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30) +#define FLASH_PCROP1BSR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x34) +#define FLASH_PCROP1BER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x38) +#define FLASH_SECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) +/**@}*/ + +/* --- FLASH_ACR values ----------------------------------------------------- */ + +#define FLASH_ACR_DBG_SWEN (1 << 18) +#define FLASH_ACR_EMPTY (1 << 16) +#define FLASH_ACR_ICRST (1 << 11) +#define FLASH_ACR_ICEN (1 << 9) +#define FLASH_ACR_PRFTEN (1 << 8) + +#define FLASH_ACR_LATENCY_SHIFT 0 +#define FLASH_ACR_LATENCY_MASK 0x7 +/** @defgroup flash_latency FLASH Wait States + * @brief Flash memory access latency. flash HCLK max freq for 0ws is 24mhz (range 1 voltage) / 8mhz (range 0), 48mhz/16mhz for 1ws and 64mhz for 2ws. +@{*/ +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +#define FLASH_ACR_LATENCY_2WS 0x02 +/**@}*/ + +/* --- FLASH_KEYR values ---------------------------------------------------- */ + +#define FLASH_KEYR_KEY1 ((uint32_t)0x08192a3b) +#define FLASH_KEYR_KEY2 ((uint32_t)0x4c5d6e7f) + +#define FLASH_OPTKEYR_KEY1 FLASH_KEYR_KEY1 +#define FLASH_OPTKEYR_KEY2 FLASH_KEYR_KEY2 + +/* --- FLASH_SR values ------------------------------------------------------ */ +#define FLASH_SR_CFGBSY (1 << 18) +#define FLASH_SR_BSY (1 << 16) +#define FLASH_SR_OPTVERR (1 << 15) +#define FLASH_SR_RDERR (1 << 14) +#define FLASH_SR_FASTERR (1 << 9) +#define FLASH_SR_MISERR (1 << 8) +#define FLASH_SR_PGSERR (1 << 7) +#define FLASH_SR_SIZERR (1 << 6) +#define FLASH_SR_PGAERR (1 << 5) +#define FLASH_SR_WRPERR (1 << 4) +#define FLASH_SR_PROGERR (1 << 3) +#define FLASH_SR_OPERR (1 << 1) +#define FLASH_SR_EOP (1 << 0) + +/* --- FLASH_CR values ------------------------------------------------------ */ + +#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_OPTLOCK (1 << 30) +#define FLASH_CR_SEC_PROT (1 << 28) +#define FLASH_CR_OBL_LAUNCH (1 << 27) +#define FLASH_CR_RDERRIE (1 << 26) +#define FLASH_CR_ERRIE (1 << 25) +#define FLASH_CR_EOPIE (1 << 24) +#define FLASH_CR_FSTPG (1 << 18) +#define FLASH_CR_OPTSTRT (1 << 17) +#define FLASH_CR_STRT (1 << 16) + +#define FLASH_CR_PNB_SHIFT 3 +#define FLASH_CR_PNB_MASK 0x3f + +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) + +/* --- FLASH_ECCR values ---------------------------------------------------- */ + +#define FLASH_ECCR_ECCD (1 << 31) +#define FLASH_ECCR_ECCC (1 << 30) +#define FLASH_ECCR_ECCIE (1 << 24) +#define FLASH_ECCR_SYSF_ECC (1 << 20) +#define FLASH_ECCR_ADDR_ECC_SHIFT 0 +#define FLASH_ECCR_ADDR_ECC_MASK 0x3fff +/* --- FLASH_OPTR values ---------------------------------------------------- */ + +#define FLASH_OPTR_IRHEN (1 << 29) + +#define FLASH_OPTR_NRST_MODE_SHIFT 27 +#define FLASH_OPTR_NRST_MODE_MASK 0x03 +/** @defgroup flash_optr_nrst_mode NRST MODE +* @brief NRST_MODE +@{*/ +#define FLASH_OPTR_NRST_MODE_RESET 1 +#define FLASH_OPTR_NRST_MODE_GPIO 2 +#define FLASH_OPTR_NRST_MODE_BIDIR 3 +/**@}*/ + +#define FLASH_OPTR_nBOOT0 (1 << 26) +#define FLASH_OPTR_nBOOT1 (1 << 25) +#define FLASH_OPTR_nBOOT_SEL (1 << 24) +#define FLASH_OPTR_RAM_PARITY_CHECK (1 << 22) +#define FLASH_OPTR_WWDG_SW (1 << 19) +#define FLASH_OPTR_IWDG_STDBY (1 << 18) +#define FLASH_OPTR_IWDG_STOP (1 << 17) +#define FLASH_OPTR_IDWG_SW (1 << 16) +#define FLASH_OPTR_nRSTS_HDW (1 << 15) +#define FLASH_OPTR_nRST_STDBY (1 << 14) +#define FLASH_OPTR_nRST_STOP (1 << 13) + +#define FLASH_OPTR_BORR_LEV_SHIFT 11 +#define FLASH_OPTR_BORR_LEV_MASK 0x03 +/** @defgroup flash_optr_borr_lev BORR LEV +* @brief These bits contain the VDD supply level threshold that releases the reset. +@{*/ +#define FLASH_OPTR_BORR_LEV_2V1 0 +#define FLASH_OPTR_BORR_LEV_2V3 1 +#define FLASH_OPTR_BORR_LEV_2V6 2 +#define FLASH_OPTR_BORR_LEV_2V9 3 +/**@}*/ + +#define FLASH_OPTR_BORF_LEV_SHIFT 9 +#define FLASH_OPTR_BORF_LEV_MASK 0x03 +/** @defgroup flash_optr_borf_lev BOR FLEV +* @brief These bits contain the VDD supply level threshold that activates the reset +@{*/ +#define FLASH_OPTR_BORF_LEV_2V0 0 +#define FLASH_OPTR_BORF_LEV_2V2 1 +#define FLASH_OPTR_BORF_LEV_2V5 2 +#define FLASH_OPTR_BORF_LEV_2V8 3 +/**@}*/ + +#define FLASH_OPTR_BOREN (1 << 8) + +#define FLASH_OPTR_RDP_SHIFT 0 +#define FLASH_OPTR_RDP_MASK 0xff +/** @defgroup flash_optr_rdp RDP +* @brief Read protection level +@{*/ +#define FLASH_OPTR_RDP_LEVEL_0 0xAA +#define FLASH_OPTR_RDP_LEVEL_1 0xBB +#define FLASH_OPTR_RDP_LEVEL_2 0xCC /* or any other value. */ +/**@}*/ + +BEGIN_DECLS + +/** Enable instruction cache */ +void flash_icache_enable(void); +/** Disable instruction cache */ +void flash_icache_disable(void); +/** Reset instruction cache */ +void flash_icache_reset(void); + +/** Unlock program memory */ +void flash_unlock_progmem(void); +/** lock program memory */ +void flash_lock_progmem(void); + +/** Lock Option Byte Access */ +void flash_lock_option_bytes(void); + +END_DECLS + +#endif +/**@}*/ diff --git a/include/libopencm3/stm32/g0/gpio.h b/include/libopencm3/stm32/g0/gpio.h new file mode 100644 index 00000000..1b8357da --- /dev/null +++ b/include/libopencm3/stm32/g0/gpio.h @@ -0,0 +1,75 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx General Purpose I/O</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include <libopencm3/stm32/common/gpio_common_f24.h> + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define GPIO_BRR(port) MMIO32((port) + 0x28) +#define GPIOA_BRR GPIO_BRR(GPIOA) +#define GPIOB_BRR GPIO_BRR(GPIOB) +#define GPIOC_BRR GPIO_BRR(GPIOC) +#define GPIOD_BRR GPIO_BRR(GPIOD) +#define GPIOE_BRR GPIO_BRR(GPIOE) +#define GPIOF_BRR GPIO_BRR(GPIOF) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/** @defgroup gpio_speed GPIO Output Pin Speed +@{*/ +#define GPIO_OSPEED_LOW 0x0 +#define GPIO_OSPEED_MED 0x1 +#define GPIO_OSPEED_HIGH 0x2 +#define GPIO_OSPEED_VERYHIGH 0x3 +/**@}*/ + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif +/**@}*/ diff --git a/lib/stm32/f3/timer.c b/include/libopencm3/stm32/g0/i2c.h index 0e9ac3d4..d91cc779 100644 --- a/lib/stm32/f3/timer.c +++ b/include/libopencm3/stm32/g0/i2c.h @@ -1,16 +1,13 @@ -/** @defgroup timer_file TIMER +/** @defgroup i2c_defines I2C Defines * - * @ingroup STM32F3xx + * @ingroup STM32G0xx_defines * - * @brief <b>libopencm3 STM32F3xx Timers</b> + * @brief <b>Defined Constants and Types for the STM32G0xx I2C</b> * * @version 1.0.0 * - * @date 11 July 2013 - * * LGPL License Terms @ref lgpl_license - */ - + * */ /* * This file is part of the libopencm3 project. * @@ -28,6 +25,10 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/timer.h> +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include <libopencm3/stm32/common/i2c_common_v2.h> +#endif diff --git a/include/libopencm3/stm32/g0/irq.json b/include/libopencm3/stm32/g0/irq.json new file mode 100644 index 00000000..aa43cbc1 --- /dev/null +++ b/include/libopencm3/stm32/g0/irq.json @@ -0,0 +1,39 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "rtc", + "flash", + "rcc", + "exti0_1", + "exti2_3", + "exti4_15", + "ucpd1_ucpd2", + "dma1_channel1", + "dma1_channel2_3", + "dma1_channel4_7_dmamux", + "adc_comp", + "tim1_brk_up_trg_com", + "tim1_cc", + "tim2", + "tim3", + "tim6_dac_lptim1", + "tim7_lptim2", + "tim14", + "tim15", + "tim16", + "tim17", + "i2c1", + "i2c2", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3_usart4_lpuart1", + "cec", + "aes_rng" + ], + "partname_humanreadable": "STM32 G0 series", + "partname_doxygen": "STM32G0", + "includeguard": "LIBOPENCM3_STM32_G0_NVIC_H" +} diff --git a/lib/stm32/f0/rtc.c b/include/libopencm3/stm32/g0/iwdg.h index 6d55cc71..76af04bb 100644 --- a/lib/stm32/f0/rtc.c +++ b/include/libopencm3/stm32/g0/iwdg.h @@ -1,16 +1,13 @@ -/** @defgroup rtc_file RTC +/** @defgroup iwdg_defines IWDG Defines * - * @ingroup STM32F0xx + * @ingroup STM32G0xx_defines * - * @brief <b>libopencm3 STM32F0xx RTC</b> + * @brief <b>Defined Constants and Types for the STM32G0xx Independent Watchdog Timer</b> * * @version 1.0.0 * - * @date 10 July 2013 - * * LGPL License Terms @ref lgpl_license - */ - + * */ /* * This file is part of the libopencm3 project. * @@ -28,4 +25,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/rtc.h> +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include <libopencm3/stm32/common/iwdg_common_v2.h> + +#endif diff --git a/include/libopencm3/stm32/g0/lptimer.h b/include/libopencm3/stm32/g0/lptimer.h new file mode 100644 index 00000000..e3606d7c --- /dev/null +++ b/include/libopencm3/stm32/g0/lptimer.h @@ -0,0 +1,70 @@ +/** @defgroup lptimer_defines LPTIM Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>libopencm3 Defined Constants and Types for the STM32G0xx Low Power Timer</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_LPTIMER_H +#define LIBOPENCM3_LPTIMER_H +/**@{*/ + +#include <libopencm3/stm32/common/lptimer_common_all.h> + +/** @defgroup lptim_reg_base Low Power Timer register base addresses +@{*/ +#define LPTIM1 LPTIM1_BASE +#define LPTIM2 LPTIM2_BASE +/**@}*/ + +/** LPTIM_CFGR2 LPTIM configuration register 2 */ +#define LPTIM_CFGR2(tim_base) MMIO32((tim_base) + 0x24) + +/** @addtogroup lptim_cr +@{*/ +/** COUNTRST Counter reset **/ +#define LPTIM_CR_COUNTRST (1 << 3) +/** RSTARE Reset after read enable **/ +#define LPTIM_CR_RSTARE (1 << 4) +/**@}*/ + +/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2 +@{*/ + +#define LPTIM_CFGR2_IN2SEL_SHIFT 4 +#define LPTIM_CFGR2_IN2SEL_MASK 0x03 + +#define LPTIM_CFGR2_IN1SEL_SHIFT 0 +#define LPTIM_CFGR2_IN1SEL_MASK 0x03 + +/**@}*/ + + +BEGIN_DECLS + +END_DECLS + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/g0/memorymap.h b/include/libopencm3/stm32/g0/memorymap.h new file mode 100644 index 00000000..d6069ccc --- /dev/null +++ b/include/libopencm3/stm32/g0/memorymap.h @@ -0,0 +1,88 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include <libopencm3/cm3/memorymap.h> + +#define PERIPH_BASE (0x40000000U) +#define IOPORT_BASE (0x50000000U) +#define INFO_BASE (0x1fff7500U) +#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) + +/* APB */ +#define TIM2_BASE (PERIPH_BASE_APB + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB + 0x0400) +#define TIM6_BASE (PERIPH_BASE_APB + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB + 0x1400) +#define TIM14_BASE (PERIPH_BASE_APB + 0x2000) +#define RTC_BASE (PERIPH_BASE_APB + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB + 0x3000) +#define SPI2_BASE (PERIPH_BASE_APB + 0x3800) +#define USART2_BASE (PERIPH_BASE_APB + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB + 0x4800) +#define USART4_BASE (PERIPH_BASE_APB + 0x4C00) +#define I2C1_BASE (PERIPH_BASE_APB + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB + 0x5800) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB + 0x7400) +#define CEC_BASE (PERIPH_BASE_APB + 0x7800) +#define LPTIM1_BASE (PERIPH_BASE_APB + 0x7c00) +#define LPUART1_BASE (PERIPH_BASE_APB + 0x8000) +#define LPTIM2_BASE (PERIPH_BASE_APB + 0x9400) +#define UCPD1_BASE (PERIPH_BASE_APB + 0xA000) +#define UCPD2_BASE (PERIPH_BASE_APB + 0xA400) +#define TAMP_BASE (PERIPH_BASE_APB + 0xB000) +#define SYSCFG_BASE (PERIPH_BASE_APB + 0x10000) +#define VREFBUF_BASE (PERIPH_BASE_APB + 0x10030) +#define SYSCFG_ITLINE_BASE (PERIPH_BASE_APB + 0x10080) +#define COMP_BASE (PERIPH_BASE_APB + 0x10200) +#define ADC1_BASE (PERIPH_BASE_APB + 0x12400) +#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) +#define SPI1_BASE (PERIPH_BASE_APB + 0x13000) +#define USART1_BASE (PERIPH_BASE_APB + 0x13800) +#define TIM15_BASE (PERIPH_BASE_APB + 0x14000) +#define TIM16_BASE (PERIPH_BASE_APB + 0x14400) +#define TIM17_BASE (PERIPH_BASE_APB + 0x14800) +#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800) + +/* AHB */ +#define DMA1_BASE (PERIPH_BASE_AHB + 0x00000) +#define DMAMUX_BASE (PERIPH_BASE_AHB + 0x00800) +#define RCC_BASE (PERIPH_BASE_AHB + 0x01000) +#define EXTI_BASE (PERIPH_BASE_AHB + 0x01800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x02000) +#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) +#define RNG_BASE (PERIPH_BASE_AHB + 0x05000) +#define AES_BASE (PERIPH_BASE_AHB + 0x06000) + +#define GPIO_PORT_A_BASE (IOPORT_BASE + 0x00000) +#define GPIO_PORT_B_BASE (IOPORT_BASE + 0x00400) +#define GPIO_PORT_C_BASE (IOPORT_BASE + 0x00800) +#define GPIO_PORT_D_BASE (IOPORT_BASE + 0x00c00) +#define GPIO_PORT_E_BASE (IOPORT_BASE + 0x01000) +#define GPIO_PORT_F_BASE (IOPORT_BASE + 0x01400) + +/* ST provided factory calibration values @ 3.0V */ +#define ST_VREFINT_CAL MMIO16((INFO_BASE + 0xAA)) +#define ST_TSENSE_CAL1_30C MMIO16((INFO_BASE + 0xA8)) +#define ST_TSENSE_CAL2_130C MMIO16((INFO_BASE + 0xCA)) + +#endif diff --git a/include/libopencm3/stm32/g0/pwr.h b/include/libopencm3/stm32/g0/pwr.h new file mode 100644 index 00000000..c2264d94 --- /dev/null +++ b/include/libopencm3/stm32/g0/pwr.h @@ -0,0 +1,202 @@ +/** @defgroup pwr_defines PWR Defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx PWR Control</b> + * + * @ingroup STM32G0xx_defines + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H +/**@{*/ + +/** @defgroup pwr_registers PWR Registers +@{*/ +/** Power control register 1 (PWR_CR1) */ +#define PWR_CR1 MMIO32(POWER_CONTROL_BASE + 0x00) + +/** Power control register 2 (PWR_CR2) */ +#define PWR_CR2 MMIO32(POWER_CONTROL_BASE + 0x04) + +/** Power control register 3 (PWR_CR3) */ +#define PWR_CR3 MMIO32(POWER_CONTROL_BASE + 0x08) + +/** Power control register 4 (PWR_CR4) */ +#define PWR_CR4 MMIO32(POWER_CONTROL_BASE + 0x0c) + +/** Power status register 1 (PWR_SR1) */ +#define PWR_SR1 MMIO32(POWER_CONTROL_BASE + 0x10) + +/** Power status registery 2 (PWR_SR2) */ +#define PWR_SR2 MMIO32(POWER_CONTROL_BASE + 0x14) + +/** Power status clear register (PWR_SCR) */ +#define PWR_SCR MMIO32(POWER_CONTROL_BASE + 0x18) + +#define PWR_PORT_A MMIO32(POWER_CONTROL_BASE + 0x20) +#define PWR_PORT_B MMIO32(POWER_CONTROL_BASE + 0x28) +#define PWR_PORT_C MMIO32(POWER_CONTROL_BASE + 0x30) +#define PWR_PORT_D MMIO32(POWER_CONTROL_BASE + 0x38) +#define PWR_PORT_E MMIO32(POWER_CONTROL_BASE + 0x40) +#define PWR_PORT_F MMIO32(POWER_CONTROL_BASE + 0x48) + +#define PWR_PUCR(pwr_port) MMIO32((pwr_port) + 0x00) +#define PWR_PDCR(pwr_port) MMIO32((pwr_port) + 0x04) +/**@}*/ + +/* --- PWR_CR1 values ------------------------------------------------------- */ + +#define PWR_CR1_LPR (1 << 14) + +#define PWR_CR1_VOS_SHIFT 9 +#define PWR_CR1_VOS_MASK 0x3 +/** @defgroup pwr_cr1_vos VOS + * @brief Voltage scaling range selection. +@{*/ +#define PWR_CR1_VOS_RANGE_1 1 +#define PWR_CR1_VOS_RANGE_2 2 +/**@}*/ + +#define PWR_CR1_DBP (1 << 8) + +#define PWR_CR1_FPD_LPSLP (1 << 5) +#define PWR_CR1_FPD_LPRUN (1 << 4) +#define PWR_CR1_FPD_STOP (1 << 3) + +#define PWR_CR1_LPMS_SHIFT 0 +#define PWR_CR1_LPMS_MASK 0x07 +/** @defgroup pwr_cr1_lpms LPMS + * @ingroup STM32G0xx_pwr_defines + * @brief Low-power mode selection +@{*/ +#define PWR_CR1_LPMS_STOP_0 0 +#define PWR_CR1_LPMS_STOP_1 1 +#define PWR_CR1_LPMS_STANDBY 3 +#define PWR_CR1_LPMS_SHUTDOWN 4 +/**@}*/ + +/* --- PWR_CR2 values ------------------------------------------------------- */ + +#define PWR_CR2_PVDRT_SHIFT 4 +#define PWR_CR2_PVDRT_MASK 0x07 +/** @defgroup pwr_cr2_pvdrt PVDRT + * @brief Power voltage detector rising threshold selection +@{*/ +#define PWR_CR2_PVDRT_2V1 0x00 +#define PWR_CR2_PVDRT_2V2 0x01 +#define PWR_CR2_PVDRT_2V5 0x02 +#define PWR_CR2_PVDRT_2V6 0x03 +#define PWR_CR2_PVDRT_2V7 0x04 +#define PWR_CR2_PVDRT_2V9 0x05 +#define PWR_CR2_PVDRT_3V0 0x06 +#define PWR_CR2_PVDRT_PVD_IN 0x07 +/**@}*/ + +#define PWR_CR2_PVDFT_SHIFT 1 +#define PWR_CR2_PVDFT_MASK 0x07 +/** @defgroup pwr_cr2_pvdft PVDFT + * @brief Power voltage detector falling threshold selection +@{*/ +#define PWR_CR2_PVDFT_2V0 0x00 +#define PWR_CR2_PVDFT_2V2 0x01 +#define PWR_CR2_PVDFT_2V4 0x02 +#define PWR_CR2_PVDFT_2V5 0x03 +#define PWR_CR2_PVDFT_2V6 0x04 +#define PWR_CR2_PVDFT_2V8 0x05 +#define PWR_CR2_PVDFT_2V9 0x06 +/**@}*/ + +#define PWR_CR2_PVDE (1 << 0) + +/* --- PWR_CR3 values ------------------------------------------------------- */ + +#define PWR_CR3_EIWUL (1 << 15) +#define PWR_CR3_APC (1 << 10) +#define PWR_CR3_ULPEN (1 << 9) +#define PWR_CR3_RRS (1 << 8) +#define PWR_CR3_EWUP6 (1 << 5) +#define PWR_CR3_EWUP5 (1 << 4) +#define PWR_CR3_EWUP4 (1 << 3) +#define PWR_CR3_EWUP2 (1 << 1) +#define PWR_CR3_EWUP1 (1 << 0) + +/* --- PWR_CR4 values ------------------------------------------------------- */ + +#define PWR_CR4_VBRS (1 << 9) +#define PWR_CR4_VBE (1 << 8) +#define PWR_CR4_WP6 (1 << 5) +#define PWR_CR4_WP5 (1 << 4) +#define PWR_CR4_WP4 (1 << 3) +#define PWR_CR4_WP2 (1 << 1) +#define PWR_CR4_WP1 (1 << 0) + +/* --- PWR_SR1 values ------------------------------------------------------- */ + +#define PWR_SR1_WUFI (1 << 15) +#define PWR_SR1_SBF (1 << 8) +#define PWR_SR1_WUF6 (1 << 5) +#define PWR_SR1_WUF5 (1 << 4) +#define PWR_SR1_WUF4 (1 << 3) +#define PWR_SR1_WUF2 (1 << 1) +#define PWR_SR1_WUF1 (1 << 0) + +/* --- PWR_SR2 values ------------------------------------------------------- */ + +#define PWR_SR2_PVDO (1 << 11) +#define PWR_SR2_VOSF (1 << 10) +#define PWR_SR2_REGLPF (1 << 9) +#define PWR_SR2_REGLPS (1 << 8) +#define PWR_SR2_FLASHRDY (1 << 8) + +/* --- PWR_SCR values ------------------------------------------------------- */ + +#define PWR_SCR_CSBF (1 << 8) +#define PWR_SCR_CWUF6 (1 << 5) +#define PWR_SCR_CWUF5 (1 << 4) +#define PWR_SCR_CWUF4 (1 << 3) +#define PWR_SCR_CWUF2 (1 << 1) +#define PWR_SCR_CWUF1 (1 << 0) + +/* --- Function prototypes ------------------------------------------------- */ + +enum pwr_vos_scale { + PWR_SCALE1 = PWR_CR1_VOS_RANGE_1, + PWR_SCALE2 = PWR_CR1_VOS_RANGE_2, +}; + +BEGIN_DECLS + +void pwr_set_vos_scale(enum pwr_vos_scale scale); + +void pwr_disable_backup_domain_write_protect(void); +void pwr_enable_backup_domain_write_protect(void); + +void pwr_set_low_power_mode_selection(uint32_t lpms); + +void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level); +void pwr_disable_power_voltage_detect(void); + +END_DECLS + +/**@}*/ +#endif + diff --git a/include/libopencm3/stm32/g0/rcc.h b/include/libopencm3/stm32/g0/rcc.h new file mode 100644 index 00000000..dd989cef --- /dev/null +++ b/include/libopencm3/stm32/g0/rcc.h @@ -0,0 +1,842 @@ +/** @defgroup rcc_defines RCC Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx Reset and Clock Control</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + * + */ + +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include <libopencm3/stm32/pwr.h> + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x0c) +#define RCC_CIER MMIO32(RCC_BASE + 0x18) +#define RCC_CIFR MMIO32(RCC_BASE + 0x1c) +#define RCC_CICR MMIO32(RCC_BASE + 0x20) +#define RCC_IOPRSTR_OFFSET 0x24 +#define RCC_IOPRSTR MMIO32(RCC_BASE + RCC_IOPRSTR_OFFSET) +#define RCC_AHBRSTR_OFFSET 0x28 +#define RCC_AHBRSTR MMIO32(RCC_BASE + RCC_AHBRSTR_OFFSET) +#define RCC_APBRSTR1_OFFSET 0x2c +#define RCC_APBRSTR1 MMIO32(RCC_BASE + RCC_APBRSTR1_OFFSET) +#define RCC_APBRSTR2_OFFSET 0x30 +#define RCC_APBRSTR2 MMIO32(RCC_BASE + RCC_APBRSTR2_OFFSET) +#define RCC_IOPENR_OFFSET 0x34 +#define RCC_IOPENR MMIO32(RCC_BASE + RCC_IOPENR_OFFSET) +#define RCC_AHBENR_OFFSET 0x38 +#define RCC_AHBENR MMIO32(RCC_BASE + RCC_AHBENR_OFFSET) +#define RCC_APBENR1_OFFSET 0x3c +#define RCC_APBENR1 MMIO32(RCC_BASE + RCC_APBENR1_OFFSET) +#define RCC_APBENR2_OFFSET 0x40 +#define RCC_APBENR2 MMIO32(RCC_BASE + RCC_APBENR2_OFFSET) +#define RCC_IOPSMENR_OFFSET 0x44 +#define RCC_IOPSMENR MMIO32(RCC_BASE + RCC_IOPSMENR_OFFSET) +#define RCC_AHBSMENR_OFFSET 0x48 +#define RCC_AHBSMENR MMIO32(RCC_BASE + RCC_AHBSMENR_OFFSET) +#define RCC_APBSMENR1_OFFSET 0x4c +#define RCC_APBSMENR1 MMIO32(RCC_BASE + RCC_APBSMENR1_OFFSET) +#define RCC_APBSMENR2_OFFSET 0x50 +#define RCC_APBSMENR2 MMIO32(RCC_BASE + RCC_APBSMENR2_OFFSET) +#define RCC_CCIPR MMIO32(RCC_BASE + 0x54) +#define RCC_BDCR MMIO32(RCC_BASE + 0x5c) +#define RCC_CSR MMIO32(RCC_BASE + 0x60) + + + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) + +#define RCC_CR_HSIDIV_SHIFT 11 +#define RCC_CR_HSIDIV_MASK 0x7 +/** @defgroup rcc_cr_hsidiv HSI Div + * @brief Division factor of the HSI16 oscillator to produce HSISYS clock +@sa rcc_cr_hsidiv +@{*/ +#define RCC_CR_HSIDIV_DIV1 0 +#define RCC_CR_HSIDIV_DIV2 1 +#define RCC_CR_HSIDIV_DIV4 2 +#define RCC_CR_HSIDIV_DIV8 3 +#define RCC_CR_HSIDIV_DIV16 4 +#define RCC_CR_HSIDIV_DIV32 5 +#define RCC_CR_HSIDIV_DIV64 6 +#define RCC_CR_HSIDIV_DIV128 7 +/**@}*/ + +#define RCC_CR_HSIRDY (1 << 10) +#define RCC_CR_HSIKERON (1 << 9) +#define RCC_CR_HSION (1 << 8) + +/* --- RCC_ICSCR values ---------------------------------------------------- */ + +#define RCC_ICSCR_HSITRIM_SHIFT 8 +#define RCC_ICSCR_HSITRIM_MASK 0x1f +#define RCC_ICSCR_HSICAL_SHIFT 0 +#define RCC_ICSCR_HSICAL_MASK 0xff + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +#define RCC_CFGR_MCOPRE_SHIFT 28 +#define RCC_CFGR_MCOPRE_MASK 0x7 +/** @defgroup rcc_cfgr_mcopre MCO Pre + * @brief Division factor of microcontroler clock output +@sa rcc_cfgr_mcopre +@{*/ +#define RCC_CFGR_MCOPRE_DIV1 0 +#define RCC_CFGR_MCOPRE_DIV2 1 +#define RCC_CFGR_MCOPRE_DIV4 2 +#define RCC_CFGR_MCOPRE_DIV8 3 +#define RCC_CFGR_MCOPRE_DIV16 4 +#define RCC_CFGR_MCOPRE_DIV32 5 +#define RCC_CFGR_MCOPRE_DIV64 6 +#define RCC_CFGR_MCOPRE_DIV128 7 +/**@}*/ + +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO_MASK 0xf + +/** @defgroup rcc_cfgr_mcosel MCO Sel + * @brief Microcontroler clock output selector +@sa rcc_cfgr_mcosel +@{*/ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x1 +#define RCC_CFGR_MCO_HSI16 0x3 +#define RCC_CFGR_MCO_HSE 0x4 +#define RCC_CFGR_MCO_PLLRCLK 0x5 +#define RCC_CFGR_MCO_LSI 0x6 +#define RCC_CFGR_MCO_LSE 0x7 +/**@}*/ + +#define RCC_CFGR_PPRE_MASK 0x7 +#define RCC_CFGR_PPRE_SHIFT 12 + +/** @defgroup rcc_cfgr_ppre PPRE + * @brief APB Prescaler +@sa rcc_cfgr_ppre +@{*/ +#define RCC_CFGR_PPRE_NODIV 0x0 +#define RCC_CFGR_PPRE_DIV2 0x4 +#define RCC_CFGR_PPRE_DIV4 0x5 +#define RCC_CFGR_PPRE_DIV8 0x6 +#define RCC_CFGR_PPRE_DIV16 0x7 +/**@}*/ + +#define RCC_CFGR_HPRE_MASK 0xf +#define RCC_CFGR_HPRE_SHIFT 8 +/** @defgroup rcc_cfgr_hpre HPRE + * @brief APB Prescaler +@sa rcc_cfgr_hpre +@{*/ +#define RCC_CFGR_HPRE_NODIV 0x0 +#define RCC_CFGR_HPRE_DIV2 0x8 +#define RCC_CFGR_HPRE_DIV4 0x9 +#define RCC_CFGR_HPRE_DIV8 0xa +#define RCC_CFGR_HPRE_DIV16 0xb +#define RCC_CFGR_HPRE_DIV64 0xc +#define RCC_CFGR_HPRE_DIV128 0xd +#define RCC_CFGR_HPRE_DIV256 0xe +#define RCC_CFGR_HPRE_DIV512 0xf +/**@}*/ + +#define RCC_CFGR_SWS_MASK 0x3 +#define RCC_CFGR_SWS_SHIFT 3 +/** @defgroup rcc_cfgr_sws SWS + * @brief System clock switch status +@sa rcc_cfgr_sws +@{*/ +#define RCC_CFGR_SWS_HSISYS 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLLRCLK 0x2 +#define RCC_CFGR_SWS_LSI 0x3 +#define RCC_CFGR_SWS_LSE 0x4 +/**@}*/ + +#define RCC_CFGR_SW_MASK 0x3 +#define RCC_CFGR_SW_SHIFT 0 +/** @defgroup rcc_cfgr_sws SW + * @brief System clock switch +@sa rcc_cfgr_sw +@{*/ +#define RCC_CFGR_SW_HSISYS 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLLRCLK 0x2 +#define RCC_CFGR_SW_LSI 0x3 +#define RCC_CFGR_SW_LSE 0x4 +/**@}*/ + +/* --- RCC_PLLCFGR - PLL Configuration Register */ + +#define RCC_PLLCFGR_PLLR_SHIFT 29 +#define RCC_PLLCFGR_PLLR_MASK 0x7 +/** @defgroup rcc_pllcfgr_pllr PLLR + * @brief VCO Division factor R for PLLRCLK clock output [2..8]. Frequency must not exceed 64mhz in voltage range 1, or 16mhz in voltage range 2. +@sa rcc_pllcfgr_pllr +@{*/ +#define RCC_PLLCFGR_PLLR_DIV(x) ((x)-1) +/**@}*/ + +#define RCC_PLLCFGR_PLLREN (1<<28) + +#define RCC_PLLCFGR_PLLQ_SHIFT 25 +#define RCC_PLLCFGR_PLLQ_MASK 0x7 +/** @defgroup rcc_pllcfgr_pllq PLLQ + * @brief VCO Division factor Q for PLLQCLK clock output [2..8]. Frequency must not exceed 128mhz in voltage range 1, or 32mhz in range 2 +@sa rcc_pllcfgr_pllq +@{*/ +#define RCC_PLLCFGR_PLLQ_DIV(x) ((x)-1) +/**@}*/ + +#define RCC_PLLCFGR_PLLQEN (1 << 24) + +#define RCC_PLLCFGR_PLLP_SHIFT 17 +#define RCC_PLLCFGR_PLLP_MASK 0x1f +/** @defgroup rcc_pllcfgr_pllp PLLP + * @brief VCO Division factor P for PLLPCLK clock output [2..32]. Frequency must not exceed 122mhz in voltage range 1, or 40mhz in range 2 +@sa rcc_pllcfgr_pllp +@{*/ +#define RCC_PLLCFGR_PLLP_DIV(x) ((x)-1) +/**@}*/ + +#define RCC_PLLCFGR_PLLPEN (1 << 16) + +#define RCC_PLLCFGR_PLLN_SHIFT 0x8 +#define RCC_PLLCFGR_PLLN_MASK 0x7f +/** @defgroup rcc_pllcfgr_plln PLLN + * @brief Multiplication factor N [8..86] for PLL VCO output frequency. Frequency must be between 64mhz and 344mhz. +@{*/ +#define RCC_PLLCFGR_PLLN_MUL(x) (x) +/**@}*/ + +#define RCC_PLLCFGR_PLLM_SHIFT 0x4 +#define RCC_PLLCFGR_PLLM_MASK 0x7 +/** @defgroup rcc_pllcfgr_pllm PLLM + * @brief Division factor M [1..8] for PLL input clock. Input frequency must be between 4mhz and 16mhz. +@{*/ +#define RCC_PLLCFGR_PLLM_DIV(x) ((x)-1) +/**@}*/ + +#define RCC_PLLCFGR_PLLSRC_SHIFT 0 +#define RCC_PLLCFGR_PLLSRC_MASK 0x3 +/** @defgroup rcc_pllcfgr_pllsrc PLLSRC + * @brief PLL input clock source +@sa rcc_pllcfgr_pllsrc +@{*/ +#define RCC_PLLCFGR_PLLSRC_NONE 0 +#define RCC_PLLCFGR_PLLSRC_HSI16 2 +#define RCC_PLLCFGR_PLLSRC_HSE 3 +/**@}*/ + +/* --- RCC_CIER - Clock interrupt enable register */ + +#define RCC_CIER_PLLRDYIE (1 << 5) +#define RCC_CIER_HSERDYIE (1 << 4) +#define RCC_CIER_HSIRDYIE (1 << 3) +#define RCC_CIER_LSERDYIE (1 << 1) +#define RCC_CIER_LSIRDYIE (1 << 0) + +/* --- RCC_CIFR - Clock interrupt flag register */ + +#define RCC_CIFR_LSECSSF (1 << 9) +#define RCC_CIFR_CSSF (1 << 8) +#define RCC_CIFR_PLLRDYF (1 << 5) +#define RCC_CIFR_HSERDYF (1 << 4) +#define RCC_CIFR_HSIRDYF (1 << 3) +#define RCC_CIFR_LSERDYF (1 << 1) +#define RCC_CIFR_LSIRDYF (1 << 0) + +/* --- RCC_CICR - Clock interrupt flag register */ + +#define RCC_CICR_LSECSSC (1 << 9) +#define RCC_CICR_CSSC (1 << 8) +#define RCC_CICR_PLLRDYC (1 << 5) +#define RCC_CICR_HSERDYC (1 << 4) +#define RCC_CICR_HSIRDYC (1 << 3) +#define RCC_CICR_LSERDYC (1 << 1) +#define RCC_CICR_LSIRDYC (1 << 0) + +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values +@{*/ +#define RCC_AHBRSTR_RNGRST (1 << 18) +#define RCC_AHBRSTR_AESRST (1 << 16) +#define RCC_AHBRSTR_CRCRST (1 << 12) +#define RCC_AHBRSTR_FLASHRST (1 << 8) +#define RCC_AHBRSTR_DMARST (1 << 0) +/**@}*/ + +/** @defgroup rcc_apb1rstr_rst RCC_APBRSTRx reset values (full set) +@{*/ +/** @defgroup rcc_apbrstr1_rst RCC_APBRSTR1 reset values +@{*/ +#define RCC_APBRSTR1_LPTIM1RST (1 << 31) +#define RCC_APBRSTR1_LPTIM2RST (1 << 30) +#define RCC_APBRSTR1_DAC1RST (1 << 29) +#define RCC_APBRSTR1_PWRRST (1 << 28) +#define RCC_APBRSTR1_DBGRST (1 << 27) +#define RCC_APBRSTR1_UCPD2RST (1 << 26) +#define RCC_APBRSTR1_UCPD1RST (1 << 25) +#define RCC_APBRSTR1_I2C2RST (1 << 22) +#define RCC_APBRSTR1_I2C1RST (1 << 21) +#define RCC_APBRSTR1_LPUART1RST (1 << 20) +#define RCC_APBRSTR1_USART4RST (1 << 19) +#define RCC_APBRSTR1_USART3RST (1 << 18) +#define RCC_APBRSTR1_USART2RST (1 << 17) +#define RCC_APBRSTR1_SPI2RST (1 << 14) +#define RCC_APBRSTR1_TIM7RST (1 << 5) +#define RCC_APBRSTR1_TIM6RST (1 << 4) +#define RCC_APBRSTR1_TIM3RST (1 << 1) +#define RCC_APBRSTR1_TIM2RST (1 << 0) +/**@}*/ + +/** @defgroup rcc_apbrstr2_rst RCC_APBRSTR2 reset values +@{*/ +#define RCC_APBRSTR2_ADCRST (1 << 20) +#define RCC_APBRSTR2_TIM17RST (1 << 18) +#define RCC_APBRSTR2_TIM16RST (1 << 17) +#define RCC_APBRSTR2_TIM16RST (1 << 17) +#define RCC_APBRSTR2_TIM15RST (1 << 16) +#define RCC_APBRSTR2_TIM14RST (1 << 15) +#define RCC_APBRSTR2_USART1RST (1 << 14) +#define RCC_APBRSTR2_SPI1RST (1 << 12) +#define RCC_APBRSTR2_TIM1RST (1 << 11) +#define RCC_APBRSTR2_SYSCFGRST (1 << 0) +/**@}*/ +/**@}*/ + +/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values +@{*/ +#define RCC_AHBENR_RNGEN (1 << 18) +#define RCC_AHBENR_AESEN (1 << 16) +#define RCC_AHBENR_CRCEN (1 << 12) +#define RCC_AHBENR_FLASHEN (1 << 8) +#define RCC_AHBENR_DMAEN (1 << 0) +/**@}*/ + +/** @defgroup rcc_apb1enr_en RCC_APBENRx enable values (full set) +@{*/ +/** @defgroup rcc_apbenr1_en RCC_APBENR1 enable values +@{*/ +#define RCC_APBENR1_LPTIM1EN (1 << 31) +#define RCC_APBENR1_LPTIM2EN (1 << 30) +#define RCC_APBENR1_DAC1EN (1 << 29) +#define RCC_APBENR1_PWREN (1 << 28) +#define RCC_APBENR1_DBGEN (1 << 27) +#define RCC_APBENR1_UCPD2EN (1 << 26) +#define RCC_APBENR1_UCPD1EN (1 << 25) +#define RCC_APBENR1_CECEN (1 << 24) +#define RCC_APBENR1_I2C2EN (1 << 22) +#define RCC_APBENR1_I2C1EN (1 << 21) +#define RCC_APBENR1_LPUART1EN (1 << 20) +#define RCC_APBENR1_USART4EN (1 << 19) +#define RCC_APBENR1_USART3EN (1 << 18) +#define RCC_APBENR1_USART2EN (1 << 17) +#define RCC_APBENR1_SPI2EN (1 << 14) +#define RCC_APBENR1_WWDGEN (1 << 11) +#define RCC_APBENR1_RTCAPBEN (1 << 10) +#define RCC_APBENR1_TIM7EN (1 << 5) +#define RCC_APBENR1_TIM6EN (1 << 4) +#define RCC_APBENR1_TIM3EN (1 << 1) +#define RCC_APBENR1_TIM2EN (1 << 0) +/**@}*/ + +/** @defgroup rcc_apbenr2_en RCC_APBENR2 enable values +@{*/ +#define RCC_APBENR2_ADCEN (1 << 20) +#define RCC_APBENR2_TIM17EN (1 << 18) +#define RCC_APBENR2_TIM16EN (1 << 17) +#define RCC_APBENR2_TIM16EN (1 << 17) +#define RCC_APBENR2_TIM15EN (1 << 16) +#define RCC_APBENR2_TIM14EN (1 << 15) +#define RCC_APBENR2_USART1EN (1 << 14) +#define RCC_APBENR2_SPI1EN (1 << 12) +#define RCC_APBENR2_TIM1EN (1 << 11) +#define RCC_APBENR2_SYSCFGEN (1 << 0) +/**@}*/ +/**@}*/ + +/* --- RCC_AHBSMENR values ------------------------------------------------- */ + +/** @defgroup rcc_aphbsmenr_en RCC_AHBSMENR enable in sleep/stop mode values +@{*/ +#define RCC_AHBSMENR_RNGSMEN (1 << 18) +#define RCC_AHBSMENR_AESSMEN (1 << 16) +#define RCC_AHBSMENR_CRCSMEN (1 << 12) +#define RCC_AHBSMENR_SRAMSMEN (1 << 9) +#define RCC_AHBSMENR_FLASHSMEN (1 << 8) +#define RCC_AHBSMENR_DMASMEN (1 << 0) +/**@}*/ + +/* --- RCC_APBSMENR1 values ------------------------------------------------- */ + +/** @defgroup rcc_apbsmenr_en RCC_APBSMENR1 enable in sleep/stop mode values +@{*/ +#define RCC_APBSMENR1_LPTIM1SMEN (1 << 31) +#define RCC_APBSMENR1_LPTIM2SMEN (1 << 30) +#define RCC_APBSMENR1_DAC1SMEN (1 << 29) +#define RCC_APBSMENR1_PWRSMEN (1 << 28) +#define RCC_APBSMENR1_DBGSMEN (1 << 27) +#define RCC_APBSMENR1_UCPD2SMEN (1 << 26) +#define RCC_APBSMENR1_UCPD1SMEN (1 << 25) +#define RCC_APBSMENR1_CECSMEN (1 << 24) +#define RCC_APBSMENR1_I2C2SMEN (1 << 22) +#define RCC_APBSMENR1_I2C1SMEN (1 << 21) +#define RCC_APBSMENR1_LPUART1SMEN (1 << 20) +#define RCC_APBSMENR1_USART4SMEN (1 << 19) +#define RCC_APBSMENR1_USART3SMEN (1 << 18) +#define RCC_APBSMENR1_USART2SMEN (1 << 17) +#define RCC_APBSMENR1_SPI2SMEN (1 << 14) +#define RCC_APBSMENR1_WWDGSMEN (1 << 11) +#define RCC_APBSMENR1_RTCAPBSMEN (1 << 10) +#define RCC_APBSMENR1_TIM7SMEN (1 << 5) +#define RCC_APBSMENR1_TIM6SMEN (1 << 4) +#define RCC_APBSMENR1_TIM3SMEN (1 << 1) +#define RCC_APBSMENR1_TIM2SMEN (1 << 0) +/**@}*/ + +/* --- RCC_APBSMENR2 values ------------------------------------------------- */ + +/** @defgroup rcc_apbsmenr2_en RCC_APBSMENR2 enable in sleep/stop mode values +@{*/ +#define RCC_APBSMENR2_ADCSMEN (1 << 20) +#define RCC_APBSMENR2_TIM17SMEN (1 << 18) +#define RCC_APBSMENR2_TIM16SMEN (1 << 17) +#define RCC_APBSMENR2_TIM16SMEN (1 << 17) +#define RCC_APBSMENR2_TIM15SMEN (1 << 16) +#define RCC_APBSMENR2_TIM14SMEN (1 << 15) +#define RCC_APBSMENR2_USART1SMEN (1 << 14) +#define RCC_APBSMENR2_SPI1SMEN (1 << 12) +#define RCC_APBSMENR2_TIM1SMEN (1 << 11) +#define RCC_APBSMENR2_SYSCFGSMEN (1 << 0) +/**@}*/ + +/* --- RCC_CCIPR - Peripherals independent clock config register ----------- */ + +#define RCC_CCIPR_ADCSEL_MASK 0x3 +#define RCC_CCIPR_ADCSEL_SHIFT 30 +/** @defgroup rcc_ccipr_adcsel ADCSEL +@{*/ +#define RCC_CCIPR_ADCSEL_SYSCLK 0 +#define RCC_CCIPR_ADCSEL_PLLPCLK 1 +#define RCC_CCIPR_ADCSEL_HSI16 2 +/**@}*/ + +#define RCC_CCIPR_RNGDIV_MASK 0x3 +#define RCC_CCIPR_RNGDIV_SHIFT 28 +/** @defgroup rcc_ccipr_rngdiv RNGDIV +@{*/ +#define RCC_CCIPR_RNGDIV_1 0 +#define RCC_CCIPR_RNGDIV_2 1 +#define RCC_CCIPR_RNGDIV_4 2 +#define RCC_CCIPR_RNGDIV_8 3 +/**@}*/ + +#define RCC_CCIPR_RNGSEL_MASK 0x3 +#define RCC_CCIPR_RNGSEL_SHIFT 26 +/** @defgroup rcc_ccipr_rngsel RNGSEL +@{*/ +#define RCC_CCIPR_RNGSEL_NONE 0 +#define RCC_CCIPR_RNGSEL_HSI16 1 +#define RCC_CCIPR_RNGSEL_SYSCLK 2 +#define RCC_CCIPR_RNGSEL_PLLQCLK 3 +/**@}*/ + +#define RCC_CCIPR_TIM15SEL_MASK 0x1 +#define RCC_CCIPR_TIM15SEL_SHIFT 24 +/** @defgroup rcc_ccipr_tim15sel TIM15SEL +@{*/ +#define RCC_CCIPR_TIM15SEL_TIMPCLK 0 +#define RCC_CCIPR_TIM15SEL_PLLQCLK 1 +/**@}*/ + +#define RCC_CCIPR_TIM1SEL_MASK 0x1 +#define RCC_CCIPR_TIM1SEL_SHIFT 20 +/** @defgroup rcc_ccipr_tim1sel TIM1SEL +@{*/ +#define RCC_CCIPR_TIM1SEL_TIMPCLK 0 +#define RCC_CCIPR_TIM1SEL_PLLQCLK 1 +/**@}*/ + +#define RCC_CCIPR_LPTIM2SEL_MASK 0x3 +#define RCC_CCIPR_LPTIM2SEL_SHIFT 20 +/** @defgroup rcc_ccipr_lptim2sel LPTIM2SEL LPTIM2 Clock source selection +@{*/ +#define RCC_CCIPR_LPTIM2SEL_PCLK 0 +#define RCC_CCIPR_LPTIM2SEL_LSI 1 +#define RCC_CCIPR_LPTIM2SEL_HSI16 2 +#define RCC_CCIPR_LPTIM2SEL_LSE 3 +/**@}*/ + +#define RCC_CCIPR_LPTIM1SEL_MASK 0x3 +#define RCC_CCIPR_LPTIM1SEL_SHIFT 18 +/** @defgroup rcc_ccipr_lptim1sel LPTIM1SEL LPTIM1 Clock source selection +@{*/ +#define RCC_CCIPR_LPTIM1SEL_PCLK 0 +#define RCC_CCIPR_LPTIM1SEL_LSI 1 +#define RCC_CCIPR_LPTIM1SEL_HSI16 2 +#define RCC_CCIPR_LPTIM1SEL_LSE 3 +/**@}*/ + +#define RCC_CCIPR_I2S1SEL_MASK 0x3 +#define RCC_CCIPR_I2S1SEL_SHIFT 14 +/** @defgroup rcc_ccipr_i2s1sel I2S1SEL I2S1 Clock source selection +@{*/ +#define RCC_CCIPR_I2S1SEL_SYSCLK 0 +#define RCC_CCIPR_I2S1SEL_PLLPLCK 1 +#define RCC_CCIPR_I2S1SEL_HSI16 2 +#define RCC_CCIPR_I2S1SEL_I2S_CKIN 2 +/**@}*/ + +#define RCC_CCIPR_I2C1SEL_MASK 0x3 +#define RCC_CCIPR_I2C1SEL_SHIFT 12 +/** @defgroup rcc_ccipr_i2c1sel I2C1SEL I2C1 Clock source selection +@{*/ +#define RCC_CCIPR_I2C1SEL_PCLK 0 +#define RCC_CCIPR_I2C1SEL_SYSCLK 1 +#define RCC_CCIPR_I2C1SEL_HSI16 2 +/**@}*/ + +#define RCC_CCIPR_LPUART1SEL_MASK 0x3 +#define RCC_CCIPR_LPUART1SEL_SHIFT 10 +/** @defgroup rcc_ccipr_lpuart1sel LPUART1SEL LPUART1 Clock source selection +@{*/ +#define RCC_CCIPR_LPUART1SEL_PCLK 0 +#define RCC_CCIPR_LPUART1SEL_SYSCLK 1 +#define RCC_CCIPR_LPUART1SEL_HSI16 2 +#define RCC_CCIPR_LPUART1SEL_LSE 3 +/**@}*/ + +#define RCC_CCIPR_CECSEL_MASK 0x1 +#define RCC_CCIPR_CECSEL_SHIFT 6 +/** @defgroup rcc_ccipr_cecsel CECSEL CEC Clock souce selection +@{*/ +#define RCC_CCIPR_CECSEL_HSI16 0 +#define RCC_CCIPR_CECSEL_LSE 1 +/**@}*/ + +#define RCC_CCIPR_USART2SEL_MASK 0x3 +#define RCC_CCIPR_USART2SEL_SHIFT 2 +/** @defgroup rcc_ccipr_usart2sel USART2SEL USART2 Clock source selection +@{*/ +#define RCC_CCIPR_USART2SEL_PCLK 0 +#define RCC_CCIPR_USART2SEL_SYSCLK 1 +#define RCC_CCIPR_USART2SEL_HSI16 2 +#define RCC_CCIPR_USART2SEL_LSE 3 +/**@}*/ + +#define RCC_CCIPR_USART1SEL_MASK 0x3 +#define RCC_CCIPR_USART1SEL_SHIFT 0 +/** @defgroup rcc_ccipr_usart1sel USART1SEL USART1 Clock source selection +@{*/ +#define RCC_CCIPR_USART1SEL_PCLK 0 +#define RCC_CCIPR_USART1SEL_SYSCLK 1 +#define RCC_CCIPR_USART1SEL_HSI16 2 +#define RCC_CCIPR_USART1SEL_LSE 3 +/**@}*/ + +/* --- RCC_BDCR - PLL Configuration Register */ + +#define RCC_BDCR_LSCOSEL (1 << 25) +#define RCC_BDCR_LSCOEN (1 << 24) +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) + +#define RCC_BDCR_RTCSEL_SHIFT 8 +#define RCC_BDCR_RTCSEL_MASK 0x3 +/** @defgroup rcc_bdcr_rtcsel RTCSEL RTC Clock source selection +@{*/ +#define RCC_BDCR_RTCSEL_NONE 0 +#define RCC_BDCR_RTCSEL_LSE 1 +#define RCC_BDCR_RTCSEL_LSI 2 +#define RCC_BDCR_RTCSEL_HSE_DIV32 3 +/**@}*/ + +#define RCC_BDCR_LSEDRV_SHIFT 3 +#define RCC_BDCR_LSEDRV_MASK 0x3 +/** @defgroup rcc_bdcr_lsedrv LSEDRV LSE Oscillator drive capacity +@{*/ +#define RCC_BDCR_LSEDRV_LOW 0 +#define RCC_BDCR_LSEDRV_MEDLOW 1 +#define RCC_BDCR_LSEDRV_MEDHIGH 2 +#define RCC_BDCR_LSEDRV_HIGH 3 +/**@}*/ + +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR - Control/Status register ----------------------------------- */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PWRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 23) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- Variable definitions ------------------------------------------------ */ + +extern uint32_t rcc_ahb_frequency; +extern uint32_t rcc_apb1_frequency; +/* + * as done for F0, fake out apb2_frequency as the device does not really have + * apb2 clock. + */ +#define rcc_apb2_frequency rcc_apb1_frequency + +/* --- Function prototypes ------------------------------------------------- */ + +#define _REG_BIT(offset, bit) (((offset) << 5) + (bit)) + +enum rcc_osc { + RCC_HSI, + RCC_HSE, + RCC_PLL, + RCC_LSE, + RCC_LSI, +}; + +enum rcc_periph_clken { + RCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5), + RCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4), + RCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3), + RCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2), + RCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1), + RCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0), + + RCC_RNG = _REG_BIT(RCC_AHBENR_OFFSET, 18), + RCC_AES = _REG_BIT(RCC_AHBENR_OFFSET, 16), + RCC_CRC = _REG_BIT(RCC_AHBENR_OFFSET, 12), + RCC_FLASH = _REG_BIT(RCC_AHBENR_OFFSET, 8), + RCC_DMA = _REG_BIT(RCC_AHBENR_OFFSET, 0), + RCC_DMA1 = _REG_BIT(RCC_AHBENR_OFFSET, 0), /* Compatibility */ + + RCC_LPTIM1 = _REG_BIT(RCC_APBENR1_OFFSET, 31), + RCC_LPTIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 30), + RCC_DAC1 = _REG_BIT(RCC_APBENR1_OFFSET, 29), + RCC_PWR = _REG_BIT(RCC_APBENR1_OFFSET, 28), + RCC_DBG = _REG_BIT(RCC_APBENR1_OFFSET, 27), + RCC_UCPD1 = _REG_BIT(RCC_APBENR1_OFFSET, 26), + RCC_UCPD2 = _REG_BIT(RCC_APBENR1_OFFSET, 25), + RCC_CEC = _REG_BIT(RCC_APBENR1_OFFSET, 24), + RCC_I2C2 = _REG_BIT(RCC_APBENR1_OFFSET, 22), + RCC_I2C1 = _REG_BIT(RCC_APBENR1_OFFSET, 21), + RCC_LPUART1 = _REG_BIT(RCC_APBENR1_OFFSET, 20), + RCC_USART4 = _REG_BIT(RCC_APBENR1_OFFSET, 19), + RCC_USART3 = _REG_BIT(RCC_APBENR1_OFFSET, 18), + RCC_USART2 = _REG_BIT(RCC_APBENR1_OFFSET, 17), + RCC_SPI2 = _REG_BIT(RCC_APBENR1_OFFSET, 14), + RCC_TIM7 = _REG_BIT(RCC_APBENR1_OFFSET, 5), + RCC_TIM6 = _REG_BIT(RCC_APBENR1_OFFSET, 4), + RCC_TIM3 = _REG_BIT(RCC_APBENR1_OFFSET, 1), + RCC_TIM2 = _REG_BIT(RCC_APBENR1_OFFSET, 0), + + RCC_ADC = _REG_BIT(RCC_APBENR2_OFFSET, 20), + RCC_TIM17 = _REG_BIT(RCC_APBENR2_OFFSET, 18), + RCC_TIM16 = _REG_BIT(RCC_APBENR2_OFFSET, 17), + RCC_TIM15 = _REG_BIT(RCC_APBENR2_OFFSET, 16), + RCC_TIM14 = _REG_BIT(RCC_APBENR2_OFFSET, 15), + RCC_USART1 = _REG_BIT(RCC_APBENR2_OFFSET, 14), + RCC_SPI1 = _REG_BIT(RCC_APBENR2_OFFSET, 12), + RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11), + RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0), + + SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5), + SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4), + SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3), + SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2), + SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1), + SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0), + + SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18), + SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16), + SCC_CRC = _REG_BIT(RCC_AHBSMENR_OFFSET, 12), + SCC_FLASH = _REG_BIT(RCC_AHBSMENR_OFFSET, 8), + SCC_DMA = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), + SCC_DMA1 = _REG_BIT(RCC_AHBSMENR_OFFSET, 0), /* Compatibility */ + + SCC_LPTIM1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 31), + SCC_LPTIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 30), + SCC_DAC1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 29), + SCC_PWR = _REG_BIT(RCC_APBSMENR1_OFFSET, 28), + SCC_DBG = _REG_BIT(RCC_APBSMENR1_OFFSET, 27), + SCC_UCPD1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 26), + SCC_UCPD2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 25), + SCC_CEC = _REG_BIT(RCC_APBSMENR1_OFFSET, 24), + SCC_I2C2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 22), + SCC_I2C1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 21), + SCC_LPUART1 = _REG_BIT(RCC_APBSMENR1_OFFSET, 20), + SCC_USART4 = _REG_BIT(RCC_APBSMENR1_OFFSET, 19), + SCC_USART3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 18), + SCC_USART2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 17), + SCC_SPI2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 14), + SCC_TIM7 = _REG_BIT(RCC_APBSMENR1_OFFSET, 5), + SCC_TIM6 = _REG_BIT(RCC_APBSMENR1_OFFSET, 4), + SCC_TIM3 = _REG_BIT(RCC_APBSMENR1_OFFSET, 1), + SCC_TIM2 = _REG_BIT(RCC_APBSMENR1_OFFSET, 0), + + SCC_ADC = _REG_BIT(RCC_APBSMENR2_OFFSET, 20), + SCC_TIM17 = _REG_BIT(RCC_APBSMENR2_OFFSET, 18), + SCC_TIM16 = _REG_BIT(RCC_APBSMENR2_OFFSET, 17), + SCC_TIM15 = _REG_BIT(RCC_APBSMENR2_OFFSET, 16), + SCC_TIM14 = _REG_BIT(RCC_APBSMENR2_OFFSET, 15), + SCC_USART1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 14), + SCC_SPI1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 12), + SCC_TIM1 = _REG_BIT(RCC_APBSMENR2_OFFSET, 11), + SCC_SYSCFG = _REG_BIT(RCC_APBSMENR2_OFFSET, 0), +}; + +enum rcc_periph_rst { + RST_GPIOF = _REG_BIT(RCC_IOPRSTR_OFFSET, 5), + RST_GPIOE = _REG_BIT(RCC_IOPRSTR_OFFSET, 4), + RST_GPIOD = _REG_BIT(RCC_IOPRSTR_OFFSET, 3), + RST_GPIOC = _REG_BIT(RCC_IOPRSTR_OFFSET, 2), + RST_GPIOB = _REG_BIT(RCC_IOPRSTR_OFFSET, 1), + RST_GPIOA = _REG_BIT(RCC_IOPRSTR_OFFSET, 0), + + RST_RNG = _REG_BIT(RCC_AHBRSTR_OFFSET, 18), + RST_AES = _REG_BIT(RCC_AHBRSTR_OFFSET, 16), + RST_CRC = _REG_BIT(RCC_AHBRSTR_OFFSET, 12), + RST_FLASH = _REG_BIT(RCC_AHBRSTR_OFFSET, 8), + RST_DMA = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), + RST_DMA1 = _REG_BIT(RCC_AHBRSTR_OFFSET, 0), /* Compatibility */ + + RST_LPTIM1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 31), + RST_LPTIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 30), + RST_DAC1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 29), + RST_PWR = _REG_BIT(RCC_APBRSTR1_OFFSET, 28), + RST_DBG = _REG_BIT(RCC_APBRSTR1_OFFSET, 27), + RST_UCPD1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 26), + RST_UCPD2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 25), + RST_CEC = _REG_BIT(RCC_APBRSTR1_OFFSET, 24), + RST_I2C2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 22), + RST_I2C1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 21), + RST_LPUART1 = _REG_BIT(RCC_APBRSTR1_OFFSET, 20), + RST_USART4 = _REG_BIT(RCC_APBRSTR1_OFFSET, 19), + RST_USART3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 18), + RST_USART2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 17), + RST_SPI2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 14), + RST_TIM7 = _REG_BIT(RCC_APBRSTR1_OFFSET, 5), + RST_TIM6 = _REG_BIT(RCC_APBRSTR1_OFFSET, 4), + RST_TIM3 = _REG_BIT(RCC_APBRSTR1_OFFSET, 1), + RST_TIM2 = _REG_BIT(RCC_APBRSTR1_OFFSET, 0), + + RST_ADC = _REG_BIT(RCC_APBRSTR2_OFFSET, 20), + RST_TIM17 = _REG_BIT(RCC_APBRSTR2_OFFSET, 18), + RST_TIM16 = _REG_BIT(RCC_APBRSTR2_OFFSET, 17), + RST_TIM15 = _REG_BIT(RCC_APBRSTR2_OFFSET, 16), + RST_TIM14 = _REG_BIT(RCC_APBRSTR2_OFFSET, 15), + RST_USART1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 14), + RST_SPI1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 12), + RST_TIM1 = _REG_BIT(RCC_APBRSTR2_OFFSET, 11), + RST_SYSCFG = _REG_BIT(RCC_APBRSTR2_OFFSET, 0), +}; + +struct rcc_clock_scale { + enum rcc_osc sysclock_source; + + /* PLL as sysclock source cfg */ + uint8_t pll_source; + uint8_t pll_div; + uint8_t pll_mul; + uint8_t pllp_div; + uint8_t pllq_div; + uint8_t pllr_div; + + /* HSI as sysclock source cfg */ + uint8_t hsisys_div; + + uint8_t hpre; + uint8_t ppre; + uint8_t flash_waitstates; + enum pwr_vos_scale voltage_scale; + uint32_t ahb_frequency; + uint32_t apb_frequency; +}; + +enum rcc_clock { + RCC_CLOCK_CONFIG_LSI_32KHZ, + RCC_CLOCK_CONFIG_HSI_4MHZ, + RCC_CLOCK_CONFIG_HSI_16MHZ, + RCC_CLOCK_CONFIG_HSI_PLL_32MHZ, + RCC_CLOCK_CONFIG_HSI_PLL_64MHZ, + RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ, + RCC_CLOCK_CONFIG_END +}; + +extern const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END]; + +#include <libopencm3/stm32/common/rcc_common_all.h> + +BEGIN_DECLS + +void rcc_osc_on(enum rcc_osc osc); +void rcc_osc_off(enum rcc_osc osc); + +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); + +void rcc_set_sysclk_source(enum rcc_osc osc); +void rcc_wait_for_sysclk_status(enum rcc_osc osc); +enum rcc_osc rcc_system_clock_source(void); + +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, uint32_t pllq, uint32_t pllr); +void rcc_enable_pllp(bool enable); +void rcc_enable_pllq(bool enable); +void rcc_enable_pllr(bool enable); + +void rcc_set_ppre(uint32_t ppre); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_hsisys_div(uint32_t hsidiv); +void rcc_set_mcopre(uint32_t mcopre); + +void rcc_clock_setup(const struct rcc_clock_scale *clock); + +void rcc_set_rng_clk_div(uint32_t rng_div); +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel); + +END_DECLS + +/**@}*/ + +#endif diff --git a/lib/stm32/f3/pwr.c b/include/libopencm3/stm32/g0/rng.h index 3c1a84bd..5df67dba 100644 --- a/lib/stm32/f3/pwr.c +++ b/include/libopencm3/stm32/g0/rng.h @@ -1,26 +1,16 @@ -/** @defgroup pwr_file PWR +/** @defgroup rng_defines RNG Defines * - * @ingroup STM32F3xx + * @ingroup STM32G0xx_defines * - * @brief <b>libopencm3 STM32F3xx Power Control</b> - * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies <ksarkies@internode.on.net> - * - * @date 13 January 2014 + * @brief <b>Defined Constants and Types for the STM32G0xx EXTI Control</b> * * @version 1.0.0 * - * @date 11 July 2013 - * * LGPL License Terms @ref lgpl_license - */ - + * */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net> - * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by * the Free Software Foundation, either version 3 of the License, or @@ -35,6 +25,16 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/pwr.h> +/**@{*/ +#ifndef LIBOPENCM3_RNG_H +#define LIBOPENCM3_RNG_H + +#include <libopencm3/stm32/common/rng_common_v1.h> + +/* --- RNG_CR values ------------------------------------------------------- */ +/** Clock error detection : CED = 0 : Detection Enabled */ +#define RNG_CR_CED (1 << 5) +#endif +/**@}*/ diff --git a/include/libopencm3/stm32/g0/spi.h b/include/libopencm3/stm32/g0/spi.h new file mode 100644 index 00000000..0fbe0765 --- /dev/null +++ b/include/libopencm3/stm32/g0/spi.h @@ -0,0 +1,34 @@ +/** @defgroup spi_defines SPI Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx SPI</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include <libopencm3/stm32/common/spi_common_all.h> +#include <libopencm3/stm32/common/spi_common_v1_frf.h> + +#endif diff --git a/include/libopencm3/stm32/g0/timer.h b/include/libopencm3/stm32/g0/timer.h new file mode 100644 index 00000000..1f102ba8 --- /dev/null +++ b/include/libopencm3/stm32/g0/timer.h @@ -0,0 +1,74 @@ +/** @defgroup timer_defines Timer Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx Timers</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include <libopencm3/stm32/common/timer_common_all.h> + +/**@{*/ + +/* Option Register (TIMx_OR1) */ +#define TIM_OR1(tim_base) MMIO32((tim_base) + 0x50) +#define TIM2_OR1 TIM_OR1(TIM2) +#define TIM3_OR1 TIM_OR1(TIM3) + +/* Alternate Function (TIMx_AF1) */ +#define TIM_AF1(tim_base) MMIO32((tim_base) + 0x60) +#define TIM2_AF1 TIM_AF1(TIM2) +#define TIM3_AF1 TIM_AF1(TIM3) +#define TIM16_AF1 TIM_AF1(TIM16) +#define TIM17_AF1 TIM_AF1(TIM17) + +/* Input Selection Register (TIMx_TISEL) */ +#define TIM_TISEL(tim_base) MMIO32((tim_base) + 0x68) +#define TIM2_TISEL TIM_TISEL(TIM2) +#define TIM3_TISEL TIM_TISEL(TIM3) +#define TIM14_TISEL TIM_TISEL(TIM14) +#define TIM16_TISEL TIM_TISEL(TIM16) +#define TIM17_TISEL TIM_TISEL(TIM17) + +/* --- TIMx_OR1 values ---------------------------------------------------- */ + +/* OCREF_CLR: ocref_clr Source Selection */ +#define TIM_OR1_OCREF_CLR (1 << 0) + +/** @defgroup tim_or1_ocref_clr TIM_OR1_OCREF_CLR Source Selection +@{*/ +#define TIM_OR1_OCREF_CLR_COMP1 (0) +#define TIM_OR1_OCREF_CLR_COMP2 (1) +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ + +#endif diff --git a/include/libopencm3/stm32/g0/usart.h b/include/libopencm3/stm32/g0/usart.h new file mode 100644 index 00000000..2078bf53 --- /dev/null +++ b/include/libopencm3/stm32/g0/usart.h @@ -0,0 +1,48 @@ +/** @defgroup usart_defines USART Defines + * + * @ingroup STM32G0xx_defines + * + * @brief <b>Defined Constants and Types for the STM32G0xx USART</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include <libopencm3/stm32/common/usart_common_all.h> +#include <libopencm3/stm32/common/usart_common_v2.h> + +/**@{*/ + +/** @defgroup usart_reg_base USART register base addresses + * Holds all the U(S)ART peripherals supported. + * @{ + */ +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define USART4 USART4_BASE +#define LPUART1 LPUART1_BASE +/**@}*/ + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/gpio.h b/include/libopencm3/stm32/gpio.h index d20b8cba..14dd418a 100644 --- a/include/libopencm3/stm32/gpio.h +++ b/include/libopencm3/stm32/gpio.h @@ -38,6 +38,10 @@ # include <libopencm3/stm32/l1/gpio.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/gpio.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/gpio.h> +#elif defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/gpio.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/i2c.h b/include/libopencm3/stm32/i2c.h index 112ece2c..880ca49e 100644 --- a/include/libopencm3/stm32/i2c.h +++ b/include/libopencm3/stm32/i2c.h @@ -38,6 +38,8 @@ # include <libopencm3/stm32/l1/i2c.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/i2c.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/i2c.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/iwdg.h b/include/libopencm3/stm32/iwdg.h index 769a84f7..b94b8741 100644 --- a/include/libopencm3/stm32/iwdg.h +++ b/include/libopencm3/stm32/iwdg.h @@ -30,12 +30,16 @@ # include <libopencm3/stm32/f3/iwdg.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/iwdg.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/iwdg.h> #elif defined(STM32L0) # include <libopencm3/stm32/l0/iwdg.h> #elif defined(STM32L1) # include <libopencm3/stm32/l1/iwdg.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/iwdg.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/iwdg.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/l0/dma.h b/include/libopencm3/stm32/l0/dma.h index b39d0610..344f4d4b 100644 --- a/include/libopencm3/stm32/l0/dma.h +++ b/include/libopencm3/stm32/l0/dma.h @@ -32,6 +32,7 @@ #define LIBOPENCM3_DMA_H #include <libopencm3/stm32/common/dma_common_l1f013.h> +#include <libopencm3/stm32/common/dma_common_csel.h> #endif diff --git a/include/libopencm3/stm32/l0/doc-stm32l0.h b/include/libopencm3/stm32/l0/doc-stm32l0.h index 2d01ca01..0813bcd9 100644 --- a/include/libopencm3/stm32/l0/doc-stm32l0.h +++ b/include/libopencm3/stm32/l0/doc-stm32l0.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32L0 +/** @page libopencm3 STM32L0 @version 1.0.0 diff --git a/include/libopencm3/stm32/l0/exti.h b/include/libopencm3/stm32/l0/exti.h index b2af19b2..c1d90156 100644 --- a/include/libopencm3/stm32/l0/exti.h +++ b/include/libopencm3/stm32/l0/exti.h @@ -37,5 +37,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/l0/gpio.h b/include/libopencm3/stm32/l0/gpio.h index a1b48990..da2f420d 100644 --- a/include/libopencm3/stm32/l0/gpio.h +++ b/include/libopencm3/stm32/l0/gpio.h @@ -57,7 +57,8 @@ @{*/ #define GPIO_OSPEED_LOW 0x0 #define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_HIGH 0x3 +#define GPIO_OSPEED_HIGH 0x2 +#define GPIO_OSPEED_VERYHIGH 0x3 /**@}*/ /*****************************************************************************/ diff --git a/include/libopencm3/stm32/l0/lptimer.h b/include/libopencm3/stm32/l0/lptimer.h new file mode 100644 index 00000000..e6d99d8c --- /dev/null +++ b/include/libopencm3/stm32/l0/lptimer.h @@ -0,0 +1,46 @@ +/** @defgroup lptimer_defines LPTIM Defines + * + * @ingroup STM32L0xx_defines + * + * @brief <b>libopencm3 Defined Constants and Types for the STM32L0xx Low Power Timer</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_LPTIMER_H +#define LIBOPENCM3_LPTIMER_H +/**@{*/ + +#include <libopencm3/stm32/common/lptimer_common_all.h> + +/** @defgroup lptim_reg_base Low Power Timer register base addresses +@{*/ +#define LPTIM1 LPTIM1_BASE +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index ace255b1..59194425 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -142,14 +142,17 @@ #define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO_MASK 0xf -/* PLL Output division selection */ +/** @defgroup rcc_cfgr_pdf PLLDIV PLL division factor + @{*/ #define RCC_CFGR_PLLDIV_DIV2 0x1 #define RCC_CFGR_PLLDIV_DIV3 0x2 #define RCC_CFGR_PLLDIV_DIV4 0x3 +/**@}*/ #define RCC_CFGR_PLLDIV_SHIFT 22 #define RCC_CFGR_PLLDIV_MASK 0x3 -/* PLLMUL: PLL multiplication factor */ +/** @defgroup rcc_cfgr_pmf PLLMUL PLL multiplication factor + @{*/ #define RCC_CFGR_PLLMUL_MUL3 0x0 #define RCC_CFGR_PLLMUL_MUL4 0x1 #define RCC_CFGR_PLLMUL_MUL6 0x2 @@ -159,6 +162,7 @@ #define RCC_CFGR_PLLMUL_MUL24 0x6 #define RCC_CFGR_PLLMUL_MUL32 0x7 #define RCC_CFGR_PLLMUL_MUL48 0x8 +/**@}*/ #define RCC_CFGR_PLLMUL_SHIFT 18 #define RCC_CFGR_PLLMUL_MASK 0xf @@ -171,24 +175,32 @@ #define RCC_CFGR_STOPWUCK_HSI16 (1<<15) /* PPRE2: APB high-speed prescaler (APB2) */ +/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors +@{*/ #define RCC_CFGR_PPRE2_NODIV 0x0 #define RCC_CFGR_PPRE2_DIV2 0x4 #define RCC_CFGR_PPRE2_DIV4 0x5 #define RCC_CFGR_PPRE2_DIV8 0x6 #define RCC_CFGR_PPRE2_DIV16 0x7 +/**@}*/ #define RCC_CFGR_PPRE2_MASK 0x7 #define RCC_CFGR_PPRE2_SHIFT 11 /* PPRE1: APB low-speed prescaler (APB1) */ +/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors +@{*/ #define RCC_CFGR_PPRE1_NODIV 0x0 #define RCC_CFGR_PPRE1_DIV2 0x4 #define RCC_CFGR_PPRE1_DIV4 0x5 #define RCC_CFGR_PPRE1_DIV8 0x6 #define RCC_CFGR_PPRE1_DIV16 0x7 +/**@}*/ #define RCC_CFGR_PPRE1_MASK 0x7 #define RCC_CFGR_PPRE1_SHIFT 8 /* HPRE: AHB prescaler */ +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors +@{*/ #define RCC_CFGR_HPRE_NODIV 0x0 #define RCC_CFGR_HPRE_DIV2 0x8 #define RCC_CFGR_HPRE_DIV4 0x9 @@ -198,6 +210,7 @@ #define RCC_CFGR_HPRE_DIV128 0xd #define RCC_CFGR_HPRE_DIV256 0xe #define RCC_CFGR_HPRE_DIV512 0xf +/**@}*/ #define RCC_CFGR_HPRE_MASK 0xf #define RCC_CFGR_HPRE_SHIFT 4 @@ -262,17 +275,18 @@ #define RCC_IOPPRSTR_IOPBRST (1<<1) #define RCC_IOPPRSTR_IOPARST (1<<0) -/* --- RCC_AHBRSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values +@{*/ #define RCC_AHBRSTR_CRYPRST (1 << 24) #define RCC_AHBRSTR_RNGRST (1 << 20) #define RCC_AHBRSTR_TSCRST (1 << 16) #define RCC_AHBRSTR_CRCRST (1 << 12) #define RCC_AHBRSTR_MIFRST (1 << 8) #define RCC_AHBRSTR_DMARST (1 << 0) +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_DBGRST (1 << 22) #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) @@ -280,9 +294,10 @@ #define RCC_APB2RSTR_TIM22RST (1 << 5) #define RCC_APB2RSTR_TIM21RST (1 << 2) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@{*/ #define RCC_APB1RSTR_LPTIM1RST (1 << 31) #define RCC_APB1RSTR_I2C3RST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) @@ -302,6 +317,7 @@ #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ /* --- RCC_IOPENR - GPIO clock enable register */ @@ -312,11 +328,7 @@ #define RCC_IOPENR_IOPBEN (1<<1) #define RCC_IOPENR_IOPAEN (1<<0) -/* --- RCC_AHBENR values --------------------------------------------------- */ - -/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values -@ingroup STM32L0xx_rcc_defines - +/** @defgroup rcc_ahbenr_en RCC_APHBENR enable values @{*/ #define RCC_AHBENR_CRYPEN (1 << 24) #define RCC_AHBENR_RNGEN (1 << 20) @@ -324,13 +336,9 @@ #define RCC_AHBENR_CRCEN (1 << 12) #define RCC_AHBENR_MIFEN (1 << 8) #define RCC_AHBENR_DMAEN (1 << 0) -/*@}*/ - -/* --- RCC_APB2ENR values -------------------------------------------------- */ - -/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values -@ingroup STM32L0xx_rcc_defines +/**@}*/ +/** @defgroup rcc_apb2enr_en RCC_APPB2ENR enable values @{*/ #define RCC_APB2ENR_DBGEN (1 << 22) #define RCC_APB2ENR_USART1EN (1 << 14) @@ -340,13 +348,9 @@ #define RCC_APB2ENR_TIM22EN (1 << 5) #define RCC_APB2ENR_TIM21EN (1 << 2) #define RCC_APB2ENR_SYSCFGEN (1 << 0) -/*@}*/ - -/* --- RCC_APB1ENR values -------------------------------------------------- */ +/**@}*/ /** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values -@ingroup STM32L0xx_rcc_defines - @{*/ #define RCC_APB1ENR_LPTIM1EN (1 << 31) #define RCC_APB1ENR_DACEN (1 << 29) @@ -366,7 +370,7 @@ #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) -/*@}*/ +/**@}*/ /* --- RCC_IOPSMENR - GPIO Clock enable in sleep mode */ @@ -693,6 +697,15 @@ void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); void rcc_clock_setup_pll(const struct rcc_clock_scale *clock); +void rcc_set_msi_range(uint32_t msi_range); + +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel); + +void rcc_set_lptim1_sel(uint32_t lptim1_sel); +void rcc_set_lpuart1_sel(uint32_t lpupart1_sel); +void rcc_set_usart1_sel(uint32_t usart1_sel); +void rcc_set_usart2_sel(uint32_t usart2_sel); + END_DECLS /**@}*/ diff --git a/include/libopencm3/stm32/l0/syscfg.h b/include/libopencm3/stm32/l0/syscfg.h index 1ae0a947..767ddf44 100644 --- a/include/libopencm3/stm32/l0/syscfg.h +++ b/include/libopencm3/stm32/l0/syscfg.h @@ -111,6 +111,7 @@ /* SYSCFG_EXTICR Values -- --------------------------------------------------*/ +#define SYSCFG_EXTICR_FIELDSIZE 4 #define SYSCFG_EXTICR_GPIOA 0 #define SYSCFG_EXTICR_GPIOB 1 #define SYSCFG_EXTICR_GPIOC 2 diff --git a/include/libopencm3/stm32/l0/timer.h b/include/libopencm3/stm32/l0/timer.h index c2ed35a8..98772811 100644 --- a/include/libopencm3/stm32/l0/timer.h +++ b/include/libopencm3/stm32/l0/timer.h @@ -37,7 +37,9 @@ LGPL License Terms @ref lgpl_license #include <libopencm3/stm32/common/timer_common_all.h> -/* Timer 2/21/22 option register (TIMx_OR) */ +/**@{*/ + +/** Timer 2/21/22 option register (TIMx_OR) */ #define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) @@ -94,118 +96,8 @@ LGPL License Terms @ref lgpl_license #define TIM22_OR_TI1_RMP_COMP2_OUT (1 << TIM22_OR_TI1_RMP_SHIFT) #define TIM22_OR_TI1_RMP_COMP1_OUT (2 << TIM22_OR_TI1_RMP_SHIFT) -/* --- LPTIM (low power timer) ------------------------------------------- */ - -#define LPTIM_ISR(tim_base) MMIO32((tim_base) + 0x00) -#define LPTIM_ICR(tim_base) MMIO32((tim_base) + 0x04) -#define LPTIM_IER(tim_base) MMIO32((tim_base) + 0x08) -#define LPTIM_CFGR(tim_base) MMIO32((tim_base) + 0x0C) -#define LPTIM_CR(tim_base) MMIO32((tim_base) + 0x10) -#define LPTIM_CMP(tim_base) MMIO32((tim_base) + 0x14) -#define LPTIM_ARR(tim_base) MMIO32((tim_base) + 0x18) -#define LPTIM_CNT(tim_base) MMIO32((tim_base) + 0x1C) - -#define LPTIM1_ISR LPTIM_ISR(LPTIM1_BASE) -#define LPTIM1_ICR LPTIM_ICR(LPTIM1_BASE) -#define LPTIM1_IER LPTIM_IER(LPTIM1_BASE) -#define LPTIM1_CFGR LPTIM_CFGR(LPTIM1_BASE) -#define LPTIM1_CR LPTIM_CR(LPTIM1_BASE) -#define LPTIM1_CMP LPTIM_CMP(LPTIM1_BASE) -#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE) -#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE) - -#define LPTIM_ISR_CMPM (1 << 0) -#define LPTIM_ISR_ARRM (1 << 1) -#define LPTIM_ISR_EXTTRIG (1 << 2) -#define LPTIM_ISR_CMPOK (1 << 3) -#define LPTIM_ISR_ARROK (1 << 4) -#define LPTIM_ISR_UP (1 << 5) -#define LPTIM_ISR_DOWN (1 << 6) - -#define LPTIM_ICR_CMPMCF (1 << 0) -#define LPTIM_ICR_ARRMCF (1 << 1) -#define LPTIM_ICR_EXTTRIGCF (1 << 2) -#define LPTIM_ICR_CMPOKCF (1 << 3) -#define LPTIM_ICR_ARROKCF (1 << 4) -#define LPTIM_ICR_UPCF (1 << 5) -#define LPTIM_ICR_DOWNCF (1 << 6) - -#define LPTIM_IER_CMPMIE (1 << 0) -#define LPTIM_IER_ARRMIE (1 << 1) -#define LPTIM_IER_EXTTRIGIE (1 << 2) -#define LPTIM_IER_CMPOKIE (1 << 3) -#define LPTIM_IER_ARROKIE (1 << 4) -#define LPTIM_IER_UPIE (1 << 5) -#define LPTIM_IER_DOWNIE (1 << 6) - -#define LPTIM_CFGR_CKSEL (1 << 0) - -#define LPTIM_CFGR_CKPOL_SHIFT 1 -#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT) -#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT) - -#define LPTIM_CFGR_CKFLT_SHIFT 3 -#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT) -#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT) - -#define LPTIM_CFGR_TRGFLT_SHIFT 6 -#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT) -#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT) - -#define LPTIM_CFGR_PRESC_SHIFT 9 -#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_8 (3 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_16 (4 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT) -#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT) - -#define LPTIM_CFGR_TRIGSEL_SHIFT 13 -#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG3 (3 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG4 (4 << LPTIM_CFGR_TRIGSEL_SHIFT) -/* 5 is reserved */ -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT) -#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT) - -#define LPTIM_CFGR_TRIGEN_SHIFT 17 -#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT) -#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT) - -#define LPTIM_CFGR_TIMOUT (1 << 19) - -#define LPTIM_CFGR_WAVE (1 << 20) - -#define LPTIM_CFGR_WAVPOL (1 << 21) - -#define LPTIM_CFGR_PRELOAD (1 << 22) - -#define LPTIM_CFGR_COUNTMODE (1 << 23) - -#define LPTIM_CFGR_ENC (1 << 24) - -#define LPTIM_CR_ENABLE (1 << 0) - -#define LPTIM_CR_SNGSTRT (1 << 1) - -#define LPTIM_CR_CNTSTRT (1 << 2) +/**@}*/ #endif + +/**@}*/ diff --git a/include/libopencm3/stm32/l0/usart.h b/include/libopencm3/stm32/l0/usart.h index d3777707..6ab49067 100644 --- a/include/libopencm3/stm32/l0/usart.h +++ b/include/libopencm3/stm32/l0/usart.h @@ -30,8 +30,9 @@ #include <libopencm3/stm32/common/usart_common_all.h> #include <libopencm3/stm32/common/usart_common_v2.h> +/**@{*/ + /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ @@ -46,4 +47,5 @@ BEGIN_DECLS END_DECLS +/**@}*/ #endif diff --git a/include/libopencm3/stm32/l1/adc.h b/include/libopencm3/stm32/l1/adc.h index 93659400..fe2fa588 100644 --- a/include/libopencm3/stm32/l1/adc.h +++ b/include/libopencm3/stm32/l1/adc.h @@ -33,7 +33,7 @@ LGPL License Terms @ref lgpl_license #ifndef LIBOPENCM3_ADC_H #define LIBOPENCM3_ADC_H -#include <libopencm3/stm32/common/adc_common_v1.h> +#include <libopencm3/stm32/common/adc_common_v1_multi.h> #define ADC_MAX_REGULAR_SEQUENCE 28 /* 26 in L/M, but 32 in two banks for M+/H density */ @@ -88,9 +88,6 @@ LGPL License Terms @ref lgpl_license #define ADC_SMPR0(block) MMIO32((block) + 0x5c) #define ADC1_SMPR0 ADC_SMPR0(ADC1) -#define ADC_CSR MMIO32(ADC1 + 0x300) -#define ADC_CCR MMIO32(ADC1 + 0x304) - /** @defgroup adc_channel ADC Channel Numbers * @ingroup adc_defines * @@ -115,49 +112,16 @@ LGPL License Terms @ref lgpl_license /* ADONS:*//** ADC ON status */ #define ADC_SR_ADONS (1 << 6) -/* OVR:*//** Overrun */ -#define ADC_SR_OVR (1 << 5) /**@}*/ /* --- ADC_CR1 values ------------------------------------------------------- */ -#define ADC_CR1_OVRIE (1 << 28) -/****************************************************************************/ -/** @defgroup adc_cr1_res ADC Resolution. -@ingroup adc_defines -@{*/ -#define ADC_CR1_RES_12_BIT 0 -#define ADC_CR1_RES_10_BIT 1 -#define ADC_CR1_RES_8_BIT 2 -#define ADC_CR1_RES_6_BIT 3 -/**@}*/ -#define ADC_CR1_RES_MASK (0x3) -#define ADC_CR1_RES_SHIFT 24 #define ADC_CR1_PDI (1 << 17) #define ADC_CR1_PDD (1 << 16) #define ADC_CR1_AWDCH_MAX 26 -/* --- ADC_CR2 values ------------------------------------------------------- */ -/* SWSTART: */ /** Start conversion of regular channels. */ -#define ADC_CR2_SWSTART (1 << 30) - -/* EXTEN[1:0]: External trigger enable for regular channels. */ -/****************************************************************************/ -#define ADC_CR2_EXTEN_SHIFT 28 -#define ADC_CR2_EXTEN_MASK (0x3 << ADC_CR2_EXTEN_SHIFT) -/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity -@ingroup adc_defines -@{*/ -#define ADC_CR2_EXTEN_DISABLED (0x0 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << ADC_CR2_EXTEN_SHIFT) -#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << ADC_CR2_EXTEN_SHIFT) -/**@}*/ - /* EXTSEL[3:0]: External event selection for regular group. */ /****************************************************************************/ -#define ADC_CR2_EXTSEL_SHIFT 24 -#define ADC_CR2_EXTSEL_MASK (0xf << ADC_CR2_EXTSEL_SHIFT) /** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group @ingroup adc_defines @@ -177,27 +141,9 @@ LGPL License Terms @ref lgpl_license #define ADC_CR2_EXTSEL_EXTI11 (15 << ADC_CR2_EXTSEL_SHIFT) /**@}*/ -#define ADC_CR2_JSWSTART (1 << 22) -/* JEXTEN[1:0]: External trigger enable for injected channels. */ -/****************************************************************************/ -#define ADC_CR2_JEXTEN_SHIFT 20 -#define ADC_CR2_JEXTEN_MASK (0x3 << ADC_CR2_JEXTEN_SHIFT) -/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity -@ingroup adc_defines -@{*/ -#define ADC_CR2_JEXTEN_DISABLED (0x0 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << ADC_CR2_JEXTEN_SHIFT) -#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << ADC_CR2_JEXTEN_SHIFT) -/**@}*/ +/* FIXME - JEXTSEL values here */ -/* FIXME - add the values here */ -#define ADC_CR2_JEXTSEL_SHIFT 16 -#define ADC_CR2_JEXTSEL_MASK (0xf << ADC_CR2_JEXTSEL_SHIFT) - -#define ADC_CR2_EOCS (1 << 10) -#define ADC_CR2_DDS (1 << 9) /* FIXME- add the values here */ #define ADC_CR2_DELS_SHIFT 4 #define ADC_CR2_DELS_MASK 0x7 @@ -227,16 +173,17 @@ LGPL License Terms @ref lgpl_license #define ADC_SQR_MASK 0x1f #define ADC_SQR_MAX_CHANNELS_REGULAR 28 /* m+/h only, otherwise 27 */ -#define ADC_CCR_TSVREFE (1 << 23) +/** @defgroup adc_ccr_adcpre ADC Prescale +@ingroup adc_defines +@{*/ +#define ADC_CCR_ADCPRE_BY1 (0x0 << 16) +#define ADC_CCR_ADCPRE_BY2 (0x1 << 16) +#define ADC_CCR_ADCPRE_BY4 (0x2 << 16) +/**@}*/ +#define ADC_CCR_ADCPRE_MASK (0x3 << 16) +#define ADC_CCR_ADCPRE_SHIFT 16 BEGIN_DECLS - /* L1 specific, or not fully unified adc routines */ -void adc_enable_temperature_sensor(void); -void adc_disable_temperature_sensor(void); -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity); -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity); END_DECLS diff --git a/include/libopencm3/stm32/l1/doc-stm32l1.h b/include/libopencm3/stm32/l1/doc-stm32l1.h index 7f7c0669..fddc501f 100644 --- a/include/libopencm3/stm32/l1/doc-stm32l1.h +++ b/include/libopencm3/stm32/l1/doc-stm32l1.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32L1 +/** @page libopencm3 STM32L1 @version 1.0.0 diff --git a/include/libopencm3/stm32/l1/exti.h b/include/libopencm3/stm32/l1/exti.h index 0f309537..81915766 100644 --- a/include/libopencm3/stm32/l1/exti.h +++ b/include/libopencm3/stm32/l1/exti.h @@ -37,5 +37,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index 8933555c..6540c6a6 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -243,7 +243,8 @@ #define RCC_CIR_LSERDYF (1 << 1) #define RCC_CIR_LSIRDYF (1 << 0) -/* --- RCC_AHBRSTR values ------------------------------------------------- */ +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values values +@{*/ #define RCC_AHBRSTR_DMA1RST (1 << 24) #define RCC_AHBRSTR_FLITFRST (1 << 15) #define RCC_AHBRSTR_CRCRST (1 << 12) @@ -253,9 +254,10 @@ #define RCC_AHBRSTR_GPIOCRST (1 << 2) #define RCC_AHBRSTR_GPIOBRST (1 << 1) #define RCC_AHBRSTR_GPIOARST (1 << 0) +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values values +@{*/ #define RCC_APB2RSTR_USART1RST (1 << 14) #define RCC_APB2RSTR_SPI1RST (1 << 12) #define RCC_APB2RSTR_ADC1RST (1 << 9) @@ -263,9 +265,10 @@ #define RCC_APB2RSTR_TIM10RST (1 << 3) #define RCC_APB2RSTR_TIM9RST (1 << 2) #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values values +@{*/ #define RCC_APB1RSTR_COMPRST (1 << 31) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) @@ -283,6 +286,7 @@ #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ /* --- RCC_AHBENR values --------------------------------------------------- */ diff --git a/include/libopencm3/stm32/l1/timer.h b/include/libopencm3/stm32/l1/timer.h index f2e3cd6d..faef4346 100644 --- a/include/libopencm3/stm32/l1/timer.h +++ b/include/libopencm3/stm32/l1/timer.h @@ -37,6 +37,8 @@ LGPL License Terms @ref lgpl_license #include <libopencm3/stm32/common/timer_common_all.h> +/**@{*/ + /* * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: * CNT, ARR, CCR1, CCR2, CCR3, CCR4 @@ -51,25 +53,20 @@ LGPL License Terms @ref lgpl_license /* ITR1_RMP */ /****************************************************************************/ -/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal -Trigger 1 Remap -@ingroup timer_defines - +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Internal Trigger 1 Remap @{*/ /** Internal Trigger 1 remapped to timer 10 output compare */ #define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0) /** Internal Trigger 1 remapped to timer 5 TGO */ #define TIM2_OR_ITR1_RMP_TIM5_TGO (0x1 << 0) /**@}*/ -#define TIM3_OR_ITR1_RMP_MASK (0x1 << 0) +#define TIM2_OR_ITR1_RMP_MASK (0x1 << 0) /* --- TIMx_OR values ---------------------------------------------------- */ /* ITR2_RMP */ /****************************************************************************/ -/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap -@ingroup timer_defines - +/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Internal Trigger 2 Remap @{*/ /** Internal Trigger 1 remapped to timer 11 output compare */ #define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0) @@ -86,4 +83,6 @@ void timer_set_option(uint32_t timer_peripheral, uint32_t option); END_DECLS +/**@}*/ + #endif diff --git a/lib/stm32/f2/dac.c b/include/libopencm3/stm32/l4/dac.h index 635e142b..10b275a7 100644 --- a/lib/stm32/f2/dac.c +++ b/include/libopencm3/stm32/l4/dac.h @@ -1,15 +1,15 @@ -/** @defgroup dac_file DAC +/** @defgroup dac_defines DAC Defines -@ingroup STM32F2xx +@brief <b>Defined Constants and Types for the STM32L4xx DAC</b> -@brief <b>libopencm3 STM32F2xx DAC</b> +@ingroup STM32L4xx_defines @version 1.0.0 -@date 18 August 2012 +@date 8 June 2019 LGPL License Terms @ref lgpl_license -*/ + */ /* * This file is part of the libopencm3 project. @@ -28,4 +28,10 @@ LGPL License Terms @ref lgpl_license * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/dac.h> +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include <libopencm3/stm32/common/dac_common_all.h> + +#endif + diff --git a/include/libopencm3/stm32/l4/dma.h b/include/libopencm3/stm32/l4/dma.h index 9b1a180e..d8485a43 100644 --- a/include/libopencm3/stm32/l4/dma.h +++ b/include/libopencm3/stm32/l4/dma.h @@ -33,5 +33,6 @@ #define LIBOPENCM3_DMA_H #include <libopencm3/stm32/common/dma_common_l1f013.h> +#include <libopencm3/stm32/common/dma_common_csel.h> #endif diff --git a/include/libopencm3/stm32/l4/doc-stm32l4.h b/include/libopencm3/stm32/l4/doc-stm32l4.h index e095ccb5..c4910349 100644 --- a/include/libopencm3/stm32/l4/doc-stm32l4.h +++ b/include/libopencm3/stm32/l4/doc-stm32l4.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 STM32L4 +/** @page libopencm3 STM32L4 @version 1.0.0 diff --git a/include/libopencm3/stm32/l4/exti.h b/include/libopencm3/stm32/l4/exti.h index 3dd2c76c..7ba30b2c 100644 --- a/include/libopencm3/stm32/l4/exti.h +++ b/include/libopencm3/stm32/l4/exti.h @@ -1,3 +1,13 @@ +/** @defgroup exti_defines EXTI Defines + * + * @ingroup STM32L4xx_defines + * + * @brief <b>Defined Constants and Types for the STM32L4xx EXTI Control</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + **/ /* * This file is part of the libopencm3 project. * @@ -19,5 +29,6 @@ #define LIBOPENCM3_EXTI_H #include <libopencm3/stm32/common/exti_common_all.h> +#include <libopencm3/stm32/common/exti_common_v1.h> #endif diff --git a/include/libopencm3/stm32/l4/flash.h b/include/libopencm3/stm32/l4/flash.h index 5f1dddef..fb028a38 100644 --- a/include/libopencm3/stm32/l4/flash.h +++ b/include/libopencm3/stm32/l4/flash.h @@ -228,7 +228,7 @@ void flash_clear_size_flag(void); void flash_clear_pgaerr_flag(void); void flash_clear_wrperr_flag(void); void flash_lock_option_bytes(void); -void flash_program_word(uint32_t address, uint32_t data); +void flash_program_double_word(uint32_t address, uint64_t data); void flash_program(uint32_t address, uint8_t *data, uint32_t len); void flash_erase_page(uint32_t page); void flash_erase_all_pages(void); diff --git a/include/libopencm3/stm32/l4/gpio.h b/include/libopencm3/stm32/l4/gpio.h index 15dc7b11..3f70b18c 100644 --- a/include/libopencm3/stm32/l4/gpio.h +++ b/include/libopencm3/stm32/l4/gpio.h @@ -72,8 +72,8 @@ @{*/ #define GPIO_OSPEED_LOW 0x0 #define GPIO_OSPEED_MED 0x1 -#define GPIO_OSPEED_FAST 0x2 -#define GPIO_OSPEED_HIGH 0x3 +#define GPIO_OSPEED_HIGH 0x2 +#define GPIO_OSPEED_VERYHIGH 0x3 /**@}*/ /*****************************************************************************/ diff --git a/include/libopencm3/stm32/l4/irq.json b/include/libopencm3/stm32/l4/irq.json index 2e575ac4..85d93722 100644 --- a/include/libopencm3/stm32/l4/irq.json +++ b/include/libopencm3/stm32/l4/irq.json @@ -81,7 +81,16 @@ "lcd", "aes", "rng", - "fpu" + "fpu", + "hash_crs", + "i2c4_ev", + "i2c4_er", + "dcmi", + "can2_tx", + "can2_rx0", + "can2_rx1", + "can2_sce", + "dma2d" ], "partname_humanreadable": "STM32 L4 series", "partname_doxygen": "STM32L4", diff --git a/include/libopencm3/stm32/l4/lptimer.h b/include/libopencm3/stm32/l4/lptimer.h new file mode 100644 index 00000000..1dc78c9d --- /dev/null +++ b/include/libopencm3/stm32/l4/lptimer.h @@ -0,0 +1,47 @@ +/** @defgroup lptimer_defines LPTIM Defines + * + * @ingroup STM32L4xx_defines + * + * @brief <b>libopencm3 Defined Constants and Types for the STM32L4xx Low Power Timer</b> + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_LPTIMER_H +#define LIBOPENCM3_LPTIMER_H +/**@{*/ + +#include <libopencm3/stm32/common/lptimer_common_all.h> + +/** @defgroup lptim_reg_base Low Power Timer register base addresses +@{*/ +#define LPTIM1 LPTIM1_BASE +#define LPTIM2 LPTIM2_BASE +/**@}*/ + +BEGIN_DECLS + +END_DECLS + +/**@}*/ +#endif diff --git a/include/libopencm3/stm32/l4/memorymap.h b/include/libopencm3/stm32/l4/memorymap.h index d8e12e53..baaa32f5 100644 --- a/include/libopencm3/stm32/l4/memorymap.h +++ b/include/libopencm3/stm32/l4/memorymap.h @@ -57,11 +57,11 @@ #define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) #define I2C3_BASE (PERIPH_BASE_APB1 + 0x5c00) #define CRS_BASE (PERIPH_BASE_APB1 + 0x6000) -#define CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x6800) #define USB_PMA_BASE (PERIPH_BASE_APB1 + 0x6c00) #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) -#define DAC1_BASE (PERIPH_BASE_APB1 + 0x7400) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) #define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7800) #define LPTIM1_BASE (PERIPH_BASE_APB1 + 0x7c00) #define LPUART1_BASE (PERIPH_BASE_APB1 + 0x8000) diff --git a/include/libopencm3/stm32/l4/pwr.h b/include/libopencm3/stm32/l4/pwr.h index f4d2b911..04919327 100644 --- a/include/libopencm3/stm32/l4/pwr.h +++ b/include/libopencm3/stm32/l4/pwr.h @@ -170,6 +170,8 @@ enum pwr_vos_scale { BEGIN_DECLS void pwr_set_vos_scale(enum pwr_vos_scale scale); +void pwr_disable_backup_domain_write_protect(void); +void pwr_enable_backup_domain_write_protect(void); END_DECLS diff --git a/include/libopencm3/stm32/l4/rcc.h b/include/libopencm3/stm32/l4/rcc.h index f49ea7e2..98ec575e 100644 --- a/include/libopencm3/stm32/l4/rcc.h +++ b/include/libopencm3/stm32/l4/rcc.h @@ -320,16 +320,19 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_CICR_LSERDYC (1 << 1) #define RCC_CICR_LSIRDYC (1 << 0) -/* --- RCC_AHB1RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahbrstr_rst RCC_AHBxRSTR reset values (full set) +@{*/ +/** @defgroup rcc_ahb1rstr_rst RCC_AHB1RSTR reset values +@{*/ #define RCC_AHB1RSTR_TSCRST (1 << 16) #define RCC_AHB1RSTR_CRCRST (1 << 12) #define RCC_AHB1RSTR_FLASHRST (1 << 8) #define RCC_AHB1RSTR_DMA2RST (1 << 1) #define RCC_AHB1RSTR_DMA1RST (1 << 0) +/**@}*/ -/* --- RCC_AHB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_ahb2rstr_rst RCC_AHB2RSTR reset values +@{*/ #define RCC_AHB2RSTR_RNGRST (1 << 18) #define RCC_AHB2RSTR_AESRST (1 << 16) #define RCC_AHB2RSTR_ADCRST (1 << 13) @@ -343,13 +346,19 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_AHB2RSTR_GPIOBRST (1 << 1) #define RCC_AHB2RSTR_GPIOARST (1 << 0) -/* --- RCC_AHB3RSTR values ------------------------------------------------- */ +/**@}*/ +/** @defgroup rcc_ahb3rstr_rst RCC_AHB3RSTR reset values +@{*/ #define RCC_AHB3RSTR_QSPIRST (1 << 8) #define RCC_AHB3RSTR_FMCRST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB1RSTR1 values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTRx reset values (full set) +@{*/ +/** @defgroup rcc_apb1rstr1_rst RCC_APB1RSTR1 reset values +@{*/ #define RCC_APB1RSTR1_LPTIM1RST (1 << 31) #define RCC_APB1RSTR1_OPAMPRST (1 << 30) #define RCC_APB1RSTR1_DAC1RST (1 << 29) @@ -371,15 +380,18 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_APB1RSTR1_TIM4RST (1 << 2) #define RCC_APB1RSTR1_TIM3RST (1 << 1) #define RCC_APB1RSTR1_TIM2RST (1 << 0) +/**@}*/ -/* --- RCC_APB1RSTR2 values ------------------------------------------------- */ - +/** @defgroup rcc_apb1rstr2_rst RCC_APB1RSTR2 reset values +@{*/ #define RCC_APB1RSTR2_LPTIM2RST (1 << 5) #define RCC_APB1RSTR2_SWPMI1RST (1 << 2) #define RCC_APB1RSTR2_LPUART1RST (1 << 0) +/**@}*/ +/**@}*/ -/* --- RCC_APB2RSTR values ------------------------------------------------- */ - +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@{*/ #define RCC_APB2RSTR_DFSDMRST (1 << 24) #define RCC_APB2RSTR_SAI2RST (1 << 22) #define RCC_APB2RSTR_SAI1RST (1 << 21) @@ -393,9 +405,12 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_APB2RSTR_SDMMC1RST (1 << 10) /* Suspect FW_RST at bit 7 to match APB2_ENR ... */ #define RCC_APB2RSTR_SYSCFGRST (1 << 0) +/**@}*/ /* --- RCC_AHB1ENR values --------------------------------------------------- */ +/** @defgroup rcc_ahbenr_en RCC_AHBxENR enable values (full set) + *@{*/ /** @defgroup rcc_ahb1enr_en RCC_AHB1ENR enable values @ingroup STM32L4xx_rcc_defines @@ -437,9 +452,12 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_AHB3ENR_FMCEN (1 << 0) /*@}*/ +/**@}*/ /* --- RCC_APB1ENR1 values -------------------------------------------------- */ +/** @defgroup rcc_apb1enr_en RCC_APB1ENRx enable values (full set) + *@{*/ /** @defgroup rcc_apb1enr1_en RCC_APB1ENR1 enable values @ingroup STM32L4xx_rcc_defines @@ -477,6 +495,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz, #define RCC_APB1ENR2_SWPMI1EN (1 << 2) #define RCC_APB1ENR2_LPUART1EN (1 << 0) /*@}*/ +/*@}*/ /* --- RCC_APB2ENR values -------------------------------------------------- */ @@ -962,6 +981,11 @@ void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pl uint32_t rcc_system_clock_source(void); void rcc_set_msi_range(uint32_t msi_range); void rcc_set_msi_range_standby(uint32_t msi_range); +void rcc_pll_output_enable(uint32_t pllout); +void rcc_set_clock48_source(uint32_t clksel); +void rcc_enable_rtc_clock(void); +void rcc_disable_rtc_clock(void); +void rcc_set_rtc_clock_source(enum rcc_osc clk); END_DECLS diff --git a/include/libopencm3/stm32/l4/syscfg.h b/include/libopencm3/stm32/l4/syscfg.h index 934d7ac5..d11510b6 100644 --- a/include/libopencm3/stm32/l4/syscfg.h +++ b/include/libopencm3/stm32/l4/syscfg.h @@ -81,6 +81,7 @@ /* --- SYSCFG_EXTICR Values -------------------------------------------------*/ +#define SYSCFG_EXTICR_FIELDSIZE 4 #define SYSCFG_EXTICR_GPIOA 0 #define SYSCFG_EXTICR_GPIOB 1 #define SYSCFG_EXTICR_GPIOC 2 diff --git a/include/libopencm3/stm32/l4/usart.h b/include/libopencm3/stm32/l4/usart.h index ab7efd63..08d8a86b 100644 --- a/include/libopencm3/stm32/l4/usart.h +++ b/include/libopencm3/stm32/l4/usart.h @@ -31,7 +31,6 @@ #include <libopencm3/stm32/common/usart_common_v2.h> /** @defgroup usart_reg_base USART register base addresses - * @ingroup STM32F_usart_defines * Holds all the U(S)ART peripherals supported. * @{ */ diff --git a/lib/stm32/f2/timer.c b/include/libopencm3/stm32/lptimer.h index 6600705a..f2c6b972 100644 --- a/lib/stm32/f2/timer.c +++ b/include/libopencm3/stm32/lptimer.h @@ -1,25 +1,9 @@ -/* This file is used for documentation purposes. It does not need -to be compiled. All source code is in the common area. -If there is any device specific code required it can be included here, -in which case this file must be added to the compile list. */ - -/** @defgroup timer_file Timers - -@ingroup STM32F2xx - -@brief <b>libopencm3 STM32F2xx Timers</b> - -@version 1.0.0 - -@date 18 August 2012 - -*/ +/* This provides unification of code over STM32 subfamilies */ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org> - * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -35,4 +19,20 @@ in which case this file must be added to the compile list. */ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/timer.h> +#include <libopencm3/cm3/common.h> +#include <libopencm3/stm32/memorymap.h> + +#if defined(STM32F4) +# include <libopencm3/stm32/f4/lptimer.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/lptimer.h> +#elif defined(STM32L0) +# include <libopencm3/stm32/l0/lptimer.h> +#elif defined(STM32L4) +# include <libopencm3/stm32/l4/lptimer.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/lptimer.h> +#else +# error "stm32 family not defined." +#endif + diff --git a/include/libopencm3/stm32/ltdc.h b/include/libopencm3/stm32/ltdc.h index 71521c53..e2c5c1c5 100644 --- a/include/libopencm3/stm32/ltdc.h +++ b/include/libopencm3/stm32/ltdc.h @@ -22,6 +22,8 @@ #if defined(STM32F4) # include <libopencm3/stm32/f4/ltdc.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/ltdc.h> #else # error "LCD-TFT only defined for STM32F4" #endif diff --git a/include/libopencm3/stm32/memorymap.h b/include/libopencm3/stm32/memorymap.h index ecf41281..a5b64138 100644 --- a/include/libopencm3/stm32/memorymap.h +++ b/include/libopencm3/stm32/memorymap.h @@ -38,6 +38,10 @@ # include <libopencm3/stm32/l1/memorymap.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/memorymap.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/memorymap.h> +#elif defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/memorymap.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/pwr.h b/include/libopencm3/stm32/pwr.h index 2b21be58..066dec65 100644 --- a/include/libopencm3/stm32/pwr.h +++ b/include/libopencm3/stm32/pwr.h @@ -38,6 +38,8 @@ # include <libopencm3/stm32/l0/pwr.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/pwr.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/pwr.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/rcc.h b/include/libopencm3/stm32/rcc.h index b87f950a..0b520173 100644 --- a/include/libopencm3/stm32/rcc.h +++ b/include/libopencm3/stm32/rcc.h @@ -38,6 +38,10 @@ # include <libopencm3/stm32/l1/rcc.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/rcc.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/rcc.h> +#elif defined(GD32F1X0) +# include <libopencm3/gd32/f1x0/rcc.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/rng.h b/include/libopencm3/stm32/rng.h index 40687af2..58878c71 100644 --- a/include/libopencm3/stm32/rng.h +++ b/include/libopencm3/stm32/rng.h @@ -30,6 +30,8 @@ # include <libopencm3/stm32/l0/rng.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/rng.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/rng.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/spi.h b/include/libopencm3/stm32/spi.h index 2d32e61c..f4082bc9 100644 --- a/include/libopencm3/stm32/spi.h +++ b/include/libopencm3/stm32/spi.h @@ -38,6 +38,8 @@ # include <libopencm3/stm32/l1/spi.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/spi.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/spi.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/syscfg.h b/include/libopencm3/stm32/syscfg.h index b5fc0e47..8e78c475 100644 --- a/include/libopencm3/stm32/syscfg.h +++ b/include/libopencm3/stm32/syscfg.h @@ -28,6 +28,8 @@ # include <libopencm3/stm32/f3/syscfg.h> #elif defined(STM32F4) # include <libopencm3/stm32/f4/syscfg.h> +#elif defined(STM32F7) +# include <libopencm3/stm32/f7/syscfg.h> #elif defined(STM32L0) # include <libopencm3/stm32/l0/syscfg.h> #elif defined(STM32L1) diff --git a/include/libopencm3/stm32/timer.h b/include/libopencm3/stm32/timer.h index 3f16e797..4d1afc7a 100644 --- a/include/libopencm3/stm32/timer.h +++ b/include/libopencm3/stm32/timer.h @@ -40,6 +40,8 @@ # include <libopencm3/stm32/l1/timer.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/timer.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/timer.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/usart.h b/include/libopencm3/stm32/usart.h index 7f3b11e9..7b22d4bf 100644 --- a/include/libopencm3/stm32/usart.h +++ b/include/libopencm3/stm32/usart.h @@ -38,6 +38,8 @@ # include <libopencm3/stm32/l1/usart.h> #elif defined(STM32L4) # include <libopencm3/stm32/l4/usart.h> +#elif defined(STM32G0) +# include <libopencm3/stm32/g0/usart.h> #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/swm050/doc-swm050.h b/include/libopencm3/swm050/doc-swm050.h new file mode 100644 index 00000000..4ec7c4e8 --- /dev/null +++ b/include/libopencm3/swm050/doc-swm050.h @@ -0,0 +1,30 @@ +/** @page libopencm3 SWM050 + +@version 1.0.0 + +API documentation for Synwit SWM050 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup peripheral_apis Peripheral APIs + * APIs for device peripherals + */ + +/** @defgroup SWM050 SWM050 +Libraries for Synwit SWM050 series. + +@version 1.0.0 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup SWM050_defines SWM050 Defines + +@brief Defined Constants and Types for the SWM050 series + +@version 1.0.0 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/include/libopencm3/swm050/gpio.h b/include/libopencm3/swm050/gpio.h new file mode 100644 index 00000000..f54ec44d --- /dev/null +++ b/include/libopencm3/swm050/gpio.h @@ -0,0 +1,116 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief <b>Defined Constants and Types for the SWM050 General Purpose I/O</b> + * + * @ingroup SWM050_defines + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/swm050/memorymap.h> + +/* GPIO number definitions (for convenience) */ +/** @defgroup gpio_pin_id GPIO Pin Identifiers + +@{*/ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO_ALL 0x3ff +/**@}*/ + +/* GPIO direction definitions */ +/** @defgroup gpio_dir GPIO Pin Direction +@{*/ +#define GPIO_INPUT 0x0 +#define GPIO_OUTPUT 0x1 +/**@}*/ + +/** @defgroup gpio_registers GPIO Registers +@{*/ +/** Data register */ +#define GPIO_DATA MMIO32(GPIO_BASE + 0x0) +/** Direction register */ +#define GPIO_DIR MMIO32(GPIO_BASE + 0x4) +/** Interrupt enable register */ +#define GPIO_INTEN MMIO32(GPIO_BASE + 0x30) +/** Interrupt mask register */ +#define GPIO_INTMASK MMIO32(GPIO_BASE + 0x34) +/** Interrupt trigger mode register */ +#define GPIO_INTLEVEL MMIO32(GPIO_BASE + 0x38) +/** Interrupt polarity register */ +#define GPIO_INTPOLARITY MMIO32(GPIO_BASE + 0x3c) +/** Interrupt status after masking */ +#define GPIO_INTSTATUS MMIO32(GPIO_BASE + 0x40) +/** Interrupt status before masking */ +#define GPIO_INTRAWSTATUS MMIO32(GPIO_BASE + 0x44) +/** Interrupt clear register */ +#define GPIO_INTEOI MMIO32(GPIO_BASE + 0x48) +/** External register (wat) */ +#define GPIO_EXT MMIO32(GPIO_BASE + 0x4c) + +/**@}*/ + +/** @defgroup syscon_register SYSCON Registers + * @note These registers are really part of the SYSCON system control space + * @{*/ +/** SWD Enable register */ +#define SWD_SEL MMIO32(SYSTEM_CON_BASE + 0x30) +/** GPIO Alternat function selection register */ +#define GPIO_SEL MMIO32(SYSTEM_CON_BASE + 0x80) +/** GPIO Pull up register */ +#define GPIO_PULLUP MMIO32(SYSTEM_CON_BASE + 0x90) +/** GPIO Input enable register */ +#define GPIO_INEN MMIO32(SYSTEM_CON_BASE + 0xe0) +/*@}*/ + +BEGIN_DECLS + +void gpio_set(uint16_t gpios); +void gpio_clear(uint16_t gpios); +uint16_t gpio_get(uint16_t gpios); +void gpio_toggle(uint16_t gpios); + +void gpio_input(uint16_t gpios); +void gpio_output(uint16_t gpios); +void gpio_sel_af(uint16_t gpios, bool af_en); +void gpio_pullup(uint16_t gpios, bool en); +void gpio_in_en(uint16_t gpios, bool en); + +void gpio_sel_swd(bool en); + +END_DECLS + +#endif +/**@}*/
\ No newline at end of file diff --git a/include/libopencm3/swm050/irq.json b/include/libopencm3/swm050/irq.json new file mode 100644 index 00000000..339d81eb --- /dev/null +++ b/include/libopencm3/swm050/irq.json @@ -0,0 +1,21 @@ +{ + "irqs": [ + "timer_se0", + "timer_se1", + "wdt", + "cp", + "gpioa0", + "gpioa1", + "gpioa2", + "gpioa3", + "gpioa4", + "gpioa5", + "gpioa6", + "gpioa7", + "gpioa8", + "gpioa9" + ], + "partname_humanreadable": "SWM050 series", + "partname_doxygen": "SWM050", + "includeguard": "LIBOPENCM3_SWM050_NVIC_H" +} diff --git a/include/libopencm3/swm050/memorymap.h b/include/libopencm3/swm050/memorymap.h new file mode 100644 index 00000000..97fe23df --- /dev/null +++ b/include/libopencm3/swm050/memorymap.h @@ -0,0 +1,35 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include <libopencm3/cm3/memorymap.h> + +/* Memory map for all buses */ +#define PERIPH_BASE (0x40000000U) + +#define SYSTEM_CON_BASE (PERIPH_BASE + 0x0) +#define GPIO_BASE (PERIPH_BASE + 0x1000) +#define TIMER_SE0_BASE (PERIPH_BASE + 0x2000) +#define TIMER_SE1_BASE (PERIPH_BASE + 0x2400) +#define WDT_BASE (PERIPH_BASE + 0x19000) +#define SYSCTL_BASE (PERIPH_BASE + 0xf0000) + +#endif diff --git a/include/libopencm3/usb/doc-usb.h b/include/libopencm3/usb/doc-usb.h index faa01b11..2093cb92 100644 --- a/include/libopencm3/usb/doc-usb.h +++ b/include/libopencm3/usb/doc-usb.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 Generic USB +/** @page libopencm3 Generic USB @version 1.0.0 diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index 3decd762..1f508e85 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -143,8 +143,10 @@ typedef void (*usbd_endpoint_callback)(usbd_device *usbd_dev, uint8_t ep); * config callback. The specified callback will be called if * (type == (bmRequestType & type_mask)). * @sa usbd_register_set_config_callback + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param type Handled request type * @param type_mask Mask to apply before matching request type + * @param callback your desired callback function * @return 0 if successful */ extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, @@ -153,12 +155,17 @@ extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, /* <usb_standard.c> */ /** Registers a "Set Config" callback + * @param usbd_dev the usb device handle returned from @ref usbd_init + * @param callback your desired callback function * @return 0 if successful or already existed. * @return -1 if no more space was available for callbacks. */ extern int usbd_register_set_config_callback(usbd_device *usbd_dev, usbd_set_config_callback callback); -/** Registers a "Set Interface" (alternate setting) callback */ +/** Registers a "Set Interface" (alternate setting) callback + * @param usbd_dev the usb device handle returned from @ref usbd_init + * @param callback your desired callback function + */ extern void usbd_register_set_altsetting_callback(usbd_device *usbd_dev, usbd_set_altsetting_callback callback); @@ -170,18 +177,28 @@ extern void usbd_poll(usbd_device *usbd_dev); * This function is implemented as weak function and can be replaced by an * application specific version to handle chips that don't have built-in * handling for this (e.g. STM32F1.) + * @param usbd_dev the usb device handle returned from @ref usbd_init + * @param disconnected true to request a disconnect */ extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected); /** Setup an endpoint + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param addr Full EP address including direction (e.g. 0x01 or 0x81) * @param type Value for bmAttributes (USB_ENDPOINT_ATTR_*) + * @param max_size Endpoint max size + * @param callback your desired callback function + * @note The stack only supports 8 endpoints, 0..7, so don't try + * and use arbitrary addresses here, even though USB itself would allow this. + * Not all backends support arbitrary addressing anyway. */ extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, uint16_t max_size, usbd_endpoint_callback callback); /** Write a packet + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param addr EP address (direction is ignored) + * @param buf pointer to user data to write * @param len # of bytes * @return 0 if failed, len if successful */ @@ -189,13 +206,16 @@ extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len); /** Read a packet + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param addr EP address + * @param buf user buffer that will receive data * @param len # of bytes * @return Actual # of bytes read */ extern uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len); /** Set/clear STALL condition on an endpoint + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param addr Full EP address (with direction bit) * @param stall if 0, clear STALL, else set stall. */ @@ -203,12 +223,14 @@ extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall); /** Get STALL status of an endpoint + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param addr Full EP address (with direction bit) * @return nonzero if endpoint is stalled */ extern uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr); /** Set an Out endpoint to NAK + * @param usbd_dev the usb device handle returned from @ref usbd_init * @param addr EP address * @param nak if nonzero, set NAK */ diff --git a/include/libopencm3/vf6xx/doc-vf6xx.h b/include/libopencm3/vf6xx/doc-vf6xx.h index 2fb634ae..64482978 100644 --- a/include/libopencm3/vf6xx/doc-vf6xx.h +++ b/include/libopencm3/vf6xx/doc-vf6xx.h @@ -1,4 +1,4 @@ -/** @mainpage libopencm3 VF6xx +/** @page libopencm3 VF6xx * * @version 1.0.0 * diff --git a/include/libopencmsis/dispatch/irqhandlers.h b/include/libopencmsis/dispatch/irqhandlers.h index 7fda9135..e8ac859f 100644 --- a/include/libopencmsis/dispatch/irqhandlers.h +++ b/include/libopencmsis/dispatch/irqhandlers.h @@ -16,6 +16,11 @@ # include <libopencmsis/stm32/l1/irqhandlers.h> #elif defined(STM32L4) # include <libopencmsis/stm32/l4/irqhandlers.h> +#elif defined(STM32G0) +# include <libopencmsis/stm32/l4/irqhandlers.h> + +#elif defined(GD32F1X0) +# include <libopencmsis/gd32/f1x0/irqhandlers.h> #elif defined(EFM32TG) # include <libopencmsis/efm32/efm32tg/irqhandlers.h> @@ -54,6 +59,8 @@ /* Yes, we use the same interrupt table for both LM3S and LM4F */ # include <libopencmsis/lm3s/irqhandlers.h> +#elif defined(SWM050) +# include <libopencmsis/swm050/irqhandlers.h> #else # warning"no chipset defined; user interrupts are not redirected" diff --git a/ld/devices.data b/ld/devices.data index 2644c6f7..1c474f70 100644 --- a/ld/devices.data +++ b/ld/devices.data @@ -117,9 +117,13 @@ stm32f2[01][57]?e* stm32f2 ROM=512K RAM=128K stm32f20[57]?f* stm32f2 ROM=768K RAM=128K stm32f2[01][57]?g* stm32f2 ROM=1024K RAM=128K +stm32f301?6* stm32f3 ROM=32K RAM=16K +stm32f301?8* stm32f3 ROM=64K RAM=16K stm32f302?b* stm32f3ccm ROM=128K RAM=24K CCM=8K stm32f302?c* stm32f3ccm ROM=256K RAM=32K CCM=8K stm32f302?8* stm32f3 ROM=64K RAM=16K +stm32f303?6* stm32f3ccm ROM=32K RAM=12K CCM=4K +stm32f303?8* stm32f3ccm ROM=64K RAM=12K CCM=4K stm32f303?b* stm32f3ccm ROM=128K RAM=32K CCM=8K stm32f3[01]3?c* stm32f3ccm ROM=256K RAM=40K CCM=8K stm32f373?8* stm32f3 ROM=64K RAM=16K @@ -165,16 +169,23 @@ stm32l0[78]??8* stm32l0 ROM=64K RAM=20K stm32l0???b* stm32l0 ROM=128K RAM=20K stm32l0???z* stm32l0 ROM=192K RAM=20K -stm32l100?6* stm32l1 ROM=32K RAM=4K -stm32l100?8* stm32l1 ROM=64K RAM=8K -stm32l100?b* stm32l1 ROM=128K RAM=10K -stm32l100?c* stm32l1 ROM=256K RAM=16K +stm32l100?6* stm32l1eep ROM=32K RAM=4K EEP=2K +stm32l100?8* stm32l1eep ROM=64K RAM=8K EEP=2K +stm32l100?b*_a stm32l1eep ROM=128K RAM=16K EEP=2K +stm32l100?b* stm32l1eep ROM=128K RAM=10K EEP=2K +stm32l100?c* stm32l1eep ROM=256K RAM=16K EEP=4K +stm32l15[12]?6*_a stm32l1eep ROM=32K RAM=16K EEP=4K stm32l15[12]?6* stm32l1eep ROM=32K RAM=10K EEP=4K +stm32l15[12]?8*_a stm32l1eep ROM=64K RAM=32K EEP=4K stm32l15[12]?8* stm32l1eep ROM=64K RAM=10K EEP=4K +stm32l15[12]?b*_a stm32l1eep ROM=128K RAM=32K EEP=4K stm32l15[12]?b* stm32l1eep ROM=128K RAM=16K EEP=4K stm32l15[12]?c* stm32l1eep ROM=256K RAM=32K EEP=8K +stm32l15[12]?d*_x stm32l1eep ROM=384K RAM=80K EEP=16K stm32l15[12]?d* stm32l1eep ROM=384K RAM=48K EEP=12K +stm32l15[12]?e* stm32l1eep ROM=512K RAM=80K EEP=16K stm32l162?c* stm32l1eep ROM=256K RAM=32K EEP=8K +stm32l162?d*_x stm32l1eep ROM=384K RAM=80K EEP=16K stm32l162?d* stm32l1eep ROM=384K RAM=48K EEP=12K stm32l43??b* stm32l4 ROM=128K RAM=48K RAM2=16K @@ -196,7 +207,6 @@ stm32l496?e* stm32l4 ROM=512K RAM=256K RAM2=64K stm32l496?g* stm32l4 ROM=1024K RAM=256K RAM2=64K stm32l4a6?g* stm32l4 ROM=1024K RAM=256K RAM2=64K - stm32ts60 stm32t ROM=32K RAM=10K stm32w108c8 stm32w ROM=64K RAM=8K @@ -204,6 +214,14 @@ stm32w108?b stm32w ROM=128K RAM=8K stm32w108cz stm32w ROM=192K RAM=12K stm32w108cc stm32w ROM=256K RAM=16K +stm32g0[43]1?4* stm32g0 ROM=16K RAM=8K +stm32g0[43]1?6* stm32g0 ROM=32K RAM=8K +stm32g0[43]1?8* stm32g0 ROM=64K RAM=8K +stm32g0[78]1?8* stm32g0 ROM=64K RAM=36K +stm32g0[78][01]?b* stm32g0 ROM=128K RAM=36K +stm32g0[BC]1?c* stm32g0 ROM=256K RAM=128K +stm32g0[BC]1?e* stm32g0 ROM=512K RAM=128K + ################################################################################ # the SAM3 chips @@ -459,6 +477,7 @@ stm32f7 END ROM_OFF=0x08000000 RAM_OFF=0x20010000 CPU=cortex-m7 FPU=hard-fpv5-sp stm32l0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft stm32l1 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft stm32l4 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 RAM2_OFF=0x10000000 RAM3_OFF=0x20040000 CPU=cortex-m4 FPU=hard-fpv4-sp-d16 +stm32g0 END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m0plus FPU=soft stm32w END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft stm32t END ROM_OFF=0x08000000 RAM_OFF=0x20000000 CPU=cortex-m3 FPU=soft diff --git a/lib/cm3/dwt.c b/lib/cm3/dwt.c index b4408b0c..91a67029 100644 --- a/lib/cm3/dwt.c +++ b/lib/cm3/dwt.c @@ -1,3 +1,29 @@ +/** @defgroup CM3_dwt_file DWT + * + * @ingroup CM3_files + * + * @brief <b>libopencm3 Cortex-M Data Watchpoint and Trace unit</b> + * + * The DWT provides + * * Comparators, that support + * * watch points + * * data tracing + * * signalling to ETM + * * PC value tracing + * * cycle count matching + * * extra PC sampling + * * Sampling as a result of a clock count + * * external access for sampling + * * exception trace + * * performance profiling counters. + * + * Which of these features are available is unfortunately implementation defined. + * + * @see ARMv7m Architecture Reference Manual (Chapter ARMv7-M Debug) + * + * LGPL License Terms @ref lgpl_license + * @{ + */ /* * This file is part of the libopencm3 project. * @@ -75,3 +101,5 @@ uint32_t dwt_read_cycle_counter(void) } #endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ } + +/**@}*/
\ No newline at end of file diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c index 6c2188a8..7b20941f 100644 --- a/lib/cm3/nvic.c +++ b/lib/cm3/nvic.c @@ -51,7 +51,7 @@ * * Enables a user interrupt. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_enable_irq(uint8_t irqn) @@ -64,7 +64,7 @@ void nvic_enable_irq(uint8_t irqn) * * Disables a user interrupt. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_disable_irq(uint8_t irqn) @@ -77,7 +77,7 @@ void nvic_disable_irq(uint8_t irqn) * * True if the interrupt has occurred and is waiting for service. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @return Boolean. Interrupt pending. */ @@ -92,7 +92,7 @@ uint8_t nvic_get_pending_irq(uint8_t irqn) * Force a user interrupt to a pending state. This has no effect if the * interrupt is already pending. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_set_pending_irq(uint8_t irqn) @@ -106,7 +106,7 @@ void nvic_set_pending_irq(uint8_t irqn) * Force remove a user interrupt from a pending state. This has no effect if * the interrupt is actively being serviced. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs */ void nvic_clear_pending_irq(uint8_t irqn) @@ -119,7 +119,7 @@ void nvic_clear_pending_irq(uint8_t irqn) /*---------------------------------------------------------------------------*/ /** @brief NVIC Return Enabled Interrupt * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @return Boolean. Interrupt enabled. */ @@ -144,7 +144,7 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn) * There are 4 priority levels only, given by the upper two bits of the * priority byte, as required by ARM standards. No grouping available. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of * 16) */ @@ -170,7 +170,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority) * * Interrupt has occurred and is currently being serviced. * - * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint + * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs * @return Boolean. Interrupt active. */ diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c index 8c5a2f3a..52f38e81 100644 --- a/lib/cm3/scb.c +++ b/lib/cm3/scb.c @@ -1,3 +1,23 @@ +/** @defgroup CM3_scb_file SCB + * + * @ingroup CM3_files + * + * @brief <b>libopencm3 Cortex-M System Control Block</b> + * + * The System Control Block (SCB) is a section of the System Control Space + * which provides status information and control features for the processor core. + * It allows, amongst other: + * * software reset control + * * exception management and grouping + * * fault information + * * power management + * * debug status information + * + * @see ARMv7m Architecture Reference Manual (Chapter B3.2.1 About the SCB) + * + * LGPL License Terms @ref lgpl_license + * @{ + */ /* * This file is part of the libopencm3 project. * @@ -45,3 +65,5 @@ void scb_set_priority_grouping(uint32_t prigroup) SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup; } #endif + +/**@}*/
\ No newline at end of file diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c index a99593b6..d775dd06 100644 --- a/lib/cm3/systick.c +++ b/lib/cm3/systick.c @@ -48,7 +48,7 @@ * * @note The systick counter value might be undefined upon startup. To get * predictable behavior, it is a good idea to set or clear the counter after - * set reload. @seealso systick_clear + * set reload. @sa systick_clear * * @param[in] value uint32_t. 24 bit reload value. */ diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 3c12350d..0d4dd519 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -16,6 +16,11 @@ # include "../stm32/l1/vector_nvic.c" #elif defined(STM32L4) # include "../stm32/l4/vector_nvic.c" +#elif defined(STM32G0) +# include "../stm32/g0/vector_nvic.c" + +#elif defined(GD32F1X0) +# include "../gd32/f1x0/vector_nvic.c" #elif defined(EFM32TG) # include "../efm32/tg/vector_nvic.c" @@ -66,6 +71,9 @@ #elif defined(MSP432E4) # include "../msp432/e4/vector_nvic.c" +#elif defined(SWM050) +# include "../swm050/vector_nvic.c" + #else # warning "no interrupts defined for chipset;"\ "not allocating space in the vector table" diff --git a/lib/efm32/common/acmp_common.c b/lib/efm32/common/acmp_common.c new file mode 100644 index 00000000..1095d673 --- /dev/null +++ b/lib/efm32/common/acmp_common.c @@ -0,0 +1,15 @@ +/** @addtogroup acmp_file ACMP peripheral API + * @ingroup peripheral_apis + * @brief Analog Comparator helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/acmp.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/adc_common.c b/lib/efm32/common/adc_common.c index 980c7151..4c7a1481 100644 --- a/lib/efm32/common/adc_common.c +++ b/lib/efm32/common/adc_common.c @@ -1,3 +1,6 @@ +/** @addtogroup adc_file ADC peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include <libopencm3/efm32/adc.h> +/**@{*/ + /** * Set ADC over sampling * @param[in] adc ADC (use ADCx) @@ -633,6 +638,7 @@ uint32_t adc_scan_data_peak(uint32_t adc) /** * Set ADC scan gain calibration * @param[in] adc ADC (use ADCx) + * @param scan_gain calibration of gain for internal ref */ void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain) { @@ -642,6 +648,7 @@ void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain) /** * Set ADC scan offset calibration * @param[in] adc ADC (use ADCx) + * @param scan_offset calibration of offset for internal ref */ void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset) { @@ -651,6 +658,7 @@ void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset) /** * Set ADC single gain calibration * @param[in] adc ADC (use ADCx) + * @param single_gain calibration of gain for internal ref */ void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain) { @@ -660,8 +668,11 @@ void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain) /** * Set ADC single offset calibration * @param[in] adc ADC (use ADCx) + * @param single_offset calibration of offset for internal ref */ void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset) { ADC_CAL(adc) = (ADC_CAL(adc) & ADC_CAL_SINGLEOFF_MASK) | single_offset; } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/burtc_common.c b/lib/efm32/common/burtc_common.c new file mode 100644 index 00000000..e909f8cd --- /dev/null +++ b/lib/efm32/common/burtc_common.c @@ -0,0 +1,15 @@ +/** @addtogroup burtc_file BURTC peripheral API + * @ingroup peripheral_apis + * @brief Backup RTC helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/burtc.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/cmu_common.c b/lib/efm32/common/cmu_common.c index 6edc42dd..8a577516 100644 --- a/lib/efm32/common/cmu_common.c +++ b/lib/efm32/common/cmu_common.c @@ -1,3 +1,6 @@ +/** @addtogroup cmu_file CMU peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -20,6 +23,8 @@ #include <libopencm3/efm32/cmu.h> #include <libopencm3/efm32/msc.h> +/**@{*/ + /** * Enable CMU registers lock. */ @@ -54,7 +59,7 @@ bool cmu_get_lock_flag(void) * * Enable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -69,7 +74,7 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken) * @brief Disable Peripheral Clock in running mode. * Disable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -270,3 +275,5 @@ void cmu_clock_setup_in_hfxo_out_48mhz(void) /* wait till HFXO not selected */ while (cmu_get_hfclk_source() != HFXO); } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/dac_common.c b/lib/efm32/common/dac_common.c index 8a211afc..4d982401 100644 --- a/lib/efm32/common/dac_common.c +++ b/lib/efm32/common/dac_common.c @@ -1,3 +1,6 @@ +/** @addtogroup dac_file DAC peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -22,6 +25,8 @@ #include <libopencm3/efm32/dac.h> +/**@{*/ + /** * Set DAC refresh cycle * @param[in] dac DAC (use DACx) @@ -95,8 +100,8 @@ void dac_disable_sine(uint32_t dac) /** * Set PRS trigger source on DAC channel * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) - * @param[in] prs_ch PRS Channel (use PRS_CHx) + * @param[in] dac_chan DAC Channel (use DAC_CHx) + * @param[in] prs_chan PRS Channel (use PRS_CHx) */ void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan, enum prs_ch prs_chan) @@ -110,7 +115,7 @@ void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan, /** * Enable PRS triggerring * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_enable_prs_trigger(uint32_t dac, enum dac_ch ch) { @@ -120,7 +125,7 @@ void dac_enable_prs_trigger(uint32_t dac, enum dac_ch ch) /** * Disable PRS triggerring * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_disable_prs_trigger(uint32_t dac, enum dac_ch ch) { @@ -130,7 +135,7 @@ void dac_disable_prs_trigger(uint32_t dac, enum dac_ch ch) /** * Enable auto refresh * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_enable_auto_refresh(uint32_t dac, enum dac_ch ch) { @@ -140,7 +145,7 @@ void dac_enable_auto_refresh(uint32_t dac, enum dac_ch ch) /** * Disable auto refresh * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_disable_auto_refresh(uint32_t dac, enum dac_ch ch) { @@ -150,7 +155,7 @@ void dac_disable_auto_refresh(uint32_t dac, enum dac_ch ch) /** * Enable channel * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_enable_channel(uint32_t dac, enum dac_ch ch) { @@ -160,9 +165,11 @@ void dac_enable_channel(uint32_t dac, enum dac_ch ch) /** * Disable channel * @param[in] dac DAC (use DACx) - * @param[in] dac_ch DAC Channel (use DAC_CHx) + * @param[in] ch DAC Channel (use DAC_CHx) */ void dac_disable_channel(uint32_t dac, enum dac_ch ch) { DAC_CHx_CTRL(dac, ch) &= ~DAC_CH_CTRL_REFREN; } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/dma_common.c b/lib/efm32/common/dma_common.c index e6967bfe..e6a18ced 100644 --- a/lib/efm32/common/dma_common.c +++ b/lib/efm32/common/dma_common.c @@ -1,3 +1,6 @@ +/** @addtogroup dma_file DMA peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include <libopencm3/efm32/dma.h> +/**@{*/ + #define CHANNEL_SUPPORT_LOOP(ch) (((ch) == DMA_CH0) || ((ch) == DMA_CH1)) /** @@ -563,8 +568,8 @@ static inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc, * descriptor * @param[in] ch Channel (use DMA_CHx) * @param[in] src_start Source data start address - * @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc() - * set value to calculate the src data end address from @a src_start + * this function uses @ref dma_calc_end_from_start to calculate the + * src data end address from @a src_start * @note dma_desc_set_count() should be called first. * @note dma_desc_set_src_inc() should be called first. */ @@ -586,9 +591,8 @@ void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, * descriptor * @param[in] ch Channel (use DMA_CHx) * @param[in] dest_start Destination data start address - * @param[in] this function use dma_desc_set_count() and - * dma_desc_set_dest_inc() set value to calculate the dest data end - * address from @a dest_start + * this function uses @ref dma_calc_end_from_start to calculate the + * dest data end address from @a dest_start * @note dma_desc_set_count() should be called first. * @note dma_desc_set_dest_inc() should be called first. */ @@ -619,3 +623,5 @@ void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode) cfg |= DMA_DESC_CH_CFG_CYCLE_CTRL(mode); DMA_DESC_CHx_CFG(desc_base, ch) = cfg; } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/emu_common.c b/lib/efm32/common/emu_common.c new file mode 100644 index 00000000..1015e8e0 --- /dev/null +++ b/lib/efm32/common/emu_common.c @@ -0,0 +1,15 @@ +/** @addtogroup emu_file EMU peripheral API + * @ingroup peripheral_apis + * @brief Energy Management Unit helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/emu.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/gpio_common.c b/lib/efm32/common/gpio_common.c index 23574228..0c768ca4 100644 --- a/lib/efm32/common/gpio_common.c +++ b/lib/efm32/common/gpio_common.c @@ -1,3 +1,6 @@ +/** @addtogroup gpio_file GPIO peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include <libopencm3/efm32/gpio.h> +/**@{*/ + /** * Enable GPIO registers lock. * @see gpio_disable_lock() @@ -173,3 +178,5 @@ void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios) { GPIO_P_PINLOCKN(gpio_port) = ~gpios; } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/i2c_common.c b/lib/efm32/common/i2c_common.c new file mode 100644 index 00000000..304f12e6 --- /dev/null +++ b/lib/efm32/common/i2c_common.c @@ -0,0 +1,15 @@ +/** @addtogroup i2c_file I2C peripheral API + * @ingroup peripheral_apis + * @brief I²C helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/i2c.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/letimer_common.c b/lib/efm32/common/letimer_common.c new file mode 100644 index 00000000..7c1ba9cb --- /dev/null +++ b/lib/efm32/common/letimer_common.c @@ -0,0 +1,15 @@ +/** @addtogroup letimer_file LETIMER peripheral API + * @ingroup peripheral_apis + * @brief Low Energy Timer helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/letimer.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/msc_common.c b/lib/efm32/common/msc_common.c new file mode 100644 index 00000000..a542898d --- /dev/null +++ b/lib/efm32/common/msc_common.c @@ -0,0 +1,15 @@ +/** @addtogroup msc_file MSC peripheral API + * @ingroup peripheral_apis + * @brief Memory Systems Controller helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/msc.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/prs_common.c b/lib/efm32/common/prs_common.c index bcd47f7f..877c5c07 100644 --- a/lib/efm32/common/prs_common.c +++ b/lib/efm32/common/prs_common.c @@ -1,3 +1,10 @@ +/** @addtogroup prs_file PRS peripheral API + * @ingroup peripheral_apis + * @brief EFM32 Peripheral Reflex System (PRS). + * The Peripheral Reflex System (PRS) system is a network which allows the + * different peripheral modules to communicate directly with each other + * without involving the CPU. + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +26,8 @@ #include <libopencm3/efm32/prs.h> +/**@{*/ + /** * Enable PRS output to GPIO. * @param[in] ch Channel (use PRS_CHx) @@ -138,3 +147,5 @@ void prs_set_signal(enum prs_ch ch, uint32_t signal) PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK) | signal; } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/rmu_common.c b/lib/efm32/common/rmu_common.c new file mode 100644 index 00000000..1b0a8cfd --- /dev/null +++ b/lib/efm32/common/rmu_common.c @@ -0,0 +1,15 @@ +/** @addtogroup rmu_file RMU peripheral API + * @ingroup peripheral_apis + * @brief Reset Management Unit helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/rmu.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/rtc_common.c b/lib/efm32/common/rtc_common.c new file mode 100644 index 00000000..b7898ae6 --- /dev/null +++ b/lib/efm32/common/rtc_common.c @@ -0,0 +1,16 @@ +/** @addtogroup rtc_file RTC peripheral API + * @ingroup peripheral_apis + * @brief Real Time Clock helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @sa rtc_defines + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/rtc.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/timer_common.c b/lib/efm32/common/timer_common.c index 22664954..8f82fcfe 100644 --- a/lib/efm32/common/timer_common.c +++ b/lib/efm32/common/timer_common.c @@ -1,3 +1,6 @@ +/** @addtogroup timer_file TIMER peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -19,6 +22,8 @@ #include <libopencm3/efm32/timer.h> +/**@{*/ + #define HAS_DEAD_TIME_INSERTION(timer) (timer == TIMER0) /** @@ -60,3 +65,5 @@ void timer_set_top(uint32_t timer, uint32_t top) { TIMER_TOP(timer) = top; } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/common/usart_common.c b/lib/efm32/common/usart_common.c new file mode 100644 index 00000000..ef49f42c --- /dev/null +++ b/lib/efm32/common/usart_common.c @@ -0,0 +1,18 @@ +/** @addtogroup usart_file UART/USART peripheral API + * @ingroup peripheral_apis + * @brief UART/USART helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @sa usart_defines + * @sa uart_defines + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/uart.h> +#include <libopencm3/efm32/usart.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/common/wdog_common.c b/lib/efm32/common/wdog_common.c new file mode 100644 index 00000000..a926ab92 --- /dev/null +++ b/lib/efm32/common/wdog_common.c @@ -0,0 +1,15 @@ +/** @addtogroup wdog_file WDOG peripheral API + * @ingroup peripheral_apis + * @brief Watchdog Module helper functions. + * + * <b>NO</b> helper functions exist. Only header definitions are available. + * Delete these lines if/when you add actual helper APIs. + * @copyright See @ref lgpl_license + */ + +#include <libopencm3/efm32/wdog.h> + +/**@{*/ + +/**@}*/ + diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile index 70b1a252..28026b8c 100644 --- a/lib/efm32/ezr32wg/Makefile +++ b/lib/efm32/ezr32wg/Makefile @@ -24,10 +24,8 @@ SRCLIBDIR ?= ../.. FAMILY = EZR32WG FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -38,14 +36,27 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = -OBJS = gpio_common.o cmu_common.o prs_common.o -OBJS += adc_common.o dma_common.o timer_common.o -OBJS += dac_common.o +OBJS += acmp_common.o +OBJS += adc_common.o +OBJS += burtc_common.o +OBJS += cmu_common.o +OBJS += dac_common.o +OBJS += dma_common.o +OBJS += emu_common.o +OBJS += gpio_common.o +OBJS += i2c_common.o +OBJS += letimer_common.o +OBJS += msc_common.o +OBJS += prs_common.o +OBJS += rmu_common.o +OBJS += rtc_common.o +OBJS += timer_common.o +OBJS += usart_common.o +OBJS += wdog_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_efm32.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/efm32/g/Makefile b/lib/efm32/g/Makefile index 1aace7c6..f1f3568b 100644 --- a/lib/efm32/g/Makefile +++ b/lib/efm32/g/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_efm32g SRCLIBDIR ?= ../.. FAMILY = EFM32G -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/gg/Makefile b/lib/efm32/gg/Makefile index a96b3df8..231cec2c 100644 --- a/lib/efm32/gg/Makefile +++ b/lib/efm32/gg/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_efm32gg SRCLIBDIR ?= ../.. FAMILY = EFM32GG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/hg/Makefile b/lib/efm32/hg/Makefile index f5b897d8..c6f7ba5a 100644 --- a/lib/efm32/hg/Makefile +++ b/lib/efm32/hg/Makefile @@ -24,10 +24,8 @@ LIBNAME = libopencm3_efm32hg SRCLIBDIR ?= ../.. FAMILY = EFM32HG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -40,9 +38,12 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = cmu.o gpio_common.o timer_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o \ - usb_dwc_common.o usb_efm32hg.o +OBJS += cmu.o +OBJS += gpio_common.o +OBJS += timer_common.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_dwc_common.o usb_efm32hg.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/efm32/hg/cmu.c b/lib/efm32/hg/cmu.c index db28680d..3d678eeb 100644 --- a/lib/efm32/hg/cmu.c +++ b/lib/efm32/hg/cmu.c @@ -1,3 +1,6 @@ +/** @addtogroup cmu_file CMU peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -20,6 +23,8 @@ #include <libopencm3/efm32/cmu.h> +/**@{*/ + /** * Enable CMU registers lock. */ @@ -54,7 +59,7 @@ bool cmu_get_lock_flag(void) * * Enable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -69,7 +74,7 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken) * @brief Disable Peripheral Clock in running mode. * Disable the clock on particular peripheral. * - * @param[in] periph enum cmu_periph_clken Peripheral Name + * @param[in] clken Peripheral Name * * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for * example) @@ -105,6 +110,9 @@ void cmu_osc_on(enum cmu_osc osc) case AUXHFRCO: CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN; break; + default: + /* not applicable */ + break; } } @@ -133,6 +141,9 @@ void cmu_osc_off(enum cmu_osc osc) case AUXHFRCO: CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS; break; + default: + /* not applicable */ + break; } } @@ -163,6 +174,9 @@ bool cmu_osc_ready_flag(enum cmu_osc osc) case AUXHFRCO: return (CMU_STATUS & CMU_STATUS_AUXHFRCORDY) != 0; break; + default: + /* not applicable */ + break; } return false; @@ -193,6 +207,9 @@ void cmu_wait_for_osc_ready(enum cmu_osc osc) case AUXHFRCO: while ((CMU_STATUS & CMU_STATUS_AUXHFRCORDY) == 0); break; + default: + /* not applicable */ + break; } } @@ -218,6 +235,9 @@ void cmu_set_hfclk_source(enum cmu_osc osc) case LFRCO: CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO; break; + case USHFRCODIV2: + CMU_CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2; + break; default: /* not applicable */ return; @@ -239,6 +259,8 @@ enum cmu_osc cmu_get_hfclk_source(void) return HFXO; } else if (status & CMU_STATUS_HFRCOSEL) { return HFRCO; + } else if (status & CMU_STATUS_USHFRCODIV2SEL) { + return USHFRCODIV2; } /* never reached */ @@ -247,7 +269,7 @@ enum cmu_osc cmu_get_hfclk_source(void) /** * Set USBCLK clock source - * @retval enum cmu_osc Oscillator name + * @param osc Oscillator name */ void cmu_set_usbclk_source(enum cmu_osc osc) { @@ -288,3 +310,5 @@ void cmu_wait_for_usbclk_selected(enum cmu_osc osc) return; } } + +/**@}*/
\ No newline at end of file diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index a0163677..da0ef81d 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -23,10 +23,8 @@ LIBNAME = libopencm3_efm32lg SRCLIBDIR ?= ../.. FAMILY = EFM32LG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -38,14 +36,27 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = -OBJS = gpio_common.o cmu_common.o prs_common.o -OBJS += adc_common.o dma_common.o timer_common.o -OBJS += dac_common.o +OBJS += acmp_common.o +OBJS += adc_common.o +OBJS += burtc_common.o +OBJS += cmu_common.o +OBJS += dac_common.o +OBJS += dma_common.o +OBJS += emu_common.o +OBJS += gpio_common.o +OBJS += i2c_common.o +OBJS += letimer_common.o +OBJS += msc_common.o +OBJS += prs_common.o +OBJS += rmu_common.o +OBJS += rtc_common.o +OBJS += timer_common.o +OBJS += usart_common.o +OBJS += wdog_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_efm32.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/efm32/tg/Makefile b/lib/efm32/tg/Makefile index 43ab711c..d29ade3e 100644 --- a/lib/efm32/tg/Makefile +++ b/lib/efm32/tg/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_efm32tg SRCLIBDIR ?= ../.. FAMILY = EFM32TG -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile index f2a767c5..0df4b0b6 100644 --- a/lib/efm32/wg/Makefile +++ b/lib/efm32/wg/Makefile @@ -24,10 +24,8 @@ SRCLIBDIR ?= ../.. FAMILY = EFM32WG FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -38,14 +36,27 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = -OBJS = gpio_common.o cmu_common.o prs_common.o -OBJS += adc_common.o dma_common.o timer_common.o -OBJS += dac_common.o +OBJS += acmp_common.o +OBJS += adc_common.o +OBJS += burtc_common.o +OBJS += cmu_common.o +OBJS += dac_common.o +OBJS += dma_common.o +OBJS += emu_common.o +OBJS += gpio_common.o +OBJS += i2c_common.o +OBJS += letimer_common.o +OBJS += msc_common.o +OBJS += prs_common.o +OBJS += rmu_common.o +OBJS += rtc_common.o +OBJS += timer_common.o +OBJS += usart_common.o +OBJS += wdog_common.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_efm32.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/ethernet/mac_stm32fxx7.c b/lib/ethernet/mac_stm32fxx7.c index 2a404b61..525f6229 100644 --- a/lib/ethernet/mac_stm32fxx7.c +++ b/lib/ethernet/mac_stm32fxx7.c @@ -371,7 +371,7 @@ void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits) * * @param[in] phy uint8_t ID of the PHY (defaults to 1) * @param[in] reg uint8_t Register address - * @param[in] bits uint16_t Bits that have to be set (or'ed) + * @param[in] setbits uint16_t Bits that have to be set (or'ed) */ void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits) { diff --git a/lib/gd32/f1x0/Makefile b/lib/gd32/f1x0/Makefile new file mode 100755 index 00000000..fb5cd4d6 --- /dev/null +++ b/lib/gd32/f1x0/Makefile @@ -0,0 +1,42 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see <http://www.gnu.org/licenses/>. +## + +LIBNAME = libopencm3_gd32f1x0 +SRCLIBDIR ?= ../.. + +CC = $(PREFIX)gcc +AR = $(PREFIX)ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DGD32F1X0 +TGT_CFLAGS += $(DEBUG_FLAGS) +# ARFLAGS = rcsv +ARFLAGS = rcs + +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += rcc.o rcc_common_all.o + +VPATH += ../:../../cm3:../common:../../stm32/common + +include ../../Makefile.include diff --git a/lib/gd32/f1x0/flash.c b/lib/gd32/f1x0/flash.c new file mode 100644 index 00000000..4f222082 --- /dev/null +++ b/lib/gd32/f1x0/flash.c @@ -0,0 +1,153 @@ +/** @defgroup flash_file FLASH peripheral API + * + * @ingroup peripheral_apis + * + * @brief <b>libopencm3 GD32F1x0 FLASH</b> + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian <BuFran@seznam.cz> + * + * @date 14 January 2014 + * + * FLASH memory may be used for data storage as well as code, and may be + * programmatically modified. Note that for firmware upload the GD32F1x0 + * provides a built-in bootloader in system memory that can be entered from a + * running program. + * + * FLASH must first be unlocked before programming. In this module a write to + * FLASH is a blocking operation until the end-of-operation flag is asserted. + * + * @note: don't forget to lock it again when all operations are complete. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/gd32/flash.h> + +/*---------------------------------------------------------------------------*/ +/** @brief Clear All Status Flags + +Program error, end of operation, write protect error, busy. +*/ + +void flash_clear_status_flags(void) +{ + flash_clear_pgerr_flag(); + flash_clear_eop_flag(); + flash_clear_wrprterr_flag(); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Read All Status Flags + +The programming error, end of operation, write protect error and busy flags +are returned in the order of appearance in the status register. + +@returns uint32_t. bit 0: busy, bit 2: programming error, bit 4: write protect +error, bit 5: end of operation. +*/ + +uint32_t flash_get_status_flags(void) +{ + return FLASH_SR & (FLASH_SR_PGERR | + FLASH_SR_EOP | + FLASH_SR_WRPRTERR | + FLASH_SR_BSY); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Program a Half Word to FLASH + +This performs all operations necessary to program a 16 bit word to FLASH memory. +The program error flag should be checked separately for the event that memory +was not properly erased. + +Status bit polling is used to detect end of operation. + +@param[in] address Full address of flash half word to be programmed. +@param[in] data half word to write +*/ + +void flash_program_half_word(uint32_t address, uint16_t data) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_PG; + + MMIO16(address) = data; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_CR_PG; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Erase a Page of FLASH + +This performs all operations necessary to erase a page in FLASH memory. +The page should be checked to ensure that it was properly erased. A page must +first be fully erased before attempting to program it. + +Note that the page sizes differ between devices. See the reference manual or +the FLASH programming manual for details. + +@param[in] page_address Full address of flash page to be erased. +*/ + +void flash_erase_page(uint32_t page_address) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_PER; + FLASH_AR = page_address; + FLASH_CR |= FLASH_CR_STRT; + + flash_wait_for_last_operation(); + + FLASH_CR &= ~FLASH_CR_PER; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Erase All FLASH + +This performs all operations necessary to erase all user pages in the FLASH +memory. The information block is unaffected. +*/ + +void flash_erase_all_pages(void) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */ + FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */ + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */ + +} + +/**@}*/ + diff --git a/lib/gd32/f1x0/rcc.c b/lib/gd32/f1x0/rcc.c new file mode 100644 index 00000000..729a71eb --- /dev/null +++ b/lib/gd32/f1x0/rcc.c @@ -0,0 +1,654 @@ +/** @defgroup rcc_file RCC peripheral API + +@ingroup peripheral_apis + +@brief <b>libopencm3 GD32F1x0 Reset and Clock Control</b> + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 +Federico Ruiz-Ugalde \<memeruiz at gmail dot com\> +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de> +@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org> + +@date 18 August 2012 + +This library supports the Reset and Clock Control System in the GD32F1x0 +series of ARM Cortex Microcontrollers by GigaDevice. + +@note Full support for F170 and F190 devices is not yet provided. + +Clock settings and resets for many peripherals are given here rather than in +the corresponding peripheral library. + +The library also provides a number of common configurations for the processor +system clock. Not all possible configurations are included. + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com> + * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de> + * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/cm3/assert.h> +#include <libopencm3/gd32/rcc.h> +#include <libopencm3/gd32/flash.h> + +/** Set the default clock frequencies */ +uint32_t rcc_apb1_frequency = 8000000; +uint32_t rcc_apb2_frequency = 8000000; +uint32_t rcc_ahb_frequency = 8000000; + +const struct rcc_clock_scale rcc_hsi_configs[] = { + { /* 48MHz */ + .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL12, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .use_hse = false, + .ahb_frequency = 48000000, + .apb1_frequency = 24000000, + .apb2_frequency = 48000000, + }, + { /* 64MHz */ + .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL16, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .use_hse = false, + .ahb_frequency = 64000000, + .apb1_frequency = 32000000, + .apb2_frequency = 64000000, + } +}; + +const struct rcc_clock_scale rcc_hse8_configs[] = { + { /* 72MHz */ + .pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL9, + .hpre = RCC_CFGR_HPRE_SYSCLK_NODIV, + .ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2, + .ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV, + .adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8, + .usbpre = RCC_CFGR_USBPRE_PLL_CLK_DIV1_5, + .use_hse = true, + .pll_hse_prediv = RCC_CFGR2_PREDIV_NODIV, + .ahb_frequency = 72000000, + .apb1_frequency = 36000000, + .apb2_frequency = 72000000, + }, +}; + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Clear the Oscillator Ready Interrupt Flag + +Clear the interrupt flag that was set when a clock oscillator became ready to +use. + +@param[in] osc Oscillator ID +*/ + +void rcc_osc_ready_int_clear(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case RCC_HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case RCC_HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case RCC_LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case RCC_LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Enable the Oscillator Ready Interrupt + +@param[in] osc Oscillator ID +*/ + +void rcc_osc_ready_int_enable(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case RCC_HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case RCC_HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case RCC_LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case RCC_LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Disable the Oscillator Ready Interrupt + +@param[in] osc Oscillator ID +*/ + +void rcc_osc_ready_int_disable(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case RCC_HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case RCC_HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case RCC_LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case RCC_LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Read the Oscillator Ready Interrupt Flag + +@param[in] osc Oscillator ID +@returns int. Boolean value for flag set. +*/ + +int rcc_osc_ready_int_flag(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case RCC_HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case RCC_HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case RCC_LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case RCC_LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + } + + cm3_assert_not_reached(); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Clear the Clock Security System Interrupt Flag + +*/ + +void rcc_css_int_clear(void) +{ + RCC_CIR |= RCC_CIR_CSSC; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Read the Clock Security System Interrupt Flag + +@returns int. Boolean value for flag set. +*/ + +int rcc_css_int_flag(void) +{ + return ((RCC_CIR & RCC_CIR_CSSF) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Wait for Oscillator Ready. + +@param[in] osc Oscillator ID +*/ + +void rcc_wait_for_osc_ready(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case RCC_HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case RCC_HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case RCC_LSE: + while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); + break; + case RCC_LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Turn on an Oscillator. + +Enable an oscillator and power on. Each oscillator requires an amount of time +to settle to a usable state. Refer to datasheets for time delay information. A +status flag is available to indicate when the oscillator becomes ready (see +@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready). + +@note The LSE clock is in the backup domain and cannot be enabled until the +backup domain write protection has been removed (see @ref +pwr_disable_backup_domain_write_protect). + +@param[in] osc Oscillator ID +*/ + +void rcc_osc_on(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR |= RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Turn off an Oscillator. + +Disable an oscillator and power off. + +@note An oscillator cannot be turned off if it is selected as the system clock. +@note The LSE clock is in the backup domain and cannot be disabled until the +backup domain write protection has been removed (see +@ref pwr_disable_backup_domain_write_protect) or the backup domain has been +(see reset @ref rcc_backupdomain_reset). + +@param[in] osc Oscillator ID +*/ + +void rcc_osc_off(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Enable the Clock Security System. + +*/ + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Disable the Clock Security System. + +*/ + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the Source for the System Clock. + +@param[in] clk System Clock Selection @ref rcc_cfgr_scs +*/ + +void rcc_set_sysclk_source(uint32_t clk) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) | + (clk << RCC_CFGR_SW_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the PLL Multiplication Factor. + +@note This only has effect when the PLL is disabled. + +@param[in] mul PLL multiplication factor @ref rcc_cfgr_pmf +*/ + +void rcc_set_pll_multiplication_factor(uint32_t mul) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLMUL_0_3 & ~RCC_CFGR_PLLMUL_4) | + ((mul & 0xf) << RCC_CFGR_PLLMUL_0_3_SHIFT) | + ((!!(mul & 0x10)) << RCC_CFGR_PLLMUL_4_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the PLL Clock Source. + +@note This only has effect when the PLL is disabled. + +@param[in] pllsrc PLL clock source @ref rcc_cfgr_pcs +*/ + +void rcc_set_pll_source(uint32_t pllsrc) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLSRC) | + (pllsrc << 16); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source. + +@note This only has effect when the PLL is disabled. + +@param[in] pllxtpre HSE division factor @ref rcc_cfgr_hsepre +*/ + +void rcc_set_pllxtpre(uint32_t pllxtpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLXTPRE) | + (pllxtpre << 17); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC RTC Clock Enabled Flag + +@returns uint32_t. Nonzero if the RTC Clock is enabled. +*/ + +uint32_t rcc_rtc_clock_enabled_flag(void) +{ + return RCC_BDCR & RCC_BDCR_RTCEN; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Enable the RTC clock + +*/ + +void rcc_enable_rtc_clock(void) +{ + RCC_BDCR |= RCC_BDCR_RTCEN; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the Source for the RTC clock + +@param[in] clock_source RTC clock source. Only HSE/128, LSE and LSI. +*/ + +void rcc_set_rtc_clock_source(enum rcc_osc clock_source) +{ + uint32_t reg32; + + switch (clock_source) { + case RCC_LSE: + /* Turn the LSE on and wait while it stabilises. */ + RCC_BDCR |= RCC_BDCR_LSEON; + while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0); + + /* Choose LSE as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 8); + break; + case RCC_LSI: + /* Turn the LSI on and wait while it stabilises. */ + RCC_CSR |= RCC_CSR_LSION; + while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0); + + /* Choose LSI as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 9); + break; + case RCC_HSE: + /* Turn the HSE on and wait while it stabilises. */ + RCC_CR |= RCC_CR_HSEON; + while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0); + + /* Choose HSE as the RTC clock source. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + RCC_BDCR |= (1 << 9) | (1 << 8); + break; + case RCC_PLL: + case RCC_HSI: + /* Unusable clock source, here to prevent warnings. */ + /* Turn off clock sources to RTC. */ + RCC_BDCR &= ~((1 << 8) | (1 << 9)); + break; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Setup the A/D Clock + +The ADC's have a common clock prescale setting. + +@param[in] adcpre Prescale divider taken from @ref rcc_cfgr_adcpre +*/ + +void rcc_set_adcpre(uint32_t adcpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_ADCPRE) | + (adcpre << RCC_CFGR_ADCPRE_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the APB2 Prescale Factor. + +@param[in] ppre2 APB2 prescale factor @ref rcc_cfgr_apb2pre +*/ + +void rcc_set_ppre2(uint32_t ppre2) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE2) | + (ppre2 << RCC_CFGR_PPRE2_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the APB1 Prescale Factor. + +@note The APB1 clock frequency must not exceed 36MHz. + +@param[in] ppre1 APB1 prescale factor @ref rcc_cfgr_apb1pre +*/ + +void rcc_set_ppre1(uint32_t ppre1) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE1) | + (ppre1 << RCC_CFGR_PPRE1_SHIFT); + +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the AHB Prescale Factor. + +@param[in] hpre AHB prescale factor @ref rcc_cfgr_ahbpre +*/ + +void rcc_set_hpre(uint32_t hpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_HPRE) | + (hpre << RCC_CFGR_HPRE_SHIFT); + +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Set the USB Prescale Factor. + +The prescale factor can be set to 1 (no prescale) for use when the PLL clock is +48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock. + +@note This bit cannot be reset while the USB clock is enabled. + +@param[in] usbpre USB prescale factor @ref rcc_cfgr_usbpre +*/ + +void rcc_set_usbpre(uint32_t usbpre) +{ + RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_USBPRE) | usbpre; +} + +void rcc_set_prediv(uint32_t prediv) +{ + RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Get the System Clock Source. + +@returns Unsigned int32. System clock source: +@li 00 indicates HSE +@li 01 indicates LSE +@li 02 indicates PLL +*/ + +uint32_t rcc_system_clock_source(void) +{ + /* Return the clock source which is used as system clock. */ + return (RCC_CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_SHIFT; +} + +/*---------------------------------------------------------------------------*/ +/* + * These functions are setting up the whole clock system for the most common + * input clock and output clock configurations. + */ +/*---------------------------------------------------------------------------*/ +/** + * Setup clocks to run from PLL. + * The arguments provide the pll source, multipliers, dividers, all that's + * needed to establish a system clock. + * @param clock clock information structure + */ +void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) +{ + if (clock->use_hse) { + /* Enable external high-speed oscillator. */ + rcc_osc_on(RCC_HSE); + rcc_wait_for_osc_ready(RCC_HSE); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK); + } else { + /* Enable internal high-speed oscillator. */ + rcc_osc_on(RCC_HSI); + rcc_wait_for_osc_ready(RCC_HSI); + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK); + } + + /* + * Set prescalers for AHB, ADC, APB1, APB2 and USB. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(clock->hpre); + rcc_set_ppre1(clock->ppre1); + rcc_set_ppre2(clock->ppre2); + + rcc_set_adcpre(clock->adcpre); + if (clock->use_hse) + rcc_set_usbpre(clock->usbpre); + + /* Set the PLL multiplication factor. */ + rcc_set_pll_multiplication_factor(clock->pllmul); + + if (clock->use_hse) { + /* Select HSE as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK); + + /* + * External frequency undivided before entering PLL + * (only valid/needed for HSE). + */ + rcc_set_prediv(clock->pll_hse_prediv); + } else { + /* Select HSI/2 as PLL source. */ + rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2); + } + + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(RCC_PLL); + rcc_wait_for_osc_ready(RCC_PLL); + + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK); + + /* Set the peripheral clock frequencies used */ + rcc_ahb_frequency = clock->ahb_frequency; + rcc_apb1_frequency = clock->apb1_frequency; + rcc_apb2_frequency = clock->apb2_frequency; +} + +/*---------------------------------------------------------------------------*/ +/** @brief RCC Reset the Backup Domain + +The backup domain registers are reset to disable RTC controls and clear user +data. +*/ + +void rcc_backupdomain_reset(void) +{ + /* Set the backup domain software reset. */ + RCC_BDCR |= RCC_BDCR_BDRST; + + /* Clear the backup domain software reset. */ + RCC_BDCR &= ~RCC_BDCR_BDRST; +} + +/**@}*/ + diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile index 7bce6313..287ccacc 100644 --- a/lib/lm3s/Makefile +++ b/lib/lm3s/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_lm3s SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -35,7 +33,12 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o assert.o rcc.o usart.o + +OBJS += assert.o +OBJS += gpio.o +OBJS += rcc.o +OBJS += usart.o +OBJS += vector.o VPATH += ../cm3 diff --git a/lib/lm3s/rcc.c b/lib/lm3s/rcc.c index 96c09504..248ff815 100644 --- a/lib/lm3s/rcc.c +++ b/lib/lm3s/rcc.c @@ -7,7 +7,7 @@ @version 1.0.0 @author @htmlonly © @endhtmlonly 2015 -Daniele Lacamera <root at danielinux dot net> +Daniele Lacamera \<root at danielinux dot net\> @date 21 November 2015 diff --git a/lib/lm4f/Makefile b/lib/lm4f/Makefile index 2cb3853a..ab23f083 100644 --- a/lib/lm4f/Makefile +++ b/lib/lm4f/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_lm4f SRCLIBDIR ?= .. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -37,9 +35,16 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o vector.o assert.o systemcontrol.o rcc.o uart.o \ - usb_lm4f.o usb.o usb_control.o usb_standard.o -OBJS += usb_msc.o + +OBJS += assert.o +OBJS += gpio.o +OBJS += rcc.o +OBJS += systemcontrol.o +OBJS += uart.o +OBJS += vector.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_lm4f.o VPATH += ../usb:../cm3 diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile index 5b6ec485..7d12597e 100644 --- a/lib/lpc13xx/Makefile +++ b/lib/lpc13xx/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_lpc13xx SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -35,7 +33,8 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o + +OBJS += gpio.o VPATH += ../cm3 diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile index 5a34606e..eaaef8c8 100644 --- a/lib/lpc17xx/Makefile +++ b/lib/lpc17xx/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_lpc17xx SRCLIBDIR ?= .. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -35,7 +33,9 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o pwr.o + +OBJS += gpio.o +OBJS += pwr.o VPATH += ../cm3 diff --git a/lib/lpc43xx/m0/Makefile b/lib/lpc43xx/m0/Makefile index e05b799c..6f36574b 100644 --- a/lib/lpc43xx/m0/Makefile +++ b/lib/lpc43xx/m0/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_lpc43xx_m0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -O2 -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m0 -mthumb -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DLPC43XX -DLPC43XX_M0 diff --git a/lib/lpc43xx/m4/Makefile b/lib/lpc43xx/m4/Makefile index 4c022f92..e9ca7eaf 100644 --- a/lib/lpc43xx/m4/Makefile +++ b/lib/lpc43xx/m4/Makefile @@ -24,10 +24,8 @@ LIBNAME = libopencm3_lpc43xx SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -O2 \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ diff --git a/lib/msp432/e4/Makefile b/lib/msp432/e4/Makefile index 61abb1ab..53d20f78 100644 --- a/lib/msp432/e4/Makefile +++ b/lib/msp432/e4/Makefile @@ -23,10 +23,8 @@ LIBNAME = libopencm3_msp432e4 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -40,7 +38,8 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = systemcontrol.o +OBJS += gpio.o +OBJS += systemcontrol.o VPATH += ../:../../cm3:../common diff --git a/lib/msp432/e4/gpio.c b/lib/msp432/e4/gpio.c new file mode 100644 index 00000000..f4b082cf --- /dev/null +++ b/lib/msp432/e4/gpio.c @@ -0,0 +1,448 @@ +/** @defgroup gpio_file General-Purpose I/O + * + * @ingroup MSP432E4xx + * + * @brief libopencm3 MSP432E4xx General Purpose Input/Outputs + * + * @version 1.0.0 + * + * @date 23 September 2018 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com> + * Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <libopencm3/msp432/e4/gpio.h> +#include <libopencm3/msp432/e4/systemcontrol.h> + +/** @brief General Purpose Input/Outputs Set Pin Mode + * + * Sets the Pin Direction, Analog/Digital Mode and Output Pin Pull, + * for a set of GPIO pins on a given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] mode Pin mode @ref gpio_mode + * - GPIO_MODE_OUTPUT -- Configure pin as output + * - GPIO_MODE_INPUT -- Configure pin as input + * - GPIO_MODE_ANALOG -- Configure pin as analog function + * @param[in] pull_up_down Pin pull up/down configuration @ref gpio_pull_up_down + * - GPIO_PUPD_NONE -- Do not pull the pin high or low + * - GPIO_PUPD_PULLUP -- Pull the pin high + * - GPIO_PUPD_PULLDOWN -- Pull the pin low + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be set, use bitwise OR '|' to separate them. + */ +void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, + enum gpio_pull_up_down pull_up_down, uint8_t gpios) +{ + GPIO_AFSEL(gpioport) &= ~gpios; + + switch (mode) { + case GPIO_MODE_OUTPUT: + GPIO_DIR(gpioport) |= gpios; + GPIO_DEN(gpioport) |= gpios; + GPIO_AMSEL(gpioport) &= ~gpios; + break; + case GPIO_MODE_INPUT: + GPIO_DIR(gpioport) &= ~gpios; + GPIO_DEN(gpioport) |= gpios; + GPIO_AMSEL(gpioport) &= ~gpios; + break; + case GPIO_MODE_ANALOG: + GPIO_AFSEL(gpioport) |= gpios; + GPIO_DEN(gpioport) &= ~gpios; + GPIO_AMSEL(gpioport) |= gpios; + break; + default: + /* Don't do anything */ + break; + } + + /* + * Setting a bit in the GPIO_PDR register clears the corresponding bit + * in the GPIO_PUR register, and vice-versa. + */ + switch (pull_up_down) { + case GPIO_PUPD_PULLUP: + GPIO_PDR(gpioport) &= ~gpios; + GPIO_PUR(gpioport) |= gpios; + break; + case GPIO_PUPD_PULLDOWN: + GPIO_PUR(gpioport) &= ~gpios; + GPIO_PDR(gpioport) |= gpios; + break; + case GPIO_PUPD_NONE: /* Fall through */ + default: + GPIO_PUR(gpioport) &= ~gpios; + GPIO_PDR(gpioport) &= ~gpios; + break; + } +} + +/** @brief General Purpose Input/Outputs Set Output Options + * + * When the pin is set to output mode, this sets the configuration + * (open drain/push pull), drive strength, speed and slew rate control, + * for a set of GPIO pins on a given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] otype Output driver configuration @ref gpio_output_type + * - GPIO_OTYPE_PP -- Configure pin driver as push-pull \n + * - GPIO_OTYPE_OD -- Configure pin driver as open drain + * @param[in] drive Pin drive strength @ref gpio_drive_strength + * - GPIO_DRIVE_2MA -- 2mA drive \n + * - GPIO_DRIVE_4MA -- 4mA drive \n + * - GPIO_DRIVE_6MA -- 4mA drive \n + * - GPIO_DRIVE_8MA -- 8mA drive \n + * - GPIO_DRIVE_10MA -- 10mA drive \n + * - GPIO_DRIVE_12MA -- 12mA drive + * @param[in] slewctl Pin slew rate control select @ref gpio_slew_ctl + * @note Available only for 8, 10 and 12-ma drive strength. + * - GPIO_SLEW_CTL_ENABLE -- Slew rate control enable + * - GPIO_SLEW_CTL_DISABLE -- Slew rate control disable + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be set, use bitwise OR '|' to separate them. + */ +void gpio_set_output_options(uint32_t gpioport, + enum gpio_output_type otype, + enum gpio_drive_strength drive, + enum gpio_slew_ctl slewctl, + uint8_t gpios) +{ + uint8_t i; + uint8_t pin_mask; + + if (otype == GPIO_OTYPE_OD) { + GPIO_ODR(gpioport) |= gpios; + } else { + GPIO_ODR(gpioport) &= ~gpios; + } + + GPIO_PP(gpioport) |= GPIO_PP_EDE; + + for (i = 0; i < 8; i++) { + pin_mask = (1 << i); + + if (!(gpios & pin_mask)) { + continue; + } + + GPIO_PC(gpioport) &= ~GPIO_PC_EDM_MASK(i); + GPIO_PC(gpioport) |= GPIO_PC_EDM(i, GPIO_PC_EDM_FULL_RANGE); + } + + GPIO_DR4R(gpioport) &= ~gpios; + GPIO_DR8R(gpioport) &= ~gpios; + GPIO_DR12R(gpioport) &= ~gpios; + + switch (drive) { + case GPIO_DRIVE_4MA: + GPIO_DR4R(gpioport) |= gpios; + break; + case GPIO_DRIVE_6MA: + GPIO_DR8R(gpioport) |= gpios; + break; + case GPIO_DRIVE_8MA: + GPIO_DR4R(gpioport) |= gpios; + GPIO_DR8R(gpioport) |= gpios; + break; + case GPIO_DRIVE_10MA: + GPIO_DR8R(gpioport) |= gpios; + GPIO_DR12R(gpioport) |= gpios; + break; + case GPIO_DRIVE_12MA: + GPIO_DR4R(gpioport) |= gpios; + GPIO_DR8R(gpioport) |= gpios; + GPIO_DR12R(gpioport) |= gpios; + break; + case GPIO_DRIVE_2MA: /* Fall through */ + default: + /* don't anything */ + break; + } + + if ((slewctl == GPIO_SLEW_CTL_ENABLE) && + ((drive == GPIO_DRIVE_8MA) || (drive == GPIO_DRIVE_10MA) || + (drive == GPIO_DRIVE_12MA))) { + GPIO_SLR(gpioport) |= gpios; + } else { + GPIO_SLR(gpioport) &= ~gpios; + } +} + +/** @brief General Purpose Input/Outputs Set Alternate Function Selection + * + * Mux the pin or group of pins to the given alternate function. Note that a + * number of pins may be set but only with a single AF number. + * + * Because AF0 is not used on the MSP432E4, + * passing GPIO_AF_DISABLE as the alt_func_num parameter will disable + * the alternate function of the given pins. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] alt_func_num Pin alternate function number or GPIO_AF_DISABLE to + * disable the alternate function multiplexing. + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be set, use bitwise OR '|' to separate them. + */ +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios) +{ + uint32_t pctl32; + uint8_t pin_mask; + uint8_t i; + + /* Did we mean to disable the alternate function? */ + if (alt_func_num == 0) { + GPIO_AFSEL(gpioport) &= ~gpios; + return; + } + + /* Enable the alternate function */ + GPIO_AFSEL(gpioport) |= gpios; + + /* Now take care of the actual multiplexing */ + pctl32 = GPIO_PCTL(gpioport); + for (i = 0; i < 8; i++) { + pin_mask = (1 << i); + + if (!(gpios & pin_mask)) { + continue; + } + + pctl32 &= ~GPIO_PCTL_MASK(i); + pctl32 |= GPIO_PCTL_AF(i, (alt_func_num & 0xf)); + } + + GPIO_PCTL(gpioport) = pctl32; +} + +/** @brief General Purpose Input/Outputs Configure Interrupt Trigger + * + * Sets the trigger level/edge, for a set of GPIO pins on a given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] trigger Trigger configuration @ref gpio_trigger + * - GPIO_TRIG_LVL_LOW -- Trigger on low level + * - GPIO_TRIG_LVL_HIGH -- Trigger on high level + * - GPIO_TRIG_EDGE_FALL -- Trigger on falling edges + * - GPIO_TRIG_EDGE_RISE -- Trigger on rising edges + * - GPIO_TRIG_EDGE_BOTH -- Trigger on all edges + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be configure, use bitwise OR '|' to separate them. + */ +void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, + uint8_t gpios) +{ + switch (trigger) { + case GPIO_TRIG_LVL_LOW: + GPIO_IS(gpioport) |= gpios; + GPIO_IEV(gpioport) &= ~gpios; + break; + case GPIO_TRIG_LVL_HIGH: + GPIO_IS(gpioport) |= gpios; + GPIO_IEV(gpioport) |= gpios; + break; + case GPIO_TRIG_EDGE_FALL: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) &= ~gpios; + GPIO_IEV(gpioport) &= ~gpios; + break; + case GPIO_TRIG_EDGE_RISE: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) &= ~gpios; + GPIO_IEV(gpioport) |= gpios; + break; + case GPIO_TRIG_EDGE_BOTH: + GPIO_IS(gpioport) &= ~gpios; + GPIO_IBE(gpioport) |= gpios; + break; + default: + /* Don't do anything */ + break; + } +} + +/** @brief General Purpose Input/Outputs Set a Group of Pins Atomic + * + * Set one or more pins of the given GPIO port to 1 in an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be changed, use bitwise OR '|' to separate them. + */ +void gpio_set(uint32_t gpioport, uint8_t gpios) +{ + GPIO_DATA(gpioport)[gpios] = 0xFF; +} + +/** @brief General Purpose Input/Outputs Clear a Group of Pins Atomic + * + * Clear one or more pins of the given GPIO port to 0 in an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be changed, use bitwise OR '|' to separate them. + */ +void gpio_clear(uint32_t gpioport, uint8_t gpios) +{ + GPIO_DATA(gpioport)[gpios] = 0x0; +} + +/** @brief General Purpose Input/Outputs Read a Group of Pins + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be read, use bitwise OR '|' to separate them. + * + * @return Unsigned int8 value of the pin values. The bit position of the pin + value returned corresponds to the pin number. + */ +uint8_t gpio_get(uint32_t gpioport, uint8_t gpios) +{ + return (uint8_t)GPIO_DATA(gpioport)[gpios]; +} + +/** @brief General Purpose Input/Outputs Toggle a Group of Pins + * + * Toggle one or more pins of the given GPIO port. + * The non-toggled pins are not affected. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be changed, use bitwise OR '|' to separate them. + */ +void gpio_toggle(uint32_t gpioport, uint8_t gpios) +{ + /* The mask makes sure we only toggle the GPIOs we want to */ + GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL; +} + +/** @brief General Purpose Input/Outputs Read from a Port + * + * Read the current value of the given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * + * @return Unsigned int8. The value held in the specified GPIO port. + */ +uint8_t gpio_port_read(uint32_t gpioport) +{ + return (uint8_t)GPIO_DATA(gpioport)[GPIO_ALL]; +} + +/** @brief General Purpose Input/Outputs Write to a Port + * + * Write a value to the given GPIO port. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] data Unsigned int8. The value to be written to the GPIO port. + */ +void gpio_port_write(uint32_t gpioport, uint8_t data) +{ + GPIO_DATA(gpioport)[GPIO_ALL] = data; +} + +/** @brief General Purpose Input/Outputs Enable Interrupts on specified pins + * + * Enable interrupts on the specified GPIO pins. + * + * @note The NVIC must be enabled and properly configured for the interrupt + * to be routed to the CPU. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base) + * @param[in] gpios Pin identifiers @ref gpio_pin_id. + * Pins whose interrupts to enable. + * If multiple pins are to be enable interrupt, + * use bitwise OR '|' to separate them. + */ +void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios) +{ + GPIO_IM(gpioport) |= gpios; +} + +/** @brief General Purpose Input/Outputs Disable interrupts on specified pins + * + * Disable interrupts on the specified GPIO pins. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. + * Pins whose interrupts to disable. + * If multiple pins are to be disable interrupt, + * use bitwise OR '|' to separate them. + */ +void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios) +{ + GPIO_IM(gpioport) &= ~gpios; +} + +/** @brief General Purpose Input/Outputs Unlock The Commit Control + * + * Unlocks the commit control of the given pin or group of pins. If a pin is a + * JTAG/SWD or NMI, the pin may then be reconfigured as a GPIO pin. If the pin + * is not locked by default, this has no effect. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. + * If multiple pins are to be unlock, + * use bitwise OR '|' to separate them. + */ +void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios) +{ + /* Unlock the GPIO_CR register */ + GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE; + /* Enable committing changes */ + GPIO_CR(gpioport) |= gpios; + /* Lock the GPIO_CR register */ + GPIO_LOCK(gpioport) = ~GPIO_LOCK_UNLOCK_CODE; +} + +/** @brief General Purpose Input/Outputs Determine if interrupt is generated + * by the given pin + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Source pin identifiers @ref gpio_pin_id. + * If multiple pins are to be check, + * use bitwise OR '|' to separate them. + * + * @return Unsigned int8. The bit position of the pin + value returned corresponds to the pin number. + */ +uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios) +{ + return GPIO_MIS(gpioport) & gpios; +} + +/** @brief General Purpose Input/Outputs Mark Interrupt as Serviced + * + * After an interrupt is services, its flag must be cleared. If the flag is not + * cleared, then execution will jump back to the start of the ISR after the ISR + * returns. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are + * to be clear interrupt flag, use bitwise OR '|' to separate them. + */ +void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios) +{ + GPIO_ICR(gpioport) |= gpios; +} diff --git a/lib/msp432/e4/systemcontrol.c b/lib/msp432/e4/systemcontrol.c index 8a441175..01a20739 100644 --- a/lib/msp432/e4/systemcontrol.c +++ b/lib/msp432/e4/systemcontrol.c @@ -44,9 +44,9 @@ * @param[in] periph ::msp432_periph Peripheral block */ void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, - enum msp432_periph periph) + enum msp432_periph periph) { - _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph); + _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -56,9 +56,9 @@ void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode, * @param[in] periph ::msp432_periph Peripheral block */ void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, - enum msp432_periph periph) + enum msp432_periph periph) { - _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph); + _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -68,7 +68,7 @@ void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode, */ void sysctl_periph_reset(enum msp432_periph periph) { - _SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph); + _SYSCTL_REG((uint32_t) &SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -78,7 +78,7 @@ void sysctl_periph_reset(enum msp432_periph periph) */ void sysctl_periph_clear_reset(enum msp432_periph periph) { - _SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph); + _SYSCTL_REG((uint32_t) &SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph); } /*----------------------------------------------------------------------------*/ @@ -88,10 +88,10 @@ void sysctl_periph_clear_reset(enum msp432_periph periph) */ bool sysctl_periph_is_present(enum msp432_periph periph) { - uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PPWD, periph); - uint32_t mask = _SYSCTL_BIT(periph); + uint32_t reg32 = _SYSCTL_REG((uint32_t) &SYSCTL_PPWD, periph); + uint32_t mask = _SYSCTL_BIT(periph); - return ((reg32 & mask) != 0); + return((reg32 & mask) != 0); } /*----------------------------------------------------------------------------*/ @@ -101,10 +101,10 @@ bool sysctl_periph_is_present(enum msp432_periph periph) */ bool sysctl_periph_is_ready(enum msp432_periph periph) { - uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PRWD, periph); - uint32_t mask = _SYSCTL_BIT(periph); + uint32_t reg32 = _SYSCTL_REG((uint32_t) &SYSCTL_PRWD, periph); + uint32_t mask = _SYSCTL_BIT(periph); - return ((reg32 & mask) != 0); + return((reg32 & mask) != 0); } /*----------------------------------------------------------------------------*/ @@ -117,13 +117,13 @@ bool sysctl_periph_is_ready(enum msp432_periph periph) * is powered and receives a clock regardless of the value of power mode. */ void sysctl_periph_set_power_state(enum msp432_power_mode power_mode, - enum msp432_periph periph) + enum msp432_periph periph) { - if(power_mode == POWER_ENABLE) { - _SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph); - } else { - _SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph); - } + if (power_mode == POWER_ENABLE) { + _SYSCTL_REG((uint32_t) &SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph); + } else { + _SYSCTL_REG((uint32_t) &SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph); + } } #undef _SYSCTL_REG diff --git a/lib/sam/3a/Makefile b/lib/sam/3a/Makefile index 5b9293d7..61183ae4 100644 --- a/lib/sam/3a/Makefile +++ b/lib/sam/3a/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_sam3a SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3A @@ -31,7 +29,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3a3u3x.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/3n/Makefile b/lib/sam/3n/Makefile index 2baa2ee2..167e9093 100644 --- a/lib/sam/3n/Makefile +++ b/lib/sam/3n/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_sam3n SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3N @@ -31,7 +29,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3n3s.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3n3s.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../cm3:../common diff --git a/lib/sam/3s/Makefile b/lib/sam/3s/Makefile index 4ec0b12b..e20931e2 100644 --- a/lib/sam/3s/Makefile +++ b/lib/sam/3s/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_sam3s SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3S @@ -32,7 +30,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3n3s.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3n3s.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/3u/Makefile b/lib/sam/3u/Makefile index 4b0ab0ce..5dce7e92 100644 --- a/lib/sam/3u/Makefile +++ b/lib/sam/3u/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_sam3u SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3U @@ -32,7 +30,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3a3u3x.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/3x/Makefile b/lib/sam/3x/Makefile index c3dbc02d..5fa4c419 100644 --- a/lib/sam/3x/Makefile +++ b/lib/sam/3x/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_sam3x SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM3X @@ -31,7 +29,10 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o + +OBJS += gpio_common_all.o gpio_common_3a3u3x.o +OBJS += pmc.o +OBJS += usart_common_all.o usart_common_3.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/4l/Makefile b/lib/sam/4l/Makefile index 42a507f0..fd8d825b 100644 --- a/lib/sam/4l/Makefile +++ b/lib/sam/4l/Makefile @@ -18,18 +18,21 @@ LIBNAME = libopencm3_sam4l SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi FP_FLAGS ?= -msoft-float - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAM4L TGT_CFLAGS += $(DEBUG_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adcife.o gpio.o scif.o pm.o usart_common_all.o usart.o + +OBJS += adcife.o +OBJS += gpio.o +OBJS += pm.o +OBJS += scif.o +OBJS += usart_common_all.o usart.o VPATH += ../../usb:../../cm3:../common diff --git a/lib/sam/d/Makefile b/lib/sam/d/Makefile index 0a2a5c89..380ade30 100644 --- a/lib/sam/d/Makefile +++ b/lib/sam/d/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_samd SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os -Wall -Wextra -I../../../include -fno-common \ -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) -Wstrict-prototypes \ -ffunction-sections -fdata-sections -MD -DSAMD diff --git a/lib/stm32/can.c b/lib/stm32/can.c index 37599c9b..f404a4a7 100644 --- a/lib/stm32/can.c +++ b/lib/stm32/can.c @@ -464,7 +464,7 @@ void can_fifo_release(uint32_t canport, uint8_t fifo) @param[out] fmi Unsigned int8 pointer. ID of the matched filter. @param[out] length Unsigned int8 pointer. Length of message payload. @param[out] data Unsigned int8[]. Message payload data. -@param[out] timestamp. Pointer to store the message timestamp. +@param[out] timestamp Pointer to store the message timestamp. Only valid on time triggered CAN. Use NULL to ignore. */ void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, diff --git a/lib/stm32/common/adc_common_f47.c b/lib/stm32/common/adc_common_f47.c new file mode 100644 index 00000000..50abf2b2 --- /dev/null +++ b/lib/stm32/common/adc_common_f47.c @@ -0,0 +1,124 @@ +/** @addtogroup adc_file ADC peripheral API +@ingroup peripheral_apis + +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies <ksarkies@internode.on.net> + +@date 30 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <libopencm3/stm32/adc.h> + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for a Single Channel + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) +{ + uint32_t reg32; + + if (channel < 10) { + reg32 = ADC_SMPR2(adc); + reg32 &= ~(0x7 << (channel * 3)); + reg32 |= (time << (channel * 3)); + ADC_SMPR2(adc) = reg32; + } else { + reg32 = ADC_SMPR1(adc); + reg32 &= ~(0x7 << ((channel - 10) * 3)); + reg32 |= (time << ((channel - 10) * 3)); + ADC_SMPR1(adc) = reg32; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set the Sample Time for All Channels + +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. + +@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg + * NOTE Common with f1, f2 and f37x +*/ +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) +{ + uint8_t i; + uint32_t reg32 = 0; + + for (i = 0; i <= 9; i++) { + reg32 |= (time << (i * 3)); + } + ADC_SMPR2(adc) = reg32; + + for (i = 10; i <= 17; i++) { + reg32 |= (time << ((i - 10) * 3)); + } + ADC_SMPR1(adc) = reg32; +} + + +/*---------------------------------------------------------------------------*/ +/** @brief ADC Set Dual/Triple Mode + +The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave +arrangement. This setting is applied to ADC1 only. + +The various modes possible are described in the reference manual. + +@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode +*/ +void adc_set_multi_mode(uint32_t mode) +{ + ADC_CCR |= mode; +} + + +/** Enable The VBat Sensor. + * This enables the battery voltage measurements on ADC1 channel 18. On + * STM32F42x and STM32F43x, this must be disabled when the temperature sensor + * is enabled. If both are enabled, only the VBat conversion is performed. + */ +void adc_enable_vbat_sensor(void) +{ + ADC_CCR |= ADC_CCR_VBATE; +} + +/** Disable The VBat Sensor. + * Disabling this will reduce power consumption from the battery voltage + * measurement. + */ +void adc_disable_vbat_sensor(void) +{ + ADC_CCR &= ~ADC_CCR_VBATE; +} + +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/f4/adc.c b/lib/stm32/common/adc_common_v1_multi.c index 020db884..eb368cde 100644 --- a/lib/stm32/f4/adc.c +++ b/lib/stm32/common/adc_common_v1_multi.c @@ -14,10 +14,14 @@ registers. However all the A/D converters share a common clock which is prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. -Each A/D converter has up to 19 channels: -@li On ADC1 the analog channels 16 is internally connected to the temperature -sensor, channel 17 to V<sub>REFINT</sub>, and channel 18 to V<sub>BAT</sub>. -@li On ADC2 and ADC3 the analog channels 16 - 18 are not used. +Each A/D converter has multiple channels, not all of which might be available +externally. Internal channels can be used for the the temperature sensor, +VBat monitoring, and the internal reference voltage VREFINT. Consult the +Reference manual for the specifics of your part. +@sa ADC_MAX_CHANNELS +@sa ADC_CHANNEL_TEMP +@sa ADC_CHANNEL_VREF +@sa ADC_CHANNEL_VBAT The conversions can occur as a one-off conversion whereby the process stops once conversion is complete. The conversions can also be continuous wherein a @@ -36,7 +40,7 @@ Injected conversions allow a second group of channels to be converted separately from the regular group. An interrupt can be set to occur at the end of conversion, which occurs after all channels have been scanned. -@section adc_f4_api_ex Basic ADC Handling API. +@section adc_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock and ADC, reset ADC and set the prescaler divider. Set the sample time to a @@ -83,61 +87,6 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for a Single Channel - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref -adc_channel -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time) -{ - uint32_t reg32; - - if (channel < 10) { - reg32 = ADC_SMPR2(adc); - reg32 &= ~(0x7 << (channel * 3)); - reg32 |= (time << (channel * 3)); - ADC_SMPR2(adc) = reg32; - } else { - reg32 = ADC_SMPR1(adc); - reg32 &= ~(0x7 << ((channel - 10) * 3)); - reg32 |= (time << ((channel - 10) * 3)); - ADC_SMPR1(adc) = reg32; - } -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Set the Sample Time for All Channels - -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same -for all channels. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg - * NOTE Common with f1, f2 and f37x -*/ - -void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) -{ - uint8_t i; - uint32_t reg32 = 0; - - for (i = 0; i <= 9; i++) { - reg32 |= (time << (i * 3)); - } - ADC_SMPR2(adc) = reg32; - - for (i = 10; i <= 17; i++) { - reg32 |= (time << ((i - 10) * 3)); - } - ADC_SMPR1(adc) = reg32; -} /*---------------------------------------------------------------------------*/ /** @brief ADC Power On @@ -157,11 +106,9 @@ void adc_power_on(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale - -The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. - -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref -adc_ccr_adcpre +The ADC clock can be prescaled. +The Clock sources and scaler values are part specific. +@param[in] prescale Prescale value for ADC Clock @ref adc_ccr_adcpre */ void adc_set_clk_prescale(uint32_t prescale) @@ -171,22 +118,6 @@ void adc_set_clk_prescale(uint32_t prescale) } /*---------------------------------------------------------------------------*/ -/** @brief ADC Set Dual/Triple Mode - -The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave -arrangement. This setting is applied to ADC1 only. - -The various modes possible are described in the reference manual. - -@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode -*/ - -void adc_set_multi_mode(uint32_t mode) -{ - ADC_CCR |= mode; -} - -/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels This enables an external trigger for set of defined regular channels, and sets @@ -403,8 +334,8 @@ bool adc_awd(uint32_t adc) /*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor -This enables both the sensor and the reference voltage measurements on ADC1 -channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is +This enables both the sensor and the reference voltage measurements on ADC1. +On STM32F42x and STM32F43x, the temperature sensor is connected to ADC1 channel 18, the same as VBat. If both are enabled, only the VBat conversion is performed. */ @@ -426,23 +357,4 @@ void adc_disable_temperature_sensor(void) ADC_CCR &= ~ADC_CCR_TSVREFE; } -/** Enable The VBat Sensor. - * This enables the battery voltage measurements on ADC1 channel 18. On - * STM32F42x and STM32F43x, this must be disabled when the temperature sensor - * is enabled. If both are enabled, only the VBat conversion is performed. - */ -void adc_enable_vbat_sensor(void) -{ - ADC_CCR |= ADC_CCR_VBATE; -} - -/** Disable The VBat Sensor. - * Disabling this will reduce power consumption from the battery voltage - * measurement. - */ -void adc_disable_vbat_sensor(void) -{ - ADC_CCR &= ~ADC_CCR_VBATE; -} - /**@}*/ diff --git a/lib/stm32/common/adc_common_v2.c b/lib/stm32/common/adc_common_v2.c index fb22d273..7fd26476 100644 --- a/lib/stm32/common/adc_common_v2.c +++ b/lib/stm32/common/adc_common_v2.c @@ -155,7 +155,7 @@ void adc_power_off(uint32_t adc) */ void adc_calibrate_async(uint32_t adc) { - ADC_CR(adc) = ADC_CR_ADCAL; + ADC_CR(adc) |= ADC_CR_ADCAL; } /** @@ -389,4 +389,24 @@ void adc_start_conversion_regular(uint32_t adc) ADC_CR(adc) |= ADC_CR_ADSTART; } +/** @brief Enable circular mode for DMA transfers + * + * For this to work it needs to be ebabled on the DMA side as well. + * + * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) + */ +void adc_enable_dma_circular_mode(uint32_t adc) +{ + ADC_CFGR1(adc) |= ADC_CFGR1_DMACFG; +} + +/** @brief Disable circular mode for DMA transfers + * + * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) + */ +void adc_disable_dma_circular_mode(uint32_t adc) +{ + ADC_CFGR1(adc) &= ~ADC_CFGR1_DMACFG; +} + /**@}*/ diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c index a8a0daf8..5d1893c1 100644 --- a/lib/stm32/common/dac_common_all.c +++ b/lib/stm32/common/dac_common_all.c @@ -1,12 +1,13 @@ -/** @addtogroup dac_file +/** @addtogroup dac_file DAC peripheral API + * @ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net This library supports the Digital to Analog Conversion System in the -STM32F series of ARM Cortex Microcontrollers by ST Microelectronics. +STM32 series of ARM Cortex Microcontrollers by ST Microelectronics. -The DAC is present only in a limited set of devices, notably some -of the connection line, high density and XL devices. +The DAC peripheral found on many of the devices in the STM32 lineup, +sometimes with only one channel, but normally with two channels. Two DAC channels are available, however unlike the ADC channels these are separate DAC devices controlled by the same register block. diff --git a/lib/stm32/common/dma2d_common_f47.c b/lib/stm32/common/dma2d_common_f47.c new file mode 100644 index 00000000..013292a0 --- /dev/null +++ b/lib/stm32/common/dma2d_common_f47.c @@ -0,0 +1,33 @@ +/** @defgroup dma2d_file DMA2D peripheral API + * + * @ingroup peripheral_apis + * + * @version 1.0.0 + * + * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx + * series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <libopencm3/stm32/common/dma2d_common_f47.h> + +/**@{*/ + +/**@}*/ diff --git a/lib/stm32/common/dma_common_csel.c b/lib/stm32/common/dma_common_csel.c new file mode 100644 index 00000000..4cf1fca9 --- /dev/null +++ b/lib/stm32/common/dma_common_csel.c @@ -0,0 +1,46 @@ +/** @addtogroup dma_file DMA peripheral API +@ingroup peripheral_apis + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/stm32/dma.h> + +/*---------------------------------------------------------------------------*/ +/** @brief DMA Channel Set Request Selection + +Set DMA request mapping selection for given channel. Refer to datasheet for channel +request mapping tables. + +@param[in] dma DMA controller base address: DMA1 or DMA2 +@param[in] channel Channel number: 1-7 for DMA1 or 1-5 for DMA2 +@param[in] request DMA request mapping. +*/ + +void dma_set_channel_request(uint32_t dma, uint8_t channel, uint8_t request) +{ + uint32_t reg32 = DMA_CSELR(dma) & ~(DMA_CSELR_CxS_MASK << DMA_CSELR_CxS_SHIFT(channel)); + DMA_CSELR(dma) = reg32 | ((DMA_CSELR_CxS_MASK & request) << DMA_CSELR_CxS_SHIFT(channel)); +} + +/**@}*/ diff --git a/lib/stm32/common/dma_common_f24.c b/lib/stm32/common/dma_common_f24.c index d706674f..2c61b548 100644 --- a/lib/stm32/common/dma_common_f24.c +++ b/lib/stm32/common/dma_common_f24.c @@ -1,4 +1,5 @@ -/** @addtogroup dma_file +/** @addtogroup dma_file DMA peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net> diff --git a/lib/stm32/common/dma_common_l1f013.c b/lib/stm32/common/dma_common_l1f013.c index 47abfa24..2f9190a4 100644 --- a/lib/stm32/common/dma_common_l1f013.c +++ b/lib/stm32/common/dma_common_l1f013.c @@ -1,4 +1,5 @@ -/** @addtogroup dma_file +/** @addtogroup dma_file DMA peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org> diff --git a/lib/stm32/f0/pwr.c b/lib/stm32/common/dsi_common_f47.c index 8a3ffd2e..17d875d7 100644 --- a/lib/stm32/f0/pwr.c +++ b/lib/stm32/common/dsi_common_f47.c @@ -1,15 +1,12 @@ -/** @defgroup pwr_file PWR +/** @defgroup dsi_file DSI peripheral API * - * @ingroup STM32F0xx - * - * @brief <b>libopencm3 STM32F0xx Power Control</b> + * @ingroup peripheral_apis * * @version 1.0.0 * - * @date 11 July 2013 - * - * This library supports the power control system for the - * STM32F0 series of ARM Cortex Microcontrollers by ST Microelectronics. + * This library supports the Display Serial Interface Host and Wrapper in + * the STM32F4xx and STM32F7xx series of ARM Cortex Microcontrollers by + * ST Microelectronics. * * LGPL License Terms @ref lgpl_license */ @@ -30,9 +27,8 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/**@{*/ +#include <libopencm3/stm32/common/dsi_common_f47.h> -#include <libopencm3/stm32/pwr.h> +/**@{*/ /**@}*/ - diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c index d2135f29..7135a964 100644 --- a/lib/stm32/common/exti_common_all.c +++ b/lib/stm32/common/exti_common_all.c @@ -1,3 +1,6 @@ +/** @addtogroup exti_file EXTI peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * @@ -17,7 +20,7 @@ * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see <http://www.gnu.org/licenses/>. * - * This provides the code for the "next gen" EXTI block provided in F2/F4/L1 + * This provides the code for the "next gen" EXTI block provided in F2/F4/F7/L1 * devices. (differences only in the source selection) */ /**@{*/ @@ -25,8 +28,17 @@ #include <libopencm3/stm32/exti.h> #include <libopencm3/stm32/gpio.h> -#if !defined(AFIO_BASE) -# include <libopencm3/stm32/syscfg.h> + +#if defined(EXTI_EXTICR) + #define EXTICR_SELECTION_FIELDSIZE EXTI_EXTICR_FIELDSIZE + #define EXTICR_SELECTION_REG(x) EXTI_EXTICR(x) +#elif defined(AFIO_EXTICR) + #define EXTICR_SELECTION_FIELDSIZE AFIO_EXTICR_FIELDSIZE + #define EXTICR_SELECTION_REG(x) AFIO_EXTICR(x) +#else + #include <libopencm3/stm32/syscfg.h> + #define EXTICR_SELECTION_FIELDSIZE SYSCFG_EXTICR_FIELDSIZE + #define EXTICR_SELECTION_REG(x) SYSCFG_EXTICR(x) #endif void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig) @@ -71,7 +83,12 @@ void exti_disable_request(uint32_t extis) */ void exti_reset_request(uint32_t extis) { +#if defined(EXTI_RPR1) && defined(EXTI_FPR1) + EXTI_RPR1 = extis; + EXTI_FPR1 = extis; +#else EXTI_PR = extis; +#endif } /* @@ -79,7 +96,11 @@ void exti_reset_request(uint32_t extis) * */ uint32_t exti_get_flag_status(uint32_t exti) { +#if defined(EXTI_RPR1) && defined(EXTI_FPR1) + return (EXTI_RPR1 & exti) | (EXTI_FPR1 & exti); +#else return EXTI_PR & exti; +#endif } /* @@ -96,7 +117,7 @@ void exti_select_source(uint32_t exti, uint32_t gpioport) continue; } - uint32_t bits = 0, mask = 0x0F; + uint32_t bits = 0; switch (gpioport) { case GPIOA: @@ -148,16 +169,11 @@ void exti_select_source(uint32_t exti, uint32_t gpioport) #endif } - uint8_t shift = (uint8_t)(4 * (line % 4)); + uint8_t shift = (uint8_t)(EXTICR_SELECTION_FIELDSIZE * (line % 4)); + uint32_t mask = ((1 << EXTICR_SELECTION_FIELDSIZE) - 1) << shift; uint32_t reg = line / 4; - bits <<= shift; - mask <<= shift; -#if defined(AFIO_BASE) - AFIO_EXTICR(reg) = (AFIO_EXTICR(reg) & ~mask) | bits; -#else - SYSCFG_EXTICR(reg) = (SYSCFG_EXTICR(reg) & ~mask) | bits; -#endif + EXTICR_SELECTION_REG(reg) = (EXTICR_SELECTION_REG(reg) & ~mask) | (bits << shift); }; } /**@}*/ diff --git a/lib/stm32/common/flash_common_all.c b/lib/stm32/common/flash_common_all.c index 98821796..b369d903 100644 --- a/lib/stm32/common/flash_common_all.c +++ b/lib/stm32/common/flash_common_all.c @@ -1,5 +1,5 @@ -/** @addtogroup flash_file - * +/** @addtogroup flash_file FLASH peripheral API + * @ingroup peripheral_apis */ /* diff --git a/lib/stm32/common/flash_common_f.c b/lib/stm32/common/flash_common_f.c index 291fad9b..0b867def 100644 --- a/lib/stm32/common/flash_common_f.c +++ b/lib/stm32/common/flash_common_f.c @@ -43,3 +43,4 @@ void flash_clear_eop_flag(void) FLASH_SR |= FLASH_SR_EOP; } +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/common/flash_common_idcache.c b/lib/stm32/common/flash_common_idcache.c index ebfdd0ad..c7da2066 100644 --- a/lib/stm32/common/flash_common_idcache.c +++ b/lib/stm32/common/flash_common_idcache.c @@ -55,4 +55,5 @@ void flash_icache_reset(void) FLASH_ACR |= FLASH_ACR_ICRST; } +/**@}*/ diff --git a/lib/stm32/common/flash_common_l01.c b/lib/stm32/common/flash_common_l01.c index 9eceb45f..9fb1212b 100644 --- a/lib/stm32/common/flash_common_l01.c +++ b/lib/stm32/common/flash_common_l01.c @@ -89,6 +89,14 @@ void flash_lock(void) flash_lock_pecr(); } +/** @brief Unlock RUN_PD bit from FLASH_ACR register. + */ +void flash_unlock_acr(void) +{ + FLASH_PDKEYR = FLASH_PDKEYR_PDKEY1; + FLASH_PDKEYR = FLASH_PDKEYR_PDKEY2; +} + /** @brief Write a word to eeprom * * @param address assumed to be in the eeprom space, no checking diff --git a/lib/stm32/f4/fmc.c b/lib/stm32/common/fmc_common_f47.c index 1c30dd67..1a5bc027 100644 --- a/lib/stm32/f4/fmc.c +++ b/lib/stm32/common/fmc_common_f47.c @@ -1,3 +1,11 @@ +/** @addtogroup fmc_file FMC peripheral API +@ingroup peripheral_apis + +@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net + +This library supports the Flexible Memory Controller in the STM32F4xx and +STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. +*/ /* * * This file is part of the libopencm3 project. @@ -21,6 +29,8 @@ #include <stdint.h> #include <libopencm3/stm32/fsmc.h> +/**@{*/ + /* * Install various timing values into the correct place in the * SDRAM Timing Control Register format. @@ -97,3 +107,5 @@ sdram_command(enum fmc_sdram_bank bank, /* Send the next command */ FMC_SDCMR = tmp_reg; } + +/**@}*/ diff --git a/lib/stm32/common/gpio_common_all.c b/lib/stm32/common/gpio_common_all.c index 98d15ad4..9602a999 100644 --- a/lib/stm32/common/gpio_common_all.c +++ b/lib/stm32/common/gpio_common_all.c @@ -1,4 +1,5 @@ -/** @addtogroup gpio_file +/** @addtogroup gpio_file GPIO peripheral API + * @ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de> diff --git a/lib/stm32/common/hash_common_f24.c b/lib/stm32/common/hash_common_f24.c index 24d489c1..b5046dd8 100644 --- a/lib/stm32/common/hash_common_f24.c +++ b/lib/stm32/common/hash_common_f24.c @@ -1,4 +1,6 @@ -/** @addtogroup hash_file +/** @addtogroup hash_file HASH Peripheral API + * + * @ingroup peripheral_apis * * @author @htmlonly © @endhtmlonly 2013 * Mikhail Avkhimenia <mikhail@avkhimenia.net> @@ -145,7 +147,6 @@ void hash_digest() Makes a copy of the resulting hash. @param[out] data unsigned int32. Hash 4\5 words long depending on the algorithm. -@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm */ void hash_get_result(uint32_t *data) diff --git a/lib/stm32/common/iwdg_common_all.c b/lib/stm32/common/iwdg_common_all.c index f2b1c1d8..44b3b9b3 100644 --- a/lib/stm32/common/iwdg_common_all.c +++ b/lib/stm32/common/iwdg_common_all.c @@ -70,45 +70,44 @@ loading a previous value. @param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog reset until a system reset is issued. */ - void iwdg_set_period_ms(uint32_t period) { - uint32_t count, prescale, reload, exponent; - - /* Set the count to represent ticks of the 32kHz LSI clock */ - count = (period << 5); - - /* Strip off the first 12 bits to get the prescale value required */ - prescale = (count >> 12); - if (prescale > 256) { - exponent = IWDG_PR_DIV256; reload = COUNT_MASK; - } else if (prescale > 128) { - exponent = IWDG_PR_DIV256; reload = (count >> 8); - } else if (prescale > 64) { - exponent = IWDG_PR_DIV128; reload = (count >> 7); - } else if (prescale > 32) { - exponent = IWDG_PR_DIV64; reload = (count >> 6); - } else if (prescale > 16) { - exponent = IWDG_PR_DIV32; reload = (count >> 5); - } else if (prescale > 8) { - exponent = IWDG_PR_DIV16; reload = (count >> 4); - } else if (prescale > 4) { - exponent = IWDG_PR_DIV8; reload = (count >> 3); - } else { - exponent = IWDG_PR_DIV4; reload = (count >> 2); - } + const int PRESCALER_MAX = 6; + uint8_t prescale = 0; - /* Avoid the undefined situation of a zero count */ + /* Set the count to represent ticks of 8kHz clock (the 32kHz LSI clock + * divided by 4 = lowest prescaler setting) + */ + uint32_t count = period << 3; + + /* Prevent underflow */ if (count == 0) { count = 1; } + /* Shift count while increasing prescaler as many times as needed to + * fit into IWDG_RLR + */ + while ((count - 1) >> COUNT_LENGTH) { + count >>= 1; + prescale++; + } + + /* IWDG_RLR actually holds count - 1 */ + count--; + + /* Clamp to max possible period */ + if (prescale > PRESCALER_MAX) { + count = COUNT_MASK; + prescale = PRESCALER_MAX; + } + while (iwdg_prescaler_busy()); IWDG_KR = IWDG_KR_UNLOCK; - IWDG_PR = exponent; + IWDG_PR = prescale; while (iwdg_reload_busy()); IWDG_KR = IWDG_KR_UNLOCK; - IWDG_RLR = (reload & COUNT_MASK); + IWDG_RLR = count & COUNT_MASK; } /*---------------------------------------------------------------------------*/ diff --git a/lib/stm32/common/lptimer_common_all.c b/lib/stm32/common/lptimer_common_all.c new file mode 100644 index 00000000..1dc4e0ab --- /dev/null +++ b/lib/stm32/common/lptimer_common_all.c @@ -0,0 +1,294 @@ +/** @addtogroup lptimer_file LPTIM peripheral API + * @ingroup peripheral_apis + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * @date 2 July 2019 + * + * LGPL License Terms @ref lgpl_license + * + * @section lptim_api_ex Basic LPTIMER handling API. + * + * Example: LPTIM1 with 2x clock prescaler, from internal clock (LSE), irq on match and reload. + * + * @code + * + * rcc_set_peripheral_clk_sel(LPTIM1, RCC_CCIPR_LPTIM1SEL_LSE); + * + * rcc_periph_clock_enable(RCC_LPTIM1); + * + * lptimer_set_internal_clock_source(LPTIM1); + * lptimer_enable_trigger(LPTIM1, LPTIM_CFGR_TRIGEN_SW); + * lptimer_set_prescaler(LPTIM1, LPTIM_CFGR_PRESC_2); + * + * lptimer_enable(LPTIM1); + * + * lptimer_set_period(LPTIM1, 0xffff); + * lptimer_set_compare(LPTIM1, 1234); + * + * lptimer_enable_irq(LPTIM1, LPTIM_IER_ARRMIE | LPTIM_IER_CMPMIE); + * nvic_enable_irq(NVIC_LPTIM1_IRQ); + * + * lptimer_start_counter(LPTIM1, LPTIM_CR_CNTSTRT); + * + * @endcode + * + * Note: LPTIM internal clock source selection is device specific, see clock tree + * and rcc section of reference manual. + * + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/stm32/lptimer.h> + +/** @brief Set lptimer Counter + * + * Set the value of a lptimer counter. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] count Counter value. +*/ +void lptimer_set_counter(uint32_t lptimer_peripheral, uint16_t count) +{ + LPTIM_CNT(lptimer_peripheral) = count; +} + +/** @brief Read lptimer Counter + * + * Read back the value of lptimer counter. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @returns Counter value. + */ +uint16_t lptimer_get_counter(uint32_t lptimer_peripheral) +{ + return LPTIM_CNT(lptimer_peripheral); +} + +/** @brief Clear lptimer Status Flag. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] flag Status Register clear flag (@ref lptim_icr) + */ +void lptimer_clear_flag(uint32_t lptimer_peripheral, uint32_t flag) +{ + LPTIM_ICR(lptimer_peripheral) = flag; +} + +/** @brief Read lptimer Status Flag. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] flag Status Register flag (@ref lptim_isr) + * @returns flag set. + */ +bool lptimer_get_flag(uint32_t lptimer_peripheral, uint32_t flag) +{ + return (LPTIM_ISR(lptimer_peripheral) & flag); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable lptimer interrupts. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] irq Logical or of all interrupt enable bits to be set (@ref lptim_ier) + */ +void lptimer_enable_irq(uint32_t lptimer_peripheral, uint32_t irq) +{ + LPTIM_IER(lptimer_peripheral) |= irq; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable lptimer Interrupts. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] irq Logical or of all interrupt enable bits to be cleared (@ref lptim_ier) + */ +void lptimer_disable_irq(uint32_t lptimer_peripheral, uint32_t irq) +{ + LPTIM_IER(lptimer_peripheral) &= ~irq; +} + +/** @brief Enable lptimer. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_enable(uint32_t lptimer_peripheral) +{ + LPTIM_CR(lptimer_peripheral) |= LPTIM_CR_ENABLE; +} + +/** @brief Disable lptimer. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_disable(uint32_t lptimer_peripheral) +{ + LPTIM_CR(lptimer_peripheral) &= ~LPTIM_CR_ENABLE; +} + +/** @brief Start lptimer in a given mode. + * + * Starts the timer in specified mode - Either Single (@ref LPTIM_CR_SNGSTRT) or + * Continuous mode (@ref LPTIM_CR_CNTSTRT). In Single mode, the timer will stop at + * next match on compare or period value. + * If LPTIM_CR_SNGSTRT is set while timer is started in countious mode, it + * will stop at next match on compare or period value. + * If Software trigger is disabled, start will be delayed until programmed + * triggers is detected. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] mode lptimer start mode (@ref LPTIM_CR_SNGSTRT or @ref LPTIM_CR_CNTSTRT) + */ +void lptimer_start_counter(uint32_t lptimer_peripheral, uint32_t mode) +{ + LPTIM_CR(lptimer_peripheral) |= mode; +} + +/** @brief Set lptimer clock prescaler. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] prescaler Clock prescaler (@ref lptim_cfgr_presc) + */ +void lptimer_set_prescaler(uint32_t lptimer_peripheral, uint32_t prescaler) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_PRESC_MASK << LPTIM_CFGR_PRESC_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | prescaler; +} + +/** @brief Enable lptimer External Trigger + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel) + */ +void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_TRIGEN_MASK << LPTIM_CFGR_TRIGEN_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | trigen; +} + +/** @brief Select lptimer Trigger Source + * + * Select timer external trigger source. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel) + */ +void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source) +{ + uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral); + reg32 &= ~(LPTIM_CFGR_TRIGSEL_MASK << LPTIM_CFGR_TRIGSEL_SHIFT); + LPTIM_CFGR(lptimer_peripheral) = reg32 | trigger_source; +} + +/** @brief Set lptimer counter Compare Value + * + * Set the timer compare value. Must only be set with timer enabled. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] compare_value Compare value. + */ +void lptimer_set_compare(uint32_t lptimer_peripheral, uint16_t compare_value) +{ + LPTIM_CMP(lptimer_peripheral) = compare_value; +} + +/** @brief Set lptimer period + * + * Set the timer period in the auto-reload register. Must only be set with timer + * enabled. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + * @param[in] period_value Autoreload value. Must be greater that CMP value. + */ +void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value) +{ + LPTIM_ARR(lptimer_peripheral) = period_value; +} + +/** @brief Enable lptimer Preload mode. + * + * Enable lptimer preload mode, delaying update of period and compare registers + * to the end of current period. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_enable_preload(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_PRELOAD; +} + +/** @brief Disable lptimer Preload mode. + * + * Disable lptimer preload mode, ensureing updated period and compare registers + * values are taken in account immediatly. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_disable_preload(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_PRELOAD; +} + + +/** @brief Set lptimer Internal Clock source + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_internal_clock_source(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_CKSEL; +} + +/** @brief Set lptimer External Clock source + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_external_clock_source(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_CKSEL; +} + +/** @brief Set lptimer Waveform Output Polarity High + * + * Set lptimer waveform output to reflect compare result between LPTIN_CNT + * and LPTIM_CMP. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_WAVPOL; +} + +/** @brief Set lptimer Waveform Output Polarity Low + * + * Set lptimer waveform output to reflect the inverse of the compare result + * between LPTIN_CNT and LPTIM_CMP. + * + * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base) + */ +void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral) +{ + LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_WAVPOL; +} + +/**@}*/ diff --git a/lib/stm32/f4/ltdc.c b/lib/stm32/common/ltdc_common_f47.c index 83a13961..3255f356 100644 --- a/lib/stm32/f4/ltdc.c +++ b/lib/stm32/common/ltdc_common_f47.c @@ -1,8 +1,6 @@ -/** @defgroup ltdc_file LTDC +/** @defgroup ltdc_file LTDC peripheral API * - * @ingroup STM32F4xx - * - * @brief <b>libopencm3 STM32F4xx LTDC</b> + * @ingroup peripheral_apis * * @version 1.0.0 * @@ -11,12 +9,8 @@ * * @date 5 December 2014 * - * This library supports the LCD controller (LTDC) in the STM32F4 - * series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * For the STM32F4xx, LTDC is described in LCD-TFT Controller (LTDC) - * section 16 of the STM32F4xx Reference Manual (RM0090,Rev8). - * + * This library supports the LCD controller (LTDC) in the STM32F4xx and + * STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics. * * LGPL License Terms @ref lgpl_license */ @@ -40,7 +34,9 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -#include <libopencm3/stm32/f4/ltdc.h> +/**@{*/ + +#include <libopencm3/stm32/common/ltdc_common_f47.h> void ltdc_set_tft_sync_timings(uint16_t sync_width, uint16_t sync_height, uint16_t h_back_porch, uint16_t v_back_porch, @@ -87,3 +83,5 @@ void ltdc_setup_windowing(uint8_t layer_number, (v_back_porch << 0); } +/**@}*/ + diff --git a/lib/stm32/common/pwr_common_v1.c b/lib/stm32/common/pwr_common_v1.c index 820dfcab..d4c44b3d 100644 --- a/lib/stm32/common/pwr_common_v1.c +++ b/lib/stm32/common/pwr_common_v1.c @@ -1,4 +1,5 @@ -/** @addtogroup pwr_file +/** @addtogroup pwr_file PWR peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net> diff --git a/lib/stm32/common/pwr_common_v2.c b/lib/stm32/common/pwr_common_v2.c index b895e7d0..940b29e5 100644 --- a/lib/stm32/common/pwr_common_v2.c +++ b/lib/stm32/common/pwr_common_v2.c @@ -1,4 +1,5 @@ -/** @addtogroup pwr_file +/** @addtogroup pwr_file PWR peripheral API + * @ingroup peripheral_apis * * @author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au> */ diff --git a/lib/stm32/common/rcc_common_all.c b/lib/stm32/common/rcc_common_all.c index e338dcea..5852b675 100644 --- a/lib/stm32/common/rcc_common_all.c +++ b/lib/stm32/common/rcc_common_all.c @@ -1,3 +1,6 @@ +/** @addtogroup rcc_file RCC peripheral API + * @ingroup peripheral_apis + */ /* * This file is part of the libopencm3 project. * diff --git a/lib/stm32/common/rng_common_v1.c b/lib/stm32/common/rng_common_v1.c index 7ed1e635..e26b6880 100644 --- a/lib/stm32/common/rng_common_v1.c +++ b/lib/stm32/common/rng_common_v1.c @@ -1,7 +1,10 @@ -/** @addtogroup rng_file +/** @addtogroup rng_file RNG peripheral API + * @ingroup peripheral_apis * - * This library supports the random number generator peripheral (RNG) in the - * STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. + * This library supports "version 1" of the random number generator + * peripheral (RNG) in the STM32 series of ARM Cortex Microcontrollers + * by ST Microelectronics. This is a common peripheral available on multiple + * devices in the family. * * LGPL License Terms @ref lgpl_license */ @@ -44,7 +47,7 @@ void rng_enable(void) /** Randomizes a number (non-blocking). * Can fail if a clock error or seed error is detected. Consult the Reference * Manual, but "try again", potentially after resetting the peripheral - * @param pointer to a uint32_t that will be randomized. + * @param rand_nr pointer to a uint32_t that will be randomized. * @returns true on success, pointer is only written to on success * @sa rng_get_random_blocking */ diff --git a/lib/stm32/common/rtc_common_l1f024.c b/lib/stm32/common/rtc_common_l1f024.c index 7579dfdc..d7825a7c 100644 --- a/lib/stm32/common/rtc_common_l1f024.c +++ b/lib/stm32/common/rtc_common_l1f024.c @@ -1,4 +1,5 @@ -/** @addtogroup rtc_file +/** @addtogroup rtc_file RTC peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au> @@ -106,6 +107,7 @@ void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel) * down-counting. */ RTC_WUTR = wkup_time; + RTC_CR &= ~(RTC_CR_WUCLKSEL_MASK << RTC_CR_WUCLKSEL_SHIFT); RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT); RTC_CR |= RTC_CR_WUTE; } diff --git a/lib/stm32/common/st_usbfs_core.c b/lib/stm32/common/st_usbfs_core.c index a4ab414a..0dba875b 100644 --- a/lib/stm32/common/st_usbfs_core.c +++ b/lib/stm32/common/st_usbfs_core.c @@ -40,6 +40,7 @@ void st_usbfs_set_address(usbd_device *dev, uint8_t addr) /** * Set the receive buffer size for a given USB endpoint. * + * @param dev the usb device handle returned from @ref usbd_init * @param ep Index of endpoint to configure. * @param size Size in bytes of the RX buffer. Legal sizes : {2,4,6...62}; {64,96,128...992}. * @returns (uint16) Actual size set diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index 9c8b5cc6..64701836 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -1,4 +1,5 @@ -/** @addtogroup timer_file +/** @addtogroup timer_file TIMER peripheral API +@ingroup peripheral_apis @author @htmlonly © @endhtmlonly 2010 Edward Cheeseman <evbuilder@users.sourceforge.org> diff --git a/lib/stm32/common/timer_common_f24.c b/lib/stm32/common/timer_common_f24.c index ce1c1e38..8368c38a 100644 --- a/lib/stm32/common/timer_common_f24.c +++ b/lib/stm32/common/timer_common_f24.c @@ -33,8 +33,7 @@ Set timer options register on TIM2 or TIM5, used for trigger remapping on TIM2, and similarly for TIM5 for oscillator calibration purposes. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5: -@ref tim5_opt_trigger_remap. +@param option flags TIM2 @ref tim2_opt_trigger_remap or TIM5 @ref tim5_opt_trigger_remap */ void timer_set_option(uint32_t timer_peripheral, uint32_t option) diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile index a5883643..6d832a57 100644 --- a/lib/stm32/f0/Makefile +++ b/lib/stm32/f0/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32f0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -36,24 +34,28 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = can.o flash.o rcc.o dma.o rtc.o comparator.o \ - dac.o pwr.o gpio.o timer.o adc.o desig.o - -OBJS += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \ - pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \ - dma_common_l1f013.o exti_common_all.o \ - dac_common_all.o \ - timer_common_all.o timer_common_f0234.o rcc_common_all.o - -OBJS += adc_common_v2.o -OBJS += crs_common_all.o -OBJS += flash_common_all.o flash_common_f.o flash_common_f01.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += i2c_common_v2.o -OBJS += spi_common_all.o spi_common_v2.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v2.o +OBJS += adc.o adc_common_v2.o +OBJS += can.o +OBJS += comparator.o +OBJS += crc_common_all.o crc_v2.o +OBJS += crs_common_all.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o dma_common_csel.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += iwdg_common_all.o +OBJS += i2c_common_v2.o +OBJS += pwr_common_v1.o +OBJS += rcc.o rcc_common_all.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o timer_common_f0234.o +OBJS += usart_common_all.o usart_common_v2.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v2.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c index 2302582a..663099dd 100644 --- a/lib/stm32/f0/adc.c +++ b/lib/stm32/f0/adc.c @@ -117,7 +117,7 @@ void adc_disable_discontinuous_mode(uint32_t adc) * @par * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) - * @param[in] adc ::adc_opmode. ADC operation mode (@ref adc_opmode) + * @param[in] opmode ADC operation mode */ void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode) @@ -277,6 +277,16 @@ bool adc_get_eoc_sequence_flag(uint32_t adc) return ADC_ISR(adc) & ADC_ISR_EOSEQ; } +/*---------------------------------------------------------------------------*/ +/** @brief ADC Clear Regular End-Of-Conversion Sequence Flag + * + * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) + */ + +void adc_clear_eoc_sequence_flag(uint32_t adc) +{ + ADC_ISR(adc) = ADC_ISR_EOSEQ; +} /**@}*/ @@ -291,12 +301,12 @@ bool adc_get_eoc_sequence_flag(uint32_t adc) *@{*/ /*---------------------------------------------------------------------------*/ -/** @brief ADC Set Clock Prescale +/** @brief ADC Set Clock Source * * The ADC clock taken from the many sources. * * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base) - * @param[in] prescale Unsigned int32. Prescale value (@ref adc_api_clksource) + * @param[in] source Unsigned int32. Source (@ref adc_api_clksource) */ void adc_set_clk_source(uint32_t adc, uint32_t source) diff --git a/lib/stm32/f0/flash.c b/lib/stm32/f0/flash.c index 433b7b53..d594a5e6 100644 --- a/lib/stm32/f0/flash.c +++ b/lib/stm32/f0/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32F0xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F05x FLASH</b> * diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index d4b79e5d..182bdd28 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32F0xx-rcc-file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32F0xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F0xx Reset and Clock Control</b> * @@ -51,7 +51,7 @@ uint32_t rcc_apb1_frequency = 8000000; /* 8MHz after reset */ * Clear the interrupt flag that was set when a clock oscillator became ready * to use. * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) @@ -84,7 +84,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) @@ -117,7 +117,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) @@ -150,7 +150,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID * @returns int. Boolean value for flag set. */ @@ -238,7 +238,7 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc) * becomes ready (see @ref rcc_osc_ready_int_flag and @ref * rcc_wait_for_osc_ready). * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_on(enum rcc_osc osc) @@ -276,7 +276,7 @@ void rcc_osc_on(enum rcc_osc osc) * @note An oscillator cannot be turned off if it is selected as the system * clock. * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param osc Oscillator ID */ void rcc_osc_off(enum rcc_osc osc) @@ -327,7 +327,7 @@ void rcc_css_disable(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. * - * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, LSE and PLL have + * @param clk Oscillator ID. Only HSE, LSE and PLL have * effect. */ @@ -357,7 +357,7 @@ void rcc_set_sysclk_source(enum rcc_osc clk) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the USB Clock. * - * @param[in] osc enum ::osc_t. Oscillator ID. Only HSI48 or PLL have + * @param clk Oscillator ID. Only HSI48 or PLL have * effect. */ void rcc_set_usbclk_source(enum rcc_osc clk) @@ -402,7 +402,7 @@ void rcc_disable_rtc_clock(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the RTC clock -@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI. +@param[in] clk RTC clock source. Only HSE/32, LSE and LSI. */ void rcc_set_rtc_clock_source(enum rcc_osc clk) @@ -467,7 +467,7 @@ void rcc_set_pllxtpre(uint32_t pllxtpre) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB Prescale Factor. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre + * @param[in] ppre Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre(uint32_t ppre) @@ -501,7 +501,7 @@ void rcc_set_prediv(uint32_t prediv) /*---------------------------------------------------------------------------*/ /** @brief RCC Get the System Clock Source. * - * @returns ::osc_t System clock source: + * @returns current system clock source */ enum rcc_osc rcc_system_clock_source(void) @@ -543,7 +543,7 @@ uint32_t rcc_get_i2c_clocks(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Get the USB Clock Source. * - * @returns ::osc_t USB clock source: + * @returns Currently selected USB clock source */ enum rcc_osc rcc_usb_clock_source(void) diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile index a2a8836e..f55fe391 100755 --- a/lib/stm32/f1/Makefile +++ b/lib/stm32/f1/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32f1 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -36,22 +34,30 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc.o adc_common_v1.o can.o desig.o flash.o gpio.o \ - rcc.o rtc.o timer.o -OBJS += mac.o mac_stm32fxx7.o phy.o phy_ksz80x1.o - -OBJS += crc_common_all.o dac_common_all.o dma_common_l1f013.o \ - gpio_common_all.o i2c_common_v1.o iwdg_common_all.o \ - pwr_common_v1.o \ - timer_common_all.o usart_common_all.o usart_common_f124.o \ - rcc_common_all.o exti_common_all.o +OBJS += adc.o adc_common_v1.o +OBJS += can.o +OBJS += crc_common_all.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o +OBJS += gpio.o gpio_common_all.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += pwr_common_v1.o +OBJS += rcc.o rcc_common_all.o +OBJS += rtc.o +OBJS += spi_common_all.o spi_common_v1.o +OBJS += timer.o timer_common_all.o +OBJS += usart_common_all.o usart_common_f124.o -OBJS += flash_common_all.o flash_common_f.o flash_common_f01.o -OBJS += spi_common_all.o spi_common_v1.o +OBJS += mac.o mac_stm32fxx7.o +OBJS += phy.o phy_ksz80x1.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += usb_dwc_common.o usb_f107.o -OBJS += st_usbfs_core.o st_usbfs_v1.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += usb_dwc_common.o usb_f107.o +OBJS += st_usbfs_core.o st_usbfs_v1.o OBJS += sdio_common_all.o diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index 24e79c51..3ff12bf7 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -59,11 +59,11 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent adc_set_dual_mode(ADC_CR1_DUALMOD_IND); adc_disable_scan_mode(ADC1); adc_set_single_conversion_mode(ADC1); - adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); - adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); + adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_1DOT5CYC); + adc_enable_external_trigger_regular(ADC1, ADC_CR2_EXTSEL_SWSTART); adc_power_on(ADC1); adc_reset_calibration(ADC1); - adc_calibration(ADC1); + adc_calibrate(ADC1); adc_start_conversion_regular(ADC1); while (! adc_eoc(ADC1)); reg16 = adc_read_regular(ADC1); diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c index 68606a9a..c990b1e6 100644 --- a/lib/stm32/f1/flash.c +++ b/lib/stm32/f1/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32F1xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F1xx FLASH Memory</b> * diff --git a/lib/stm32/f1/gpio.c b/lib/stm32/f1/gpio.c index c8943fce..160c46b5 100644 --- a/lib/stm32/f1/gpio.c +++ b/lib/stm32/f1/gpio.c @@ -1,6 +1,4 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F1xx +/** @addtogroup gpio_file @brief <b>libopencm3 STM32F1xx General Purpose I/O</b> diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 69041d7c..6d1c252a 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32F1xx-rcc-file RCC +/** @defgroup rcc_file RCC peripheral API -@ingroup STM32F1xx +@ingroup peripheral_apis @brief <b>libopencm3 STM32F1xx Reset and Clock Control</b> @@ -64,7 +64,7 @@ uint32_t rcc_ahb_frequency = 8000000; Clear the interrupt flag that was set when a clock oscillator became ready to use. -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) @@ -97,7 +97,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt -@param[in] osc enum ::osc_t. Oscillator ID +@param osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) @@ -130,7 +130,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) @@ -163,7 +163,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID @returns int. Boolean value for flag set. */ @@ -255,7 +255,7 @@ status flag is available to indicate when the oscillator becomes ready (see backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_on(enum rcc_osc osc) @@ -296,7 +296,7 @@ backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect) or the backup domain has been (see reset @ref rcc_backupdomain_reset). -@param[in] osc enum ::osc_t. Oscillator ID +@param[in] osc Oscillator ID */ void rcc_osc_off(enum rcc_osc osc) @@ -452,7 +452,7 @@ void rcc_enable_rtc_clock(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the RTC clock -@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI. +@param[in] clock_source RTC clock source. Only HSE/128, LSE and LSI. */ void rcc_set_rtc_clock_source(enum rcc_osc clock_source) diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c index 2743eed9..ec2711ad 100644 --- a/lib/stm32/f1/rtc.c +++ b/lib/stm32/f1/rtc.c @@ -1,6 +1,6 @@ -/** @defgroup rtc_file RTC +/** @defgroup rtc_file RTC peripheral API * - * @ingroup STM32F1xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F1xx RTC</b> * @@ -241,7 +241,7 @@ uint32_t rtc_get_alarm_val(void) /*---------------------------------------------------------------------------*/ /** @brief RTC set the Counter -@param[in] uint32_t counter_val: 32 bit time setting for the counter. +@param[in] counter_val 32 bit time setting for the counter. */ void rtc_set_counter_val(uint32_t counter_val) diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c index fd46742c..6640d6f3 100644 --- a/lib/stm32/f1/timer.c +++ b/lib/stm32/f1/timer.c @@ -1,12 +1,5 @@ -/* This file is used for documentation purposes. It does not need -to be compiled. All source code is in the common area. -If there is any device specific code required it can be included here, -in which case this file must be added to the compile list. */ - -/** @defgroup timer_file Timers - -@ingroup STM32F1xx - +/** @defgroup timer_file TIMER peripheral API +@ingroup peripheral_apis @brief <b>libopencm3 STM32F1xx Timers</b> @version 1.0.0 @@ -37,6 +30,8 @@ in which case this file must be added to the compile list. */ #include <libopencm3/stm32/timer.h> +/**@{*/ + /*---------------------------------------------------------------------------*/ /** @brief Set Input Polarity @@ -55,3 +50,4 @@ void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic, } } +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile index 4b143e58..c832bc8c 100644 --- a/lib/stm32/f2/Makefile +++ b/lib/stm32/f2/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32f2 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -36,24 +34,29 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = gpio.o rcc.o desig.o - -OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ - gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \ - iwdg_common_all.o rtc_common_l1f024.o \ - timer_common_all.o timer_common_f0234.o \ - timer_common_f24.o usart_common_all.o usart_common_f124.o \ - hash_common_f24.o \ - crypto_common_f24.o exti_common_all.o rcc_common_all.o -OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o -OBJS += flash_common_idcache.o -OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o - -OBJS += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \ - usb_f107.o usb_f207.o usb_msc.o +OBJS += crc_common_all.o +OBJS += crypto_common_f24.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o flash_common_idcache.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += hash_common_f24.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o +OBJS += usart_common_all.o usart_common_f124.o + +OBJS += usb.o usb_standard.o usb_control.o usb_msc.o +OBJS += usb_dwc.o usb_dwc_common.o usb_f107.o usb_f207.o + +OBJS += sdio_common_all.o -OBJS += sdio_common_all.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f2/flash.c b/lib/stm32/f2/flash.c index c2a0b3ba..958e62a9 100644 --- a/lib/stm32/f2/flash.c +++ b/lib/stm32/f2/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32F2xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F2xx FLASH</b> * diff --git a/lib/stm32/f2/gpio.c b/lib/stm32/f2/gpio.c deleted file mode 100644 index 052e306f..00000000 --- a/lib/stm32/f2/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F2xx - -@brief <b>libopencm3 STM32F2xx General Purpose I/O</b> - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/gpio.h> diff --git a/lib/stm32/f2/hash.c b/lib/stm32/f2/hash.c deleted file mode 100644 index ca48d8bb..00000000 --- a/lib/stm32/f2/hash.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup hash_file HASH - * - * @ingroup STM32F2xx - * - * @brief <b>libopencm3 STM32F2xx Hash Processor</b> - * - * @version 1.0.0 - * - * @date 14 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/hash.h> diff --git a/lib/stm32/f2/pwr.c b/lib/stm32/f2/pwr.c deleted file mode 100644 index 0e5641eb..00000000 --- a/lib/stm32/f2/pwr.c +++ /dev/null @@ -1,39 +0,0 @@ -/** @defgroup pwr_file PWR - * - * @ingroup STM32F2xx - * - * @brief <b>libopencm3 STM32F2xx Power Control</b> - * - * @version 1.0.0 - * - * @author @htmlonly © @endhtmlonly 2014 - * Ken Sarkies <ksarkies@internode.on.net> - * - * @date 13 January 2014 - * - * This library supports the power control system for the - * STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. - * - * LGPL License Terms @ref lgpl_license - */ -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net> - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/pwr.h> - diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index b662cebb..e530de47 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32F2xx + * @ingroup peripheral_apis * * @section rcc_f2_api_ex Reset and Clock Control API. * @@ -355,6 +355,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_main_pll_hse(clock->pllm, clock->plln, clock->pllp, clock->pllq); diff --git a/lib/stm32/f2/rtc.c b/lib/stm32/f2/rtc.c deleted file mode 100644 index 06666ab1..00000000 --- a/lib/stm32/f2/rtc.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup rtc_file RTC - * - * @ingroup STM32F2xx - * - * @brief <b>libopencm3 STM32F2xx RTC</b> - * - * @version 1.0.0 - * - * @date 4 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/rtc.h> diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile index e7a35b7f..c24cae90 100644 --- a/lib/stm32/f3/Makefile +++ b/lib/stm32/f3/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_stm32f3 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -37,23 +35,25 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = rcc.o adc.o can.o pwr.o dma.o flash.o desig.o - -OBJS += gpio_common_all.o gpio_common_f0234.o \ - dac_common_all.o crc_common_all.o crc_v2.o \ - iwdg_common_all.o pwr_common_v1.o dma_common_l1f013.o\ - timer_common_all.o timer_common_f0234.o \ - exti_common_all.o rcc_common_all.o -OBJS += adc_common_v2.o adc_common_v2_multi.o -OBJS += flash_common_all.o flash_common_f.o -OBJS += usart_common_v2.o usart_common_all.o -OBJS += i2c_common_v2.o -OBJS += spi_common_all.o spi_common_v2.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v1.o - -OBJS += sdio_common_all.o +OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o +OBJS += can.o +OBJS += crc_common_all.o crc_v2.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += pwr_common_v1.o +OBJS += rcc.o rcc_common_all.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o timer_common_f0234.o +OBJS += usart_common_v2.o usart_common_all.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v1.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/f3/adc.c b/lib/stm32/f3/adc.c index 9eb73dc2..e9a36846 100644 --- a/lib/stm32/f3/adc.c +++ b/lib/stm32/f3/adc.c @@ -587,10 +587,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset) * * The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. * + * @param adc peripheral of choice @ref adc_reg_base * @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref * adc_ccr_adcpre -*/ - + */ void adc_set_clk_prescale(uint32_t adc, uint32_t prescale) { uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | prescale); @@ -605,10 +605,10 @@ void adc_set_clk_prescale(uint32_t adc, uint32_t prescale) * * The various modes possible are described in the reference manual. * + * @param adc peripheral of choice @ref adc_reg_base * @param[in] mode Unsigned int32. Multiple mode selection from @ref * adc_multi_mode -*/ - + */ void adc_set_multi_mode(uint32_t adc, uint32_t mode) { ADC_CCR(adc) |= mode; diff --git a/lib/stm32/f3/dac.c b/lib/stm32/f3/dac.c deleted file mode 100644 index 2d8021e0..00000000 --- a/lib/stm32/f3/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - * - * @ingroup STM32F3xx - * - * @brief <b>libopencm3 STM32F3xx DAC</b> - * - * @version 1.0.0 - * - * @date 18 August 2012 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/dac.h> diff --git a/lib/stm32/f3/dma.c b/lib/stm32/f3/dma.c deleted file mode 100644 index c5d82b13..00000000 --- a/lib/stm32/f3/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - * - * @ingroup STM32F3xx - * - * @brief <b>libopencm3 STM32F3xx Direct Memory Access</b> - * - * @version 1.0.0 - * - * @date 11 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/dma.h> diff --git a/lib/stm32/f3/flash.c b/lib/stm32/f3/flash.c index da8dfb68..7d73ce62 100644 --- a/lib/stm32/f3/flash.c +++ b/lib/stm32/f3/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32F3xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F3xx FLASH</b> * diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c index 0fdb9a48..3e1852bf 100644 --- a/lib/stm32/f3/rcc.c +++ b/lib/stm32/f3/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32F3xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F3xx Reset and Clock Control</b> * @@ -80,7 +80,7 @@ const struct rcc_clock_scale rcc_hse8mhz_configs[] = { .ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ahb_frequency = 72e6, - .apb1_frequency = 32e6, + .apb1_frequency = 36e6, .apb2_frequency = 72e6, } }; diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile index 91ccf4b9..ac2673ca 100644 --- a/lib/stm32/f4/Makefile +++ b/lib/stm32/f4/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_stm32f4 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -39,30 +37,39 @@ TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = adc.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \ - rtc.o crypto.o - -OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \ - gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \ - iwdg_common_all.o pwr_common_v1.o rtc_common_l1f024.o \ - timer_common_all.o \ - timer_common_f0234.o timer_common_f24.o usart_common_all.o \ - usart_common_f124.o \ - hash_common_f24.o crypto_common_f24.o exti_common_all.o \ - rcc_common_all.o -OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o -OBJS += flash_common_idcache.o -OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o - -OBJS += sdio_common_all.o +OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o +OBJS += can.o +OBJS += crc_common_all.o +OBJS += crypto_common_f24.o crypto.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += dma2d_common_f47.o +OBJS += dsi_common_f47.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o +OBJS += flash_common_idcache.o +OBJS += fmc_common_f47.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += hash_common_f24.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o +OBJS += ltdc_common_f47.o +OBJS += pwr_common_v1.o pwr.o +OBJS += rcc_common_all.o rcc.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o rtc.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o +OBJS += usart_common_all.o usart_common_f124.o -OBJS += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \ - usb_f107.o usb_f207.o usb_msc.o +OBJS += usb.o usb_standard.o usb_control.o usb_msc.o +OBJS += usb_dwc.o usb_dwc_common.o usb_f107.o usb_f207.o -OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o fmc.o +OBJS += sdio_common_all.o -OBJS += ltdc.o +OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet diff --git a/lib/stm32/f4/dac.c b/lib/stm32/f4/dac.c deleted file mode 100644 index c5397b62..00000000 --- a/lib/stm32/f4/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - -@ingroup STM32F4xx - -@brief <b>libopencm3 STM32F4xx DAC</b> - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/dac.h> diff --git a/lib/stm32/f4/dma.c b/lib/stm32/f4/dma.c deleted file mode 100644 index 6616621a..00000000 --- a/lib/stm32/f4/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - -@ingroup STM32F4xx - -@brief <b>libopencm3 STM32F4xx DMA</b> - -@version 1.0.0 - -@date 30 November 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/dma.h> diff --git a/lib/stm32/f4/flash.c b/lib/stm32/f4/flash.c index 8891be6e..93cef9f3 100644 --- a/lib/stm32/f4/flash.c +++ b/lib/stm32/f4/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F4xx FLASH</b> * diff --git a/lib/stm32/f4/gpio.c b/lib/stm32/f4/gpio.c deleted file mode 100644 index ea59ae79..00000000 --- a/lib/stm32/f4/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F4xx - -@brief <b>libopencm3 STM32F4xx General Purpose I/O</b> - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/gpio.h> diff --git a/lib/stm32/f4/hash.c b/lib/stm32/f4/hash.c deleted file mode 100644 index cd791bff..00000000 --- a/lib/stm32/f4/hash.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup hash_file HASH - * - * @ingroup STM32F4xx - * - * @brief <b>libopencm3 STM32F4xx Hash Processor</b> - * - * @version 1.0.0 - * - * @date 13 January 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/hash.h> diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c index 58d9bd19..0d0c2d2d 100644 --- a/lib/stm32/f4/pwr.c +++ b/lib/stm32/f4/pwr.c @@ -1,6 +1,6 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file PWR peripheral API * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F4xx Power Control</b> * @@ -36,6 +36,8 @@ #include <libopencm3/stm32/pwr.h> +/**@{*/ + void pwr_set_vos_scale(enum pwr_vos_scale scale) { uint32_t reg32; @@ -43,3 +45,5 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale) reg32 |= (scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_SHIFT; PWR_CR = reg32; } + +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 5dd775d5..66c3d4a1 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @section rcc_f4_api_ex Reset and Clock Control API. * @@ -49,29 +49,68 @@ uint32_t rcc_ahb_frequency = 16000000; uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; -const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 8, - .plln = 96, +const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = { + { /* 84MHz */ + .pllm = 16, + .plln = 336, + .pllp = 4, + .pllq = 7, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_2, + .ppre2 = RCC_CFGR_PPRE_DIV_NONE, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_2WS, + .ahb_frequency = 84000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, + { /* 168MHz */ + .pllm = 16, + .plln = 336, + .pllp = 2, + .pllq = 7, + .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .voltage_scale = PWR_SCALE1, + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 168000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, + { /* 180MHz */ + .pllm = 16, + .plln = 360, .pllp = 2, - .pllq = 2, + .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, }, +}; + +const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 84MHz */ .pllm = 8, .plln = 336, .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -82,28 +121,13 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 8, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 8, .plln = 336, .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -114,31 +138,33 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, -}; - -const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 12, - .plln = 96, + { /* 180MHz */ + .pllm = 8, + .plln = 360, .pllp = 2, - .pllq = 2, + .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, }, +}; + +const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 84MHz */ .pllm = 12, .plln = 336, .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -149,28 +175,13 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 12, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 12, .plln = 336, .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -181,31 +192,33 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, -}; - -const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 16, - .plln = 96, + { /* 180MHz */ + .pllm = 12, + .plln = 360, .pllp = 2, - .pllq = 2, + .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, }, +}; + +const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 84MHz */ .pllm = 16, .plln = 336, .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -216,28 +229,13 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ - .pllm = 16, - .plln = 240, - .pllp = 2, - .pllq = 5, - .pllr = 0, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .voltage_scale = PWR_SCALE1, - .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, { /* 168MHz */ .pllm = 16, .plln = 336, .pllp = 2, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, @@ -248,31 +246,33 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, -}; - -const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { - { /* 48MHz */ - .pllm = 25, - .plln = 96, + { /* 180MHz */ + .pllm = 16, + .plln = 360, .pllp = 2, - .pllq = 2, + .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_1WS, - .ahb_frequency = 48000000, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, }, +}; + +const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { { /* 84MHz */ .pllm = 25, .plln = 336, .pllp = 4, .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, @@ -283,37 +283,39 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .apb1_frequency = 42000000, .apb2_frequency = 84000000, }, - { /* 120MHz */ + { /* 168MHz */ .pllm = 25, - .plln = 240, + .plln = 336, .pllp = 2, - .pllq = 5, + .pllq = 7, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | - FLASH_ACR_LATENCY_3WS, - .ahb_frequency = 120000000, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, + FLASH_ACR_LATENCY_5WS, + .ahb_frequency = 168000000, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, }, - { /* 168MHz */ + { /* 180MHz */ .pllm = 25, - .plln = 336, + .plln = 360, .pllp = 2, - .pllq = 7, + .pllq = 8, .pllr = 0, + .pll_source = RCC_CFGR_PLLSRC_HSE_CLK, .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .voltage_scale = PWR_SCALE1, .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, - .ahb_frequency = 168000000, - .apb1_frequency = 42000000, - .apb2_frequency = 84000000, + .ahb_frequency = 180000000, + .apb1_frequency = 45000000, + .apb2_frequency = 90000000, }, }; @@ -684,7 +686,15 @@ uint32_t rcc_system_clock_source(void) return (RCC_CFGR & 0x000c) >> 2; } -void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) +/** + * Setup clocks to run from PLL. + * + * The arguments provide the pll source, multipliers, dividers, all that's + * needed to establish a system clock. + * + * @param clock clock information structure. + */ +void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { /* Enable internal high-speed oscillator (HSI). */ rcc_osc_on(RCC_HSI); @@ -694,8 +704,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* Enable external high-speed oscillator (HSE). */ - rcc_osc_on(RCC_HSE); - rcc_wait_for_osc_ready(RCC_HSE); + if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { + rcc_osc_on(RCC_HSE); + rcc_wait_for_osc_ready(RCC_HSE); + } /* Set the VOS scale mode */ rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_PWR); @@ -709,8 +721,17 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); - rcc_set_main_pll_hse(clock->pllm, clock->plln, - clock->pllp, clock->pllq, clock->pllr); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ + if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { + rcc_set_main_pll_hse(clock->pllm, clock->plln, + clock->pllp, clock->pllq, clock->pllr); + } else { + rcc_set_main_pll_hsi(clock->pllm, clock->plln, + clock->pllp, clock->pllq, clock->pllr); + } /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(RCC_PLL); @@ -741,7 +762,21 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) rcc_apb2_frequency = clock->apb2_frequency; /* Disable internal high-speed oscillator. */ - rcc_osc_off(RCC_HSI); + if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) { + rcc_osc_off(RCC_HSI); + } +} + +/** + * Setup clocks with the HSE. + * + * @deprecated replaced by rcc_clock_setup_pll as a drop in replacement. + * @see rcc_clock_setup_pll which supports HSI as well as HSE, using the same + * clock structures. + */ +void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock) +{ + rcc_clock_setup_pll(clock); } /**@}*/ diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c index f08ac2bc..847fb55b 100644 --- a/lib/stm32/f4/rtc.c +++ b/lib/stm32/f4/rtc.c @@ -1,6 +1,6 @@ -/** @defgroup rtc_file RTC +/** @defgroup rtc_file RTC peripheral API * - * @ingroup STM32F4xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F4xx RTC</b> * @@ -32,6 +32,7 @@ #include <libopencm3/cm3/nvic.h> #include <libopencm3/stm32/rtc.h> +/**@{*/ /*---------------------------------------------------------------------------*/ /** @brief Enable the wakeup timer @@ -95,3 +96,5 @@ void rtc_disable_wakeup_timer_interrupt(void) /* 3. Disable RTC wakeup timer event. */ RTC_CR &= ~RTC_CR_WUTIE; } + +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/f4/timer.c b/lib/stm32/f4/timer.c deleted file mode 100644 index 72ecd8df..00000000 --- a/lib/stm32/f4/timer.c +++ /dev/null @@ -1,38 +0,0 @@ -/* This file is used for documentation purposes. It does not need -to be compiled. All source code is in the common area. -If there is any device specific code required it can be included here, -in which case this file must be added to the compile list. */ - -/** @defgroup timer_file Timers - -@ingroup STM32F4xx - -@brief <b>libopencm3 STM32F4xx Timers</b> - -@version 1.0.0 - -@date 18 August 2012 - -*/ - -/* - * This file is part of the libopencm3 project. - * - * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org> - * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com> - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/timer.h> diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile index 8b1bdef7..ff078655 100644 --- a/lib/stm32/f7/Makefile +++ b/lib/stm32/f7/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_stm32f7 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar # STM32F7 only supports single precision FPU FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv5-sp-d16 @@ -42,16 +40,31 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = flash_common_all.o flash_common_f.o flash_common_f24.o flash.o -OBJS += desig.o -OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o -OBJS += pwr.o rcc.o +OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o +OBJS += can.o +OBJS += crc_common_all.o crc_v2.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_f24.o +OBJS += dma2d_common_f47.o +OBJS += dsi_common_f47.o +OBJS += exti_common_all.o +OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o +OBJS += fmc_common_f47.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o +OBJS += ltdc_common_f47.o +OBJS += pwr.o rcc.o +OBJS += rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o -OBJS += rcc_common_all.o -OBJS += rng_common_v1.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o -OBJS += timer_common_all.o -OBJS += usart_common_all.o usart_common_v2.o +# Ethernet +OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet diff --git a/lib/stm32/f7/flash.c b/lib/stm32/f7/flash.c index 9ec3e219..82dcf4f3 100644 --- a/lib/stm32/f7/flash.c +++ b/lib/stm32/f7/flash.c @@ -1,5 +1,6 @@ -/** @addtogroup flash_file +/** @defgroup flash_file FLASH peripheral API * + * @ingroup peripheral_apis */ /* diff --git a/lib/stm32/f7/gpio.c b/lib/stm32/f7/gpio.c deleted file mode 100644 index a5fb4afc..00000000 --- a/lib/stm32/f7/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32F7xx - -@brief <b>libopencm3 STM32F7xx General Purpose I/O</b> - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/gpio.h> diff --git a/lib/stm32/f7/pwr.c b/lib/stm32/f7/pwr.c index 93bb845d..cb19bb6a 100644 --- a/lib/stm32/f7/pwr.c +++ b/lib/stm32/f7/pwr.c @@ -1,6 +1,6 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file PWR peripheral API * - * @ingroup STM32F7xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32F7xx Power Control</b> * @@ -38,6 +38,8 @@ #include <libopencm3/stm32/pwr.h> +/**@{*/ + void pwr_set_vos_scale(enum pwr_vos_scale scale) { PWR_CR1 &= ~PWR_CR1_VOS_MASK; @@ -64,3 +66,5 @@ void pwr_disable_overdrive(void) PWR_CR1 &= ~(PWR_CR1_ODEN | PWR_CR1_ODSWEN); while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY)); } + +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c index ea6dcd50..7abdd770 100644 --- a/lib/stm32/f7/rcc.c +++ b/lib/stm32/f7/rcc.c @@ -1,8 +1,19 @@ +/** @defgroup rcc_file RCC peripheral API + * + * @ingroup peripheral_apis + * This library supports the Reset and Clock Control System in the STM32 series + * of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + #include <libopencm3/cm3/assert.h> #include <libopencm3/stm32/rcc.h> #include <libopencm3/stm32/pwr.h> #include <libopencm3/stm32/flash.h> +/**@{*/ + uint32_t rcc_ahb_frequency = 16000000; uint32_t rcc_apb1_frequency = 16000000; uint32_t rcc_apb2_frequency = 16000000; @@ -392,6 +403,10 @@ void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz) rcc_set_ppre1(clock->ppre1); rcc_set_ppre2(clock->ppre2); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_main_pll_hse(pllm, clock->plln, clock->pllp, clock->pllq); @@ -468,3 +483,5 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock) rcc_apb1_frequency = clock->apb1_frequency; rcc_apb2_frequency = clock->apb2_frequency; } + +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile new file mode 100644 index 00000000..cb75e4fe --- /dev/null +++ b/lib/stm32/g0/Makefile @@ -0,0 +1,53 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com> +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see <http://www.gnu.org/licenses/>. +## + +LIBNAME = libopencm3_stm32g0 +SRCLIBDIR ?= ../.. + +CC = $(PREFIX)gcc +AR = $(PREFIX)ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../../include -fno-common \ + -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) \ + -ffunction-sections -fdata-sections -MD -DSTM32G0 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) + +ARFLAGS = rcs + +OBJS += crc_common_all.o +OBJS += exti.o exti_common_all.o +OBJS += flash.o flash_common_all.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o +OBJS += pwr.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o + +VPATH +=../:../../cm3:../common + +include ../../Makefile.include diff --git a/lib/stm32/g0/exti.c b/lib/stm32/g0/exti.c new file mode 100644 index 00000000..fb5534ba --- /dev/null +++ b/lib/stm32/g0/exti.c @@ -0,0 +1,72 @@ +/** @defgroup exti_file EXTI peripheral API + * @ingroup peripheral_apis + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * @date 10 January 2019 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/stm32/exti.h> + +/* @brief Get the rising edge interrupt requestf flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +uint32_t exti_get_rising_flag_status(uint32_t exti) +{ + return (EXTI_RPR1 & exti); +} + +/* @brief Get the rising edge interrupt request flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +uint32_t exti_get_falling_flag_status(uint32_t exti) +{ + return (EXTI_FPR1 & exti); +} + +/* @brief Resets the rising edge interrupt request pending flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +void exti_reset_rising_request(uint32_t extis) +{ + EXTI_RPR1 = extis; +} + +/* @brief Resets the falling edge interrupt request pending flag of a given EXTI interrupt. + * + * @param[in] exti unsigned int32 Exti line. + * + * */ +void exti_reset_falling_request(uint32_t extis) +{ + EXTI_FPR1 = extis; +} + +/**@}*/ diff --git a/lib/stm32/l0/flash.c b/lib/stm32/g0/flash.c index b1ba6420..74ecf5d0 100644 --- a/lib/stm32/l0/flash.c +++ b/lib/stm32/g0/flash.c @@ -1,8 +1,10 @@ -/** @defgroup gpio_file GPIO +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32L0xx + * @ingroup peripheral_apis * - * @brief <b>libopencm3 STM32L0xx General Purpose I/O</b> + * @brief <b>libopencm3 STM32G0xx FLASH</b> + * + * @version 1.0.0 * * LGPL License Terms @ref lgpl_license */ @@ -24,4 +26,51 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ +/**@{*/ + #include <libopencm3/stm32/flash.h> + +void flash_icache_enable(void) +{ + FLASH_ACR |= FLASH_ACR_ICEN; +} + +void flash_icache_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_ICEN; +} + +void flash_icache_reset(void) +{ + FLASH_ACR |= FLASH_ACR_ICRST; +} + +void flash_unlock_progmem(void) +{ + FLASH_KEYR = FLASH_KEYR_KEY1; + FLASH_KEYR = FLASH_KEYR_KEY2; +} + +void flash_lock_progmem(void) +{ + FLASH_CR |= FLASH_CR_LOCK; +} + +void flash_lock_option_bytes(void) +{ + FLASH_CR |= FLASH_CR_OPTLOCK; +} + +void flash_unlock(void) +{ + flash_unlock_progmem(); + flash_unlock_option_bytes(); +} + +void flash_lock(void) +{ + flash_lock_option_bytes(); + flash_lock_progmem(); +} + +/**@}*/
\ No newline at end of file diff --git a/lib/stm32/g0/pwr.c b/lib/stm32/g0/pwr.c new file mode 100644 index 00000000..32cd535a --- /dev/null +++ b/lib/stm32/g0/pwr.c @@ -0,0 +1,100 @@ +/** @defgroup pwr_file PWR peripheral API + * @ingroup peripheral_apis + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * @ingroup peripheral_apis + * + * @brief <b>libopencm3 STM32G0xx Power Control</b> + * + * @version 1.0.0 + * + * This library supports the power control system for the + * STM32G0 series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ +/**@{*/ +#include <libopencm3/stm32/pwr.h> + +/*---------------------------------------------------------------------------*/ +/** @brief Setup voltage scaling range. + */ +void pwr_set_vos_scale(enum pwr_vos_scale scale) +{ + uint32_t reg32; + + reg32 = PWR_CR1 & ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT); + reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT; + PWR_CR1 = reg32; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable RTC domain write protect. + */ +void pwr_disable_backup_domain_write_protect(void) +{ + PWR_CR1 |= PWR_CR1_DBP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable RTC domain write protect. + */ +void pwr_enable_backup_domain_write_protect(void) +{ + PWR_CR1 &= ~PWR_CR1_DBP; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Select the low power mode used in deep sleep. + * @param lpms low power mode @ref pwr_cr1_lpms + */ +void pwr_set_low_power_mode_selection(uint32_t lpms) +{ + uint32_t reg32; + + reg32 = PWR_CR1; + reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT); + PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT)); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable Power Voltage Detector. + * @param[in] pvdr_level Power Voltage Detector Rising Threshold voltage @ref pwr_cr2_pvdrt. + * @param[in] pvdf_level Power Voltage Detector Falling Threshold voltage @ref pwr_cr2_pvdft. +*/ +void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level) +{ + uint32_t reg32; + + reg32 = PWR_CR2; + reg32 &= ~(PWR_CR2_PVDRT_MASK << PWR_CR2_PVDRT_SHIFT); + reg32 &= ~(PWR_CR2_PVDFT_MASK << PWR_CR2_PVDFT_SHIFT); + PWR_CR2 = (reg32 | (pvdf_level << PWR_CR2_PVDFT_SHIFT) | (pvdr_level << PWR_CR2_PVDRT_SHIFT) | PWR_CR2_PVDE); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Disable Power Voltage Detector. +*/ +void pwr_disable_power_voltage_detect(void) +{ + PWR_CR2 &= ~PWR_CR2_PVDE; +} + +/**@}*/ diff --git a/lib/stm32/g0/rcc.c b/lib/stm32/g0/rcc.c new file mode 100644 index 00000000..c3f157ab --- /dev/null +++ b/lib/stm32/g0/rcc.c @@ -0,0 +1,550 @@ +/** @defgroup rcc_file RCC peripheral API + * + * @ingroup peripheral_apis + * + * @brief <b>libopencm3 STM32G0xx Reset and Clock Control</b> + * + * @author @htmlonly © @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com> + * + * @date 10 January 2019 + * + * This library supports the Reset and Clock Control System in the STM32 series + * of ARM Cortex Microcontrollers by ST Microelectronics. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +/**@{*/ + +#include <libopencm3/stm32/rcc.h> +#include <libopencm3/stm32/pwr.h> +#include <libopencm3/stm32/flash.h> +#include <libopencm3/cm3/assert.h> + +/* Set the default clock frequencies after reset. */ +uint32_t rcc_ahb_frequency = 16000000; +uint32_t rcc_apb1_frequency = 16000000; + +const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = { + [RCC_CLOCK_CONFIG_LSI_32KHZ] = { + /* 32khz from lsi, scale2, 0ws */ + .sysclock_source = RCC_LSI, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_0WS, + .voltage_scale = PWR_SCALE2, + .ahb_frequency = 32000, + .apb_frequency = 32000, + }, + [RCC_CLOCK_CONFIG_HSI_4MHZ] = { + /* 4mhz from hsi/4, scale2, 0ws */ + .sysclock_source = RCC_HSI, + .hsisys_div = RCC_CR_HSIDIV_DIV4, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_0WS, + .voltage_scale = PWR_SCALE2, + .ahb_frequency = 4000000, + .apb_frequency = 4000000, + }, + [RCC_CLOCK_CONFIG_HSI_16MHZ] = { + /* 16mhz from hsi, scale2, 0ws */ + .sysclock_source = RCC_HSI, + .hsisys_div = RCC_CR_HSIDIV_DIV1, + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_0WS, + .voltage_scale = PWR_SCALE2, + .ahb_frequency = 16000000, + .apb_frequency = 16000000, + }, + [RCC_CLOCK_CONFIG_HSI_PLL_32MHZ] = { + /* 32mhz from hsi via pll @ 128mhz / 4, scale1, 1ws */ + .sysclock_source = RCC_PLL, + .pll_source = RCC_PLLCFGR_PLLSRC_HSI16, + .pll_div = RCC_PLLCFGR_PLLM_DIV(1), + .pll_mul = RCC_PLLCFGR_PLLN_MUL(8), + .pllp_div = RCC_PLLCFGR_PLLP_DIV(4), + .pllq_div = RCC_PLLCFGR_PLLQ_DIV(4), + .pllr_div = RCC_PLLCFGR_PLLR_DIV(4), + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_1WS, + .voltage_scale = PWR_SCALE1, + .ahb_frequency = 32000000, + .apb_frequency = 32000000, + }, + [RCC_CLOCK_CONFIG_HSI_PLL_64MHZ] = { + /* 64mhz from hsi via pll @ 128mhz / 2, scale1, 2ws */ + .sysclock_source = RCC_PLL, + .pll_source = RCC_PLLCFGR_PLLSRC_HSI16, + .pll_div = RCC_PLLCFGR_PLLM_DIV(1), + .pll_mul = RCC_PLLCFGR_PLLN_MUL(8), + .pllp_div = RCC_PLLCFGR_PLLP_DIV(2), + .pllq_div = RCC_PLLCFGR_PLLQ_DIV(2), + .pllr_div = RCC_PLLCFGR_PLLR_DIV(2), + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_2WS, + .voltage_scale = PWR_SCALE1, + .ahb_frequency = 64000000, + .apb_frequency = 64000000, + }, + [RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ] = { + /* 64mhz from hse@12mhz via pll @ 128mhz / 2, scale1, 2ws */ + .sysclock_source = RCC_PLL, + .pll_source = RCC_PLLCFGR_PLLSRC_HSE, + .pll_div = RCC_PLLCFGR_PLLM_DIV(3), + .pll_mul = RCC_PLLCFGR_PLLN_MUL(32), + .pllp_div = RCC_PLLCFGR_PLLP_DIV(2), + .pllq_div = RCC_PLLCFGR_PLLQ_DIV(2), + .pllr_div = RCC_PLLCFGR_PLLR_DIV(2), + .hpre = RCC_CFGR_HPRE_NODIV, + .ppre = RCC_CFGR_PPRE_NODIV, + .flash_waitstates = FLASH_ACR_LATENCY_2WS, + .voltage_scale = PWR_SCALE1, + .ahb_frequency = 64000000, + .apb_frequency = 64000000, + }, +}; + +void rcc_osc_on(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR |= RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + default: + cm3_assert_not_reached(); + break; + } +} + +void rcc_osc_off(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case RCC_HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case RCC_HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case RCC_LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case RCC_LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + default: + cm3_assert_not_reached(); + break; + } +} + +bool rcc_is_osc_ready(enum rcc_osc osc) +{ + switch (osc) { + case RCC_PLL: + return RCC_CR & RCC_CR_PLLRDY; + case RCC_HSE: + return RCC_CR & RCC_CR_HSERDY; + case RCC_HSI: + return RCC_CR & RCC_CR_HSIRDY; + case RCC_LSE: + return RCC_BDCR & RCC_BDCR_LSERDY; + case RCC_LSI: + return RCC_CSR & RCC_CSR_LSIRDY; + default: + cm3_assert_not_reached(); + return 0; + } + return false; +} + +void rcc_wait_for_osc_ready(enum rcc_osc osc) +{ + while (!rcc_is_osc_ready(osc)); +} + +void rcc_css_enable(void) +{ + RCC_CR |= RCC_CR_CSSON; +} + +void rcc_css_disable(void) +{ + RCC_CR &= ~RCC_CR_CSSON; +} + +void rcc_css_int_clear(void) +{ + RCC_CICR |= RCC_CICR_CSSC; +} + +int rcc_css_int_flag(void) +{ + return ((RCC_CIFR & RCC_CIFR_CSSF) != 0); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the Source for the System Clock. + * @param osc Oscillator to use. + */ +void rcc_set_sysclk_source(enum rcc_osc osc) +{ + uint32_t reg32; + uint32_t sw = 0; + + switch (osc) { + case RCC_HSI: + sw = RCC_CFGR_SW_HSISYS; + break; + case RCC_HSE: + sw = RCC_CFGR_SW_HSE; + break; + case RCC_PLL: + sw = RCC_CFGR_SW_PLLRCLK; + break; + case RCC_LSE: + sw = RCC_CFGR_SW_LSE; + break; + case RCC_LSI: + sw = RCC_CFGR_SW_LSI; + break; + default: + cm3_assert_not_reached(); + return; + } + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT); + RCC_CFGR = (reg32 | (sw << RCC_CFGR_SW_SHIFT)); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Return the clock source which is used as system clock. + * @return rcc_osc system clock source + */ +enum rcc_osc rcc_system_clock_source(void) +{ + switch ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) { + case RCC_CFGR_SW_HSISYS: + return RCC_HSI; + case RCC_CFGR_SW_HSE: + return RCC_HSE; + case RCC_CFGR_SWS_PLLRCLK: + return RCC_PLL; + case RCC_CFGR_SW_LSE: + return RCC_LSE; + case RCC_CFGR_SW_LSI: + return RCC_LSI; + default: + cm3_assert_not_reached(); + return 0; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief Wait until system clock switched to given oscillator. + * @param osc Oscillator. + */ +void rcc_wait_for_sysclk_status(enum rcc_osc osc) +{ + uint32_t sws = 0; + + switch (osc) { + case RCC_PLL: + sws = RCC_CFGR_SWS_PLLRCLK; + break; + case RCC_HSE: + sws = RCC_CFGR_SWS_HSE; + break; + case RCC_HSI: + sws = RCC_CFGR_SWS_HSISYS; + break; + case RCC_LSI: + sws = RCC_CFGR_SWS_LSI; + break; + case RCC_LSE: + sws = RCC_CFGR_SWS_LSE; + break; + default: + cm3_assert_not_reached(); + break; + } + + while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) != sws); +} + +/** + * @brief Configure pll source. + * @param[in] pllsrc pll clock source @ref rcc_pllcfgr_pllsrc + */ +void rcc_set_pll_source(uint32_t pllsrc) +{ + uint32_t reg32; + + reg32 = RCC_PLLCFGR; + reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT); + RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT)); +} + +/** + * @brief Configure pll source and output frequencies. + * @param[in] source pll clock source @ref rcc_pllcfgr_pllsrc + * @param[in] pllm pll vco division factor @ref rcc_pllcfgr_pllm + * @param[in] plln pll vco multiplation factor @ref rcc_pllcfgr_plln + * @param[in] pllp pll P clock output division factor @ref rcc_pllcfgr_pllp + * @param[in] pllq pll Q clock output division factor @ref rcc_pllcfgr_pllq + * @param[in] pllr pll R clock output (sysclock pll) division factor @ref rcc_pllcfgr_pllr + */ +void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq, uint32_t pllr) +{ + RCC_PLLCFGR = (source << RCC_PLLCFGR_PLLSRC_SHIFT) | + (pllm << RCC_PLLCFGR_PLLM_SHIFT) | + (plln << RCC_PLLCFGR_PLLN_SHIFT) | + (pllp << RCC_PLLCFGR_PLLP_SHIFT) | + (pllq << RCC_PLLCFGR_PLLQ_SHIFT) | + (pllr << RCC_PLLCFGR_PLLR_SHIFT); +} + +/** + * @brief Enable PLL P clock output. + * @param[in] enable or disable P clock output + */ +void rcc_enable_pllp(bool enable) +{ + if (enable) { + RCC_PLLCFGR |= RCC_PLLCFGR_PLLPEN; + } else { + RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLPEN; + } +} + +/** + * @brief Enable PLL Q clock output. + * @param[in] enable or disable Q clock output + */ +void rcc_enable_pllq(bool enable) +{ + if (enable) { + RCC_PLLCFGR |= RCC_PLLCFGR_PLLQEN; + } else { + RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLQEN; + } +} + +/** + * @brief Enable PLL R clock output. + * @param[in] enable or disable R clock output + */ +void rcc_enable_pllr(bool enable) +{ + if (enable) { + RCC_PLLCFGR |= RCC_PLLCFGR_PLLREN; + } else { + RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLREN; + } +} + +/** + * @brief Configure APB peripheral clock prescaler + * @param[in] ppre APB clock prescaler value @ref rcc_cfgr_ppre + */ +void rcc_set_ppre(uint32_t ppre) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_PPRE_MASK << RCC_CFGR_PPRE_SHIFT); + RCC_CFGR = (reg32 | (ppre << RCC_CFGR_PPRE_SHIFT)); +} + +/** + * @brief Configure AHB peripheral clock prescaler + * @param[in] hpre AHB clock prescaler value @ref rcc_cfgr_hpre + */ +void rcc_set_hpre(uint32_t hpre) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT); + RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT)); +} + +/** + * @brief Configure HSI16 clock division factor to feed SYSCLK + * @param[in] hsidiv HSYSSIS clock division factor @ref rcc_cr_hsidiv + */ +void rcc_set_hsisys_div(uint32_t hsidiv) +{ + uint32_t reg32; + + reg32 = RCC_CR; + reg32 &= ~(RCC_CR_HSIDIV_MASK << RCC_CR_HSIDIV_SHIFT); + RCC_CR = (reg32 | (hsidiv << RCC_CR_HSIDIV_SHIFT)); +} + +/** + * @brief Configure mco prescaler. + * @param[in] mcopre prescaler value @ref rcc_cfgr_mcopre + */ +void rcc_set_mcopre(uint32_t mcopre) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_MCOPRE_MASK << RCC_CFGR_MCOPRE_SHIFT); + RCC_CFGR = (reg32 | (mcopre << RCC_CFGR_MCOPRE_SHIFT)); +} + +/** + * @brief Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). taking care of flash/pwr and src configuration + * @param clock rcc_clock_scale with desired parameters + */ +void rcc_clock_setup(const struct rcc_clock_scale *clock) +{ + if (clock->sysclock_source == RCC_PLL) { + enum rcc_osc pll_source; + + if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE) + pll_source = RCC_HSE; + else + pll_source = RCC_HSI; + + /* start pll src osc. */ + rcc_osc_on(pll_source); + rcc_wait_for_osc_ready(pll_source); + + /* stop pll to reconfigure it. */ + rcc_osc_off(RCC_PLL); + while (rcc_is_osc_ready(RCC_PLL)); + + rcc_set_main_pll(clock->pll_source, clock->pll_div, clock->pll_mul, clock->pllp_div, clock->pllq_div, clock->pllr_div); + + rcc_enable_pllr(true); + } else if (clock->sysclock_source == RCC_HSI) { + rcc_set_hsisys_div(clock->hsisys_div); + } + + rcc_periph_clock_enable(RCC_PWR); + pwr_set_vos_scale(clock->voltage_scale); + + flash_set_ws(clock->flash_waitstates); + + /* enable flash prefetch if we have at least 1WS */ + if (clock->flash_waitstates > FLASH_ACR_LATENCY_0WS) + flash_prefetch_enable(); + else + flash_prefetch_disable(); + + rcc_set_hpre(clock->hpre); + rcc_set_ppre(clock->ppre); + + rcc_osc_on(clock->sysclock_source); + rcc_wait_for_osc_ready(clock->sysclock_source); + + rcc_set_sysclk_source(clock->sysclock_source); + rcc_wait_for_sysclk_status(clock->sysclock_source); + + rcc_ahb_frequency = clock->ahb_frequency; + rcc_apb1_frequency = clock->apb_frequency; +} + +/** + * @brief Setup RNG Peripheral Clock Divider + * @param rng_div clock divider @ref rcc_ccipr_rngdiv + */ +void rcc_set_rng_clk_div(uint32_t rng_div) +{ + uint32_t reg32 = RCC_CCIPR & ~(RCC_CCIPR_RNGDIV_MASK << RCC_CCIPR_RNGDIV_SHIFT); + RCC_CCIPR = reg32 | (rng_div << RCC_CCIPR_RNGDIV_SHIFT); +} + +/** + * @brief Set the peripheral clock source + * @param periph peripheral of choice, eg XXX_BASE + * @param sel periphral clock source + */ +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) +{ + uint8_t shift; + uint32_t mask; + + switch (periph) { + case ADC1_BASE: + shift = RCC_CCIPR_ADCSEL_SHIFT; + mask = RCC_CCIPR_ADCSEL_MASK; + break; + case RNG_BASE: + shift = RCC_CCIPR_RNGSEL_SHIFT; + mask = RCC_CCIPR_RNGSEL_MASK; + break; + case TIM1_BASE: + shift = RCC_CCIPR_TIM1SEL_SHIFT; + mask = RCC_CCIPR_TIM1SEL_MASK; + break; + case LPTIM1_BASE: + shift = RCC_CCIPR_LPTIM1SEL_SHIFT; + mask = RCC_CCIPR_LPTIM1SEL_MASK; + break; + case LPTIM2_BASE: + shift = RCC_CCIPR_LPTIM2SEL_SHIFT; + mask = RCC_CCIPR_LPTIM2SEL_MASK; + break; + case CEC_BASE: + shift = RCC_CCIPR_CECSEL_SHIFT; + mask = RCC_CCIPR_CECSEL_MASK; + break; + case USART2_BASE: + shift = RCC_CCIPR_USART2SEL_SHIFT; + mask = RCC_CCIPR_USART2SEL_MASK; + break; + case USART1_BASE: + shift = RCC_CCIPR_USART1SEL_SHIFT; + mask = RCC_CCIPR_USART1SEL_MASK; + break; + default: + cm3_assert_not_reached(); + return; + } + + uint32_t reg32 = RCC_CCIPR & ~(mask << shift); + RCC_CCIPR = reg32 | (sel << shift); +} + +/**@}*/ diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index cd3e27c3..857d3d5c 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32l0 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi -#PREFIX ?= arm-elf -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -36,25 +34,26 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = gpio.o rcc.o desig.o -OBJS += pwr_common_v1.o pwr_common_v2.o -OBJS += timer_common_all.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o - -OBJS += gpio_common_all.o gpio_common_f0234.o rcc_common_all.o -OBJS += adc_common_v2.o -OBJS += crs_common_all.o -OBJS += dma_common_l1f013.o -OBJS += exti_common_all.o -OBJS += flash.o flash_common_all.o flash_common_l01.o -OBJS += i2c_common_v2.o -OBJS += rng_common_v1.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += iwdg_common_all.o -OBJS += rtc_common_l1f024.o - -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v2.o +OBJS += adc_common_v2.o +OBJS += crs_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o dma_common_csel.o +OBJS += exti_common_all.o +OBJS += flash_common_all.o flash_common_l01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o +OBJS += pwr_common_v1.o pwr_common_v2.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o + +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v2.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l0/gpio.c b/lib/stm32/l0/gpio.c deleted file mode 100644 index 9382ece2..00000000 --- a/lib/stm32/l0/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - * - * @ingroup STM32L0xx - * - * @brief <b>libopencm3 STM32L0xx General Purpose I/O</b> - * - * @version 1.0.0 - * - * @date 8 September 2014 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/gpio.h> diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index a6e398e2..39bdaff7 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32L0xx-rcc-file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32L0xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32L0xx Reset and Clock Control</b> * @@ -105,7 +105,7 @@ void rcc_osc_off(enum rcc_osc osc) * Clear the interrupt flag that was set when a clock oscillator became ready * to use. * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID */ void rcc_osc_ready_int_clear(enum rcc_osc osc) { @@ -137,7 +137,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID */ void rcc_osc_ready_int_enable(enum rcc_osc osc) { @@ -169,7 +169,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID */ void rcc_osc_ready_int_disable(enum rcc_osc osc) { @@ -201,7 +201,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc) /*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag * - * @param[in] osc enum ::osc_t. Oscillator ID + * @param[in] osc Oscillator ID * @returns int. Boolean value for flag set. */ int rcc_osc_ready_int_flag(enum rcc_osc osc) @@ -279,8 +279,7 @@ void rcc_set_hsi48_source_pll(void) /*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. * - * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, HSI16, MSI and PLL have - * effect. + * @param[in] osc Oscillator ID. Only HSE, HSI16, MSI and PLL have effect. */ void rcc_set_sysclk_source(enum rcc_osc osc) @@ -310,7 +309,7 @@ void rcc_set_sysclk_source(enum rcc_osc osc) * * @note This only has effect when the PLL is disabled. * - * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf + * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pmf */ void rcc_set_pll_multiplier(uint32_t factor) @@ -326,7 +325,7 @@ void rcc_set_pll_multiplier(uint32_t factor) * * @note This only has effect when the PLL is disabled. * - * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf + * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pdf */ void rcc_set_pll_divider(uint32_t factor) @@ -354,7 +353,7 @@ void rcc_set_pll_source(uint32_t pllsrc) * * @note The APB1 clock frequency must not exceed 32MHz. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre + * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb1pre */ void rcc_set_ppre1(uint32_t ppre) @@ -369,7 +368,7 @@ void rcc_set_ppre1(uint32_t ppre) * * @note The APB2 clock frequency must not exceed 32MHz. * - * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre + * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb2pre */ void rcc_set_ppre2(uint32_t ppre) @@ -391,9 +390,115 @@ void rcc_set_hpre(uint32_t hpre) RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT); } -/** - * Set up sysclock with PLL from HSI16 - * @param clock full struct with desired parameters +/*---------------------------------------------------------------------------*/ +/** @brief Set the range of the MSI oscillator +* + * @param msi_range desired range @ref rcc_icscr_msirange + */ +void rcc_set_msi_range(uint32_t msi_range) +{ + uint32_t reg32 = RCC_ICSCR & ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT); + RCC_ICSCR = reg32 | (msi_range << RCC_ICSCR_MSIRANGE_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the LPTIM1 clock source +* + * @param lptim1_sel peripheral clock source @ref rcc_ccpipr_lptim1sel + */ +void rcc_set_lptim1_sel(uint32_t lptim1_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_LPTIM1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT); + RCC_CCIPR |= (lptim1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT); +} + + +/*---------------------------------------------------------------------------*/ +/** @brief Set the LPUART1 clock source +* + * @param lpuart1_sel periphral clock source @ref rcc_ccpipr_lpuart1sel + */ +void rcc_set_lpuart1_sel(uint32_t lpuart1_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_LPUART1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT); + RCC_CCIPR |= (lpuart1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the USART1 clock source +* + * @param usart1_sel periphral clock source @ref rcc_ccpipr_usart1sel + */ +void rcc_set_usart1_sel(uint32_t usart1_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT); + RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the USART2 clock source +* + * @param usart2_sel periphral clock source @ref rcc_ccpipr_usartxsel + */ +void rcc_set_usart2_sel(uint32_t usart2_sel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_USART2SEL_MASK << RCC_CCIPR_USART2SEL_SHIFT); + RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the peripheral clock source + * @param periph peripheral of desire, eg XXX_BASE + * @param sel peripheral clock source + */ +void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel) +{ + uint8_t shift; + uint32_t mask; + + switch (periph) { + case LPTIM1_BASE: + shift = RCC_CCIPR_LPTIM1SEL_SHIFT; + mask = RCC_CCIPR_LPTIM1SEL_MASK; + break; + + case I2C3_BASE: + shift = RCC_CCIPR_I2C3SEL_SHIFT; + mask = RCC_CCIPR_I2C3SEL_MASK; + break; + + case I2C1_BASE: + shift = RCC_CCIPR_I2C1SEL_SHIFT; + mask = RCC_CCIPR_I2C1SEL_MASK; + break; + + case LPUART1_BASE: + shift = RCC_CCIPR_LPUART1SEL_SHIFT; + mask = RCC_CCIPR_LPUART1SEL_MASK; + break; + + case USART2_BASE: + shift = RCC_CCIPR_USART2SEL_SHIFT; + mask = RCC_CCIPR_USART2SEL_MASK; + break; + + case USART1_BASE: + shift = RCC_CCIPR_USART1SEL_SHIFT; + mask = RCC_CCIPR_USART1SEL_MASK; + break; + + default: + return; + } + + uint32_t reg32 = RCC_CCIPR & ~(mask << shift); + RCC_CCIPR = reg32 | (sel << shift); +} + +/** @brief RCC Setup PLL and use it as Sysclk source. + * + * @param[in] clock full struct with desired parameters + * */ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) { @@ -422,6 +527,7 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) /* Set up the PLL */ rcc_set_pll_multiplier(clock->pll_mul); rcc_set_pll_divider(clock->pll_div); + rcc_set_pll_source(clock->pll_source); rcc_osc_on(RCC_PLL); rcc_wait_for_osc_ready(RCC_PLL); diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile index ec1ea928..b5853051 100644 --- a/lib/stm32/l1/Makefile +++ b/lib/stm32/l1/Makefile @@ -20,10 +20,8 @@ LIBNAME = libopencm3_stm32l1 SRCLIBDIR ?= ../.. -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -35,22 +33,27 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) # ARFLAGS = rcsv ARFLAGS = rcs -OBJS = desig.o flash.o rcc.o dma.o lcd.o -OBJS += crc_common_all.o dac_common_all.o -OBJS += dma_common_l1f013.o -OBJS += flash_common_all.o flash_common_l01.o -OBJS += gpio_common_all.o gpio_common_f0234.o -OBJS += i2c_common_v1.o iwdg_common_all.o -OBJS += pwr_common_v1.o pwr_common_v2.o rtc_common_l1f024.o -OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o -OBJS += timer_common_all.o -OBJS += usart_common_all.o usart_common_f124.o -OBJS += exti_common_all.o -OBJS += rcc_common_all.o -OBJS += adc.o adc_common_v1.o +OBJS += adc.o adc_common_v1.o adc_common_v1_multi.o +OBJS += flash.o +OBJS += crc_common_all.o +OBJS += dac_common_all.o +OBJS += desig.o +OBJS += dma_common_l1f013.o +OBJS += exti_common_all.o +OBJS += flash_common_all.o flash_common_l01.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v1.o +OBJS += iwdg_common_all.o +OBJS += lcd.o +OBJS += pwr_common_v1.o pwr_common_v2.o +OBJS += rcc.o rcc_common_all.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o +OBJS += timer.o timer_common_all.o +OBJS += usart_common_all.o usart_common_f124.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v1.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v1.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/stm32/l1/adc.c b/lib/stm32/l1/adc.c index 1768437d..e2d3e4b8 100644 --- a/lib/stm32/l1/adc.c +++ b/lib/stm32/l1/adc.c @@ -29,23 +29,6 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*---------------------------------------------------------------------------*/ -/** @brief ADC Power On - -If the ADC is in power-down mode then it is powered up. The application needs -to wait a time of about 3 microseconds for stabilization before using the ADC. -If the ADC is already on this function call will have no effect. - * NOTE Common with F4 and F2 - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_power_on(uint32_t adc) -{ - ADC_CR2(adc) |= ADC_CR2_ADON; -} - - /*----------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel @@ -102,97 +85,6 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time) ADC_SMPR3(adc) = reg32; } -/*----------------------------------------------------------------------------*/ -/** @brief ADC Enable The Temperature Sensor - -This enables both the sensor and the reference voltage measurements on channels -16 and 17. - -*/ -void adc_enable_temperature_sensor() -{ - ADC_CCR |= ADC_CCR_TSVREFE; -} - -/*----------------------------------------------------------------------------*/ -/** @brief ADC Disable The Temperature Sensor - -Disabling this will reduce power consumption from the sensor and the reference -voltage measurements. - -*/ -void adc_disable_temperature_sensor() -{ - ADC_CCR &= ~ADC_CCR_TSVREFE; -} - -/*----------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Regular Channels - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -*/ - -void adc_disable_external_trigger_regular(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; -} - -/*----------------------------------------------------------------------------*/ -/** @brief ADC Disable an External Trigger for Injected Channels - -@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base. -*/ - -void adc_disable_external_trigger_injected(uint32_t adc) -{ - ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Regular Channels - -This enables an external trigger for set of defined regular channels, and sets -the polarity of the trigger event: rising or falling edge or both. Note that if -the trigger polarity is zero, triggering is disabled. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_regular -*/ - -void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - -/*---------------------------------------------------------------------------*/ -/** @brief ADC Enable an External Trigger for Injected Channels - -This enables an external trigger for set of defined injected channels, and sets -the polarity of the trigger event: rising or falling edge or both. - -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref -adc_trigger_polarity_injected -*/ - -void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, - uint32_t polarity) -{ - uint32_t reg32 = ADC_CR2(adc); - - reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK); - reg32 |= (trigger | polarity); - ADC_CR2(adc) = reg32; -} - /**@}*/ diff --git a/lib/stm32/l1/dac.c b/lib/stm32/l1/dac.c deleted file mode 100644 index ed118b4d..00000000 --- a/lib/stm32/l1/dac.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dac_file DAC - -@ingroup STM32L1xx - -@brief <b>libopencm3 STM32L1xx DAC</b> - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/dac.h> diff --git a/lib/stm32/l1/dma.c b/lib/stm32/l1/dma.c deleted file mode 100644 index 6f4622d2..00000000 --- a/lib/stm32/l1/dma.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup dma_file DMA - * - * @ingroup STM32L1xx - * - * @brief <b>libopencm3 STM32L1xx DMA</b> - * - * @version 1.0.0 - * - * @date 10 July 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/dma.h> diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c index 5e176b05..dfd90d25 100644 --- a/lib/stm32/l1/flash.c +++ b/lib/stm32/l1/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32L1xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32L1xx FLASH</b> * diff --git a/lib/stm32/l1/gpio.c b/lib/stm32/l1/gpio.c deleted file mode 100644 index 46ea658a..00000000 --- a/lib/stm32/l1/gpio.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup gpio_file GPIO - -@ingroup STM32L1xx - -@brief <b>libopencm3 STM32L1xx General Purpose I/O</b> - -@version 1.0.0 - -@date 18 August 2012 - -LGPL License Terms @ref lgpl_license -*/ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/gpio.h> diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index e9f7bd68..44eac07b 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup STM32L1xx-rcc-file RCC +/** @defgroup rcc_file RCC peripheral API -@ingroup STM32L1xx +@ingroup peripheral_apis @brief <b>libopencm3 STM32L1xx Reset and Clock Control</b> @@ -535,6 +535,10 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock) flash_prefetch_enable(); flash_set_ws(clock->flash_waitstates); + /* Disable PLL oscillator before changing its configuration. */ + rcc_osc_off(RCC_PLL); + + /* Configure the PLL oscillator. */ rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div); diff --git a/lib/stm32/l1/rtc.c b/lib/stm32/l1/rtc.c deleted file mode 100644 index 5628aa7e..00000000 --- a/lib/stm32/l1/rtc.c +++ /dev/null @@ -1,31 +0,0 @@ -/** @defgroup rtc_file RTC - * - * @ingroup STM32L1xx - * - * @brief <b>libopencm3 STM32L1xx RTC</b> - * - * @version 1.0.0 - * - * @date 4 March 2013 - * - * LGPL License Terms @ref lgpl_license - */ - -/* - * This file is part of the libopencm3 project. - * - * This library is free software: you can redistribute it and/or modify - * it under the terms of the GNU Lesser General Public License as published by - * the Free Software Foundation, either version 3 of the License, or - * (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public License - * along with this library. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <libopencm3/stm32/rtc.h> diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c index ab69c622..43f8d541 100644 --- a/lib/stm32/l1/timer.c +++ b/lib/stm32/l1/timer.c @@ -1,7 +1,5 @@ -/** @defgroup timer_file Timers - -@ingroup STM32L1xx - +/** @defgroup timer_file TIMER peripheral API +@ingroup peripheral_apis @brief <b>libopencm3 STM32L1xx Timers</b> @version 1.0.0 @@ -30,18 +28,17 @@ * along with this library. If not, see <http://www.gnu.org/licenses/>. */ -/**@{*/ - #include <libopencm3/stm32/timer.h> +/**@{*/ + /*---------------------------------------------------------------------------*/ /** @brief Set Timer Option Set timer options register on TIM2 or TIM3, used for trigger remapping. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: -@ref tim3_opt_trigger_remap. +@param[in] option Desired option @ref tim2_opt_trigger_remap and @ref tim3_opt_trigger_remap */ void timer_set_option(uint32_t timer_peripheral, uint32_t option) diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index a2748535..6a1594ff 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -21,10 +21,8 @@ LIBNAME = libopencm3_stm32l4 SRCLIBDIR ?= ../.. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -37,28 +35,28 @@ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -# Specific objs -OBJS = adc.o flash.o pwr.o rcc.o - -# common/shared objs -OBJS += rcc_common_all.o -OBJS += gpio_common_all.o gpio_common_f0234.o -OBJS += exti_common_all.o -OBJS += adc_common_v2.o adc_common_v2_multi.o -OBJS += crc_common_all.o crc_v2.o -OBJS += crs_common_all.o -OBJS += flash_common_all.o flash_common_f.o flash_common_idcache.o -OBJS += rng_common_v1.o -OBJS += timer_common_all.o -OBJS += i2c_common_v2.o -OBJS += usart_common_all.o usart_common_v2.o -OBJS += dma_common_l1f013.o -OBJS += iwdg_common_all.o -OBJS += rtc_common_l1f024.o -OBJS += spi_common_all.o spi_common_v2.o +OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o +OBJS += can.o +OBJS += crc_common_all.o crc_v2.o +OBJS += crs_common_all.o +OBJS += dac_common_all.o +OBJS += dma_common_l1f013.o dma_common_csel.o +OBJS += exti_common_all.o +OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o +OBJS += gpio_common_all.o gpio_common_f0234.o +OBJS += i2c_common_v2.o +OBJS += iwdg_common_all.o +OBJS += lptimer_common_all.o +OBJS += pwr.o +OBJS += rcc.o rcc_common_all.o +OBJS += rng_common_v1.o +OBJS += rtc_common_l1f024.o +OBJS += spi_common_all.o spi_common_v2.o +OBJS += timer_common_all.o +OBJS += usart_common_all.o usart_common_v2.o -OBJS += usb.o usb_control.o usb_standard.o usb_msc.o -OBJS += st_usbfs_core.o st_usbfs_v2.o +OBJS += usb.o usb_control.o usb_standard.o usb_msc.o +OBJS += st_usbfs_core.o st_usbfs_v2.o VPATH += ../../usb:../:../../cm3:../common VPATH += ../../ethernet diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c index 58374b29..16007ee6 100644 --- a/lib/stm32/l4/flash.c +++ b/lib/stm32/l4/flash.c @@ -1,6 +1,6 @@ -/** @defgroup flash_file FLASH +/** @defgroup flash_file FLASH peripheral API * - * @ingroup STM32L4xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32L4xx FLASH</b> * @@ -108,15 +108,16 @@ void flash_lock_option_bytes(void) FLASH_CR |= FLASH_CR_OPTLOCK; } -/** @brief Program a 32 bit Word to FLASH - * This performs all operations necessary to program a 32 bit word to FLASH - * memory. The program error flag should be checked separately for the event - * that memory was not properly erased. +/** @brief Program a 64 bit word to FLASH + * + * This performs all operations necessary to program a 64 bit word to FLASH memory. + * The program error flag should be checked separately for the event that memory + * was not properly erased. * * @param[in] address Starting address in Flash. - * @param[in] data word to write + * @param[in] data Double word to write */ -void flash_program_word(uint32_t address, uint32_t data) +void flash_program_double_word(uint32_t address, uint64_t data) { /* Ensure that all flash operations are complete. */ flash_wait_for_last_operation(); @@ -124,8 +125,9 @@ void flash_program_word(uint32_t address, uint32_t data) /* Enable writes to flash. */ FLASH_CR |= FLASH_CR_PG; - /* Program the word. */ - MMIO32(address) = data; + /* Program the each word separately. */ + MMIO32(address) = (uint32_t)data; + MMIO32(address+4) = (uint32_t)(data >> 32); /* Wait for the write to complete. */ flash_wait_for_last_operation(); @@ -140,16 +142,12 @@ void flash_program_word(uint32_t address, uint32_t data) * memory was not properly erased. * @param[in] address Starting address in Flash. * @param[in] data Pointer to start of data block. - * @param[in] len Length of data block. + * @param[in] len Length of data block in bytes (multiple of 8). */ void flash_program(uint32_t address, uint8_t *data, uint32_t len) { - /* TODO: Use dword and word size program operations where possible for - * turbo speed. - */ - uint32_t i; - for (i = 0; i < len; i++) { - flash_program_word(address+i, data[i]); + for (uint32_t i = 0; i < len; i += 8) { + flash_program_double_word(address+i, *(uint64_t*)(data + i)); } } @@ -198,8 +196,8 @@ void flash_program_option_bytes(uint32_t data) flash_unlock_option_bytes(); } - FLASH_OPTR = data & ~0x3; - FLASH_OPTR |= FLASH_CR_OPTSTRT; + FLASH_OPTR = data; + FLASH_CR |= FLASH_CR_OPTSTRT; flash_wait_for_last_operation(); } /**@}*/ diff --git a/lib/stm32/l4/pwr.c b/lib/stm32/l4/pwr.c index 7bfc8361..e6bd877a 100644 --- a/lib/stm32/l4/pwr.c +++ b/lib/stm32/l4/pwr.c @@ -1,6 +1,6 @@ -/** @defgroup pwr_file PWR +/** @defgroup pwr_file PWR peripheral API * - * @ingroup STM32L4xx + * @ingroup peripheral_apis * * @brief <b>libopencm3 STM32L4xx Power Control</b> * @@ -52,4 +52,24 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale) } PWR_CR1 = reg32; } + +/** Disable Backup Domain Write Protection + * + * This allows backup domain registers to be changed. These registers are write + * protected after a reset. + */ +void pwr_disable_backup_domain_write_protect(void) +{ + PWR_CR1 |= PWR_CR1_DBP; +} + +/** Re-enable Backup Domain Write Protection + * + * This protects backup domain registers from inadvertent change. + */ +void pwr_enable_backup_domain_write_protect(void) +{ + PWR_CR1 &= ~PWR_CR1_DBP; +} + /**@}*/ diff --git a/lib/stm32/l4/rcc.c b/lib/stm32/l4/rcc.c index d1fb0c48..1d3e3472 100644 --- a/lib/stm32/l4/rcc.c +++ b/lib/stm32/l4/rcc.c @@ -1,6 +1,6 @@ -/** @defgroup rcc_file RCC +/** @defgroup rcc_file RCC peripheral API * - * @ingroup STM32L4xx + * @ingroup peripheral_apis * * @section rcc_l4_api_ex Reset and Clock Control API. * @@ -369,4 +369,69 @@ void rcc_set_msi_range_standby(uint32_t msi_range) RCC_CSR = reg; } +/** Enable PLL Output + * + * - P (RCC_PLLCFGR_PLLPEN) + * - Q (RCC_PLLCFGR_PLLQEN) + * - R (RCC_PLLCFGR_PLLREN) + * + * @param pllout One or more of the definitions above + */ +void rcc_pll_output_enable(uint32_t pllout) +{ + RCC_PLLCFGR |= pllout; +} + +/** Set clock source for 48MHz clock + * + * The 48 MHz clock is derived from one of the four following sources: + * - main PLL VCO (RCC_CCIPR_CLK48SEL_PLL) + * - PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q) + * - MSI clock (RCC_CCIPR_CLK48SEL_MSI) + * - HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48) + * + * @param clksel One of the definitions above + */ +void rcc_set_clock48_source(uint32_t clksel) +{ + RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT); + RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT); +} + + +/** Enable the RTC clock */ +void rcc_enable_rtc_clock(void) +{ + RCC_BDCR |= RCC_BDCR_RTCEN; +} + +/** Disable the RTC clock */ +void rcc_disable_rtc_clock(void) +{ + RCC_BDCR &= ~RCC_BDCR_RTCEN; +} + +/** Set the source for the RTC clock + * @param[in] clk ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI. + */ +void rcc_set_rtc_clock_source(enum rcc_osc clk) +{ + RCC_BDCR &= ~(RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT); + + switch (clk) { + case RCC_HSE: + RCC_BDCR |= (RCC_BDCR_RTCSEL_HSEDIV32 << RCC_BDCR_RTCSEL_SHIFT); + break; + case RCC_LSE: + RCC_BDCR |= (RCC_BDCR_RTCSEL_LSE << RCC_BDCR_RTCSEL_SHIFT); + break; + case RCC_LSI: + RCC_BDCR |= (RCC_BDCR_RTCSEL_LSI << RCC_BDCR_RTCSEL_SHIFT); + break; + default: + /* none selected */ + break; + } +} + /**@}*/ diff --git a/lib/swm050/Makefile b/lib/swm050/Makefile new file mode 100644 index 00000000..977f5f74 --- /dev/null +++ b/lib/swm050/Makefile @@ -0,0 +1,40 @@ +## +## This file is part of the libopencm3 project. +## +## Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> +## +## This library is free software: you can redistribute it and/or modify +## it under the terms of the GNU Lesser General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This library is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU Lesser General Public License for more details. +## +## You should have received a copy of the GNU Lesser General Public License +## along with this library. If not, see <http://www.gnu.org/licenses/>. +## + +LIBNAME = libopencm3_swm050 +SRCLIBDIR ?= .. + +CC = $(PREFIX)gcc +AR = $(PREFIX)ar +TGT_CFLAGS = -Os \ + -Wall -Wextra -Wimplicit-function-declaration \ + -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ + -Wundef -Wshadow \ + -I../../include -fno-common \ + -mcpu=cortex-m0 $(FP_FLAGS) -mthumb -Wstrict-prototypes \ + -ffunction-sections -fdata-sections -MD -DSWM050 +TGT_CFLAGS += $(DEBUG_FLAGS) +TGT_CFLAGS += $(STANDARD_FLAGS) +ARFLAGS = rcs + +OBJS += gpio.o + +VPATH += ../cm3 + +include ../Makefile.include diff --git a/lib/swm050/gpio.c b/lib/swm050/gpio.c new file mode 100644 index 00000000..fdf50996 --- /dev/null +++ b/lib/swm050/gpio.c @@ -0,0 +1,197 @@ +/** @addtogroup gpio_file GPIO peripheral API + * @ingroup peripheral_apis + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <libopencm3/swm050/gpio.h> + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Set a Group of Pins + +Set one or more pins of GPIO to 1. Please note that this chip doesn't support +atomic pin setting. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_set(uint16_t gpios) +{ + GPIO_DATA |= gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Clear a Group of Pins + +Set one or more pins of GPIO to 0. Please note that this chip doesn't support +atomic pin setting. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_clear(uint16_t gpios) +{ + GPIO_DATA &= ~gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Read a Group of Pins. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be read, use bitwise OR '|' to separate + them. +@return The pin values as a bitfield. The bit position of the pin + value returned corresponds to the pin number. +*/ +uint16_t gpio_get(uint16_t gpios) +{ + return GPIO_EXT & gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Toggle a Group of Pins + +Toggle one or more pins of GPIO. The non-toggled pins are not affected. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_toggle(uint16_t gpios) +{ + uint32_t curr_status = GPIO_DATA & gpios; + GPIO_DATA = (GPIO_DATA & (~gpios)) | (~curr_status); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the direction of a Group of Pins to Input + +Set the direction of one or more pins of GPIO to input. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_input(uint16_t gpios) +{ + GPIO_DIR &= ~gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Set the direction of a Group of Pins to Output + +Set the direction of one or more pins of GPIO to output. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +*/ +void gpio_output(uint16_t gpios) +{ + GPIO_DIR |= gpios; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Select the alternative function of a Group of Pins + +Select the alternative function of one or more pins of GPIO. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +@param[in] af_en Whether alternative function is selected +*/ +void gpio_sel_af(uint16_t gpios, bool af_en) +{ + if (gpios & GPIO0) { + GPIO_SEL = (GPIO_SEL & (~0x3)) | (af_en ? 0x1 : 0x0); + } + if (gpios & GPIO1) { + GPIO_SEL = (GPIO_SEL & (~0xc)) | (af_en ? 0x4 : 0x0); + } + if (gpios & GPIO2) { + GPIO_SEL = (GPIO_SEL & (~0x30)) | (af_en ? 0x10 : 0x0); + } + if (gpios & GPIO7) { + GPIO_SEL = (GPIO_SEL & (~0xc000)) | (af_en ? 0x4000 : 0x0); + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the internal pull-up of a Group of Pins + +Enable or disable the internal pull-up of one or more pins of GPIO. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +@param[in] en Bool. Whether pull-up is enabled +*/ +void gpio_pullup(uint16_t gpios, bool en) +{ + if (en) { + GPIO_PULLUP |= gpios; + } else { + GPIO_PULLUP &= ~gpios; + } +} + +/*---------------------------------------------------------------------------*/ +/** @brief Enable the input function of a Group of Pins + +Enable or disable the input function of one or more pins of GPIO. Disabling +the input function of pins decreases the power usage of the MCU. + +@param[in] gpios Pin identifiers @ref gpio_pin_id + If multiple pins are to be changed, use bitwise OR '|' to separate + them. +@param[in] en true to enable input function. +*/ +void gpio_in_en(uint16_t gpios, bool en) +{ + if (en) { + GPIO_INEN &= ~gpios; + } else { + GPIO_INEN |= gpios; + } +} + + +/*---------------------------------------------------------------------------*/ +/** @brief Select the SWD function of GPIO 1/2 + +Enable or disable the SWD debugging port at GPIO 1/2. When SWD debugging port +is enabled, GPIO and AF of the SWD pins will be both unavailable. + +@param[in] en true to enable SWD. +*/ +void gpio_sel_swd(bool en) +{ + if (en) { + SWD_SEL = 1; + } else { + SWD_SEL = 0; + } +} + +/**@}*/ diff --git a/lib/usb/usb_efm32.c b/lib/usb/usb_efm32.c index 5768947c..4f7fa254 100644 --- a/lib/usb/usb_efm32.c +++ b/lib/usb/usb_efm32.c @@ -1,3 +1,9 @@ +/** @addtogroup usb_file USB peripheral API + * @ingroup peripheral_apis + * + * @sa usb_defines + * @copyright See @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -26,6 +32,8 @@ #include <libopencm3/usb/usbd.h> #include "usb_private.h" +/**@{*/ + /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 256 @@ -424,3 +432,5 @@ const struct _usbd_driver efm32lg_usb_driver = { .set_address_before_status = 1, .rx_fifo_size = RX_FIFO_SIZE, }; + +/**@}*/
\ No newline at end of file diff --git a/lib/usb/usb_efm32hg.c b/lib/usb/usb_efm32hg.c index 96f22c1e..5459566e 100644 --- a/lib/usb/usb_efm32hg.c +++ b/lib/usb/usb_efm32hg.c @@ -1,3 +1,13 @@ +/** @addtogroup usb_file USB peripheral API + * @ingroup peripheral_apis + * + * @brief USB Peripheral for Happy Gecko + * + * The Happy Gecko uses the "standard" usb_dwc_otg core. + * + * @sa usb_defines + * @copyright See @ref lgpl_license + */ /* * This file is part of the libopencm3 project. * @@ -28,6 +38,8 @@ #include "usb_private.h" #include "usb_dwc_common.h" +/**@{*/ + /* Receive FIFO size in 32-bit words. */ #define RX_FIFO_SIZE 256 @@ -124,3 +136,5 @@ const struct _usbd_driver efm32hg_usb_driver = { .set_address_before_status = 1, .rx_fifo_size = RX_FIFO_SIZE, }; + +/**@}*/
\ No newline at end of file diff --git a/lib/vf6xx/Makefile b/lib/vf6xx/Makefile index d87247be..c8bfd2a3 100644 --- a/lib/vf6xx/Makefile +++ b/lib/vf6xx/Makefile @@ -22,10 +22,8 @@ LIBNAME = libopencm3_vf6xx SRCLIBDIR ?= .. FP_FLAGS ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16 -PREFIX ?= arm-none-eabi - -CC = $(PREFIX)-gcc -AR = $(PREFIX)-ar +CC = $(PREFIX)gcc +AR = $(PREFIX)ar TGT_CFLAGS = -Os \ -Wall -Wextra -Wimplicit-function-declaration \ -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \ @@ -36,7 +34,11 @@ TGT_CFLAGS = -Os \ TGT_CFLAGS += $(DEBUG_FLAGS) TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = ccm.o uart.o gpio.o iomuxc.o + +OBJS += ccm.o +OBJS += gpio.o +OBJS += iomuxc.o +OBJS += uart.o VPATH += ../cm3 diff --git a/mk/genlink-config.mk b/mk/genlink-config.mk index 6935ec9b..4686fe6d 100644 --- a/mk/genlink-config.mk +++ b/mk/genlink-config.mk @@ -55,17 +55,18 @@ endif # only append to LDFLAGS if the library file exists to not break builds # where those are provided by different means ifneq (,$(wildcard $(OPENCM3_DIR)/lib/libopencm3_$(genlink_family).a)) -LDLIBS += -lopencm3_$(genlink_family) -LIBDEPS += $(OPENCM3_DIR)/lib/libopencm3_$(genlink_family).a +LIBNAME = opencm3_$(genlink_family) else ifneq (,$(wildcard $(OPENCM3_DIR)/lib/libopencm3_$(genlink_subfamily).a)) -LDLIBS += -lopencm3_$(genlink_subfamily) -LIBDEPS += $(OPENCM3_DIR)/lib/libopencm3_$(genlink_subfamily).a +LIBNAME = opencm3_$(genlink_subfamily) else $(warning $(OPENCM3_DIR)/lib/libopencm3_$(genlink_family).a library variant for the selected device does not exist.) endif endif +LDLIBS += -l$(LIBNAME) +LIBDEPS += $(OPENCM3_DIR)/lib/lib$(LIBNAME).a + # only append to LDLIBS if the directory exists ifneq (,$(wildcard $(OPENCM3_DIR)/lib)) LDFLAGS += -L$(OPENCM3_DIR)/lib diff --git a/scripts/gendoxylayout.py b/scripts/gendoxylayout.py new file mode 100755 index 00000000..24154958 --- /dev/null +++ b/scripts/gendoxylayout.py @@ -0,0 +1,68 @@ +#!/usr/bin/env python +# This python program generates parameters for the linker script generator feature. + +# This file is part of the libopencm3 project. +# +# 2019 Guillaume Revaillot <g.revaillot@gmail.com> +# +# This library is free software: you can redistribute it and/or modify +# it under the terms of the GNU Lesser General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public License +# along with this library. If not, see <http://www.gnu.org/licenses/>. + +from xml.etree import ElementTree + +import argparse + + +parser = argparse.ArgumentParser(prog='gendoxylayout') +parser.add_argument("--template", required=True) +parser.add_argument("--out", required=True) +parser.add_argument("--target") +parser.add_argument("devices", nargs='*') +args = parser.parse_args() + +class CommentedTreeBuilder(ElementTree.TreeBuilder): + def __init__(self, *args, **kwargs): + super(CommentedTreeBuilder, self).__init__(*args, **kwargs) + + def comment(self, data): + self.start(ElementTree.Comment, {}) + self.data(data) + self.end(ElementTree.Comment) + +tree = ElementTree.parse(args.template, ElementTree.XMLParser(target=CommentedTreeBuilder())) +parent_map = {c:p for p in tree.iter() for c in p} +for element in tree.iter(tag=ElementTree.Comment): + if ("#devices#" in element.text): + idx = (list(parent_map[element]).index(element)) + for device in args.devices: + tab = ElementTree.Element('tab') + + tab.set("visible", "yes") + tab.set("title", str(device).upper()) + tab.set("intro", "") + + if (args.target != None): + if (device == args.target): + tab.set("type", "modules") + else: + tab.set("type", "user") + tab.set("url", "../../" + device + "/html/modules.html") + else: + tab.set("type", "user") + tab.set("url", "../" + device + "/html/modules.html") + + parent_map[element].insert(idx, tab) + idx = idx+1; + parent_map[element].remove(element) + +tree.write(args.out) diff --git a/scripts/gendoxylist b/scripts/gendoxylist index 6ae5804b..108e2a90 100755 --- a/scripts/gendoxylist +++ b/scripts/gendoxylist @@ -13,7 +13,7 @@ PATH_DELTA=$(realpath --relative-to=${ODIR} ${DDIR}) printf "# This file is autogenerated by scripts/gendoxylist\n" > ${ODIR}/${ONAME} printf "# All headers for core/platform, not always caught by .d file tracking\n" >> ${ODIR}/${ONAME} UNTRACKED_DIRS="../include/libopencm3/cm3 ../include/libopencm3/${IPATH}" -for FN in $(find ${UNTRACKED_DIRS} -name '*.h'); do +for FN in $(find ${UNTRACKED_DIRS} -name '*.h' | sort); do printf "INPUT += ../%s\n" "$FN" >> ${ODIR}/${ONAME} done diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index c36273bf..8a1c355c 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -34,7 +34,7 @@ import json template_nvic_h = '''\ /* This file is part of the libopencm3 project. * - * It was generated by the irq2nvic_h script. + * It was generated by the irq2nvic_h script from {sourcefile} */ #ifndef {includeguard} @@ -42,7 +42,7 @@ template_nvic_h = '''\ #include <libopencm3/cm3/nvic.h> -/** @defgroup CM3_nvic_defines_{partname_doxygen} User interrupts for {partname_humanreadable} +/** @defgroup CM3_nvic_defines_irqs User interrupts for {partname_humanreadable} @ingroup CM3_nvic_defines @{{*/ @@ -125,6 +125,7 @@ def convert(infile, outfile_nvic, outfile_vectornvic, outfile_cmsis): data['isrdecls'] = "\n".join('void %s_isr(void) __attribute__((weak, alias("blocking_handler")));'%name.lower() for name in irqnames) data['vectortableinitialization'] = ', \\\n '.join('[NVIC_%s_IRQ] = %s_isr'%(name.upper(), name.lower()) for name in irqnames) data['cmsisbends'] = "\n".join("#define %s_IRQHandler %s_isr"%(name.upper(), name.lower()) for name in irqnames) + data['sourcefile'] = infile.name outfile_nvic.write(template_nvic_h.format(**data)) outfile_vectornvic.write(template_vector_nvic_c.format(**data)) diff --git a/tests/gadget-zero/Makefile b/tests/gadget-zero/Makefile index 52841cd0..8aa770d8 100644 --- a/tests/gadget-zero/Makefile +++ b/tests/gadget-zero/Makefile @@ -9,7 +9,7 @@ all: $(GZ_ALL:=.all) clean: $(GZ_ALL:=.clean) %.all: - make -f $* all + $(MAKE) -f $* all %.clean: - make -f $* clean + $(MAKE) -f $* clean diff --git a/tests/gadget-zero/main-stm32f429i-disco.c b/tests/gadget-zero/main-stm32f429i-disco.c index 9109d927..7d4fd8f1 100644 --- a/tests/gadget-zero/main-stm32f429i-disco.c +++ b/tests/gadget-zero/main-stm32f429i-disco.c @@ -35,7 +35,7 @@ int main(void) { - rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); + rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); rcc_periph_clock_enable(RCC_GPIOB); rcc_periph_clock_enable(RCC_OTGHS); diff --git a/tests/gadget-zero/main-stm32f4disco.c b/tests/gadget-zero/main-stm32f4disco.c index aea0598c..37f901d4 100644 --- a/tests/gadget-zero/main-stm32f4disco.c +++ b/tests/gadget-zero/main-stm32f4disco.c @@ -35,13 +35,12 @@ int main(void) { - rcc_clock_setup_hse_3v3(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); + rcc_clock_setup_pll(&rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_168MHZ]); rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_OTGFS); - gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, - GPIO9 | GPIO11 | GPIO12); - gpio_set_af(GPIOA, GPIO_AF10, GPIO9 | GPIO11 | GPIO12); + gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO11 | GPIO12); + gpio_set_af(GPIOA, GPIO_AF10, GPIO11 | GPIO12); /* LEDS on discovery board */ rcc_periph_clock_enable(RCC_GPIOD); |