diff options
| author | Karl Palsson <karlp@tweak.net.au> | 2015-10-15 00:52:54 +0300 |
|---|---|---|
| committer | Karl Palsson <karlp@tweak.net.au> | 2015-10-15 01:15:15 +0300 |
| commit | c72f3d588a637101262d5e2b276dc6cc5d926a6d (patch) | |
| tree | 6f2f6633adb0f80080b1a4e43b50dc43bb1cf75a /include/libopencm3/stm32 | |
| parent | c899273c62568fdb00fe54b80eab45c6c0917969 (diff) | |
Surround all macro parameters with ()
All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.
Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.
Fixes github issue #321
Diffstat (limited to 'include/libopencm3/stm32')
25 files changed, 277 insertions, 277 deletions
diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h index 53b0ef54..62db1f36 100644 --- a/include/libopencm3/stm32/can.h +++ b/include/libopencm3/stm32/can.h @@ -54,23 +54,23 @@ LGPL License Terms @ref lgpl_license /* --- CAN registers ------------------------------------------------------- */ /* CAN master control register (CAN_MCR) */ -#define CAN_MCR(can_base) MMIO32(can_base + 0x000) +#define CAN_MCR(can_base) MMIO32((can_base) + 0x000) /* CAN master status register (CAN_MSR) */ -#define CAN_MSR(can_base) MMIO32(can_base + 0x004) +#define CAN_MSR(can_base) MMIO32((can_base) + 0x004) /* CAN transmit status register (CAN_TSR) */ -#define CAN_TSR(can_base) MMIO32(can_base + 0x008) +#define CAN_TSR(can_base) MMIO32((can_base) + 0x008) /* CAN receive FIFO 0 register (CAN_RF0R) */ -#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) +#define CAN_RF0R(can_base) MMIO32((can_base) + 0x00C) /* CAN receive FIFO 1 register (CAN_RF1R) */ -#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) +#define CAN_RF1R(can_base) MMIO32((can_base) + 0x010) /* CAN interrupt enable register (CAN_IER) */ -#define CAN_IER(can_base) MMIO32(can_base + 0x014) +#define CAN_IER(can_base) MMIO32((can_base) + 0x014) /* CAN error status register (CAN_ESR) */ -#define CAN_ESR(can_base) MMIO32(can_base + 0x018) +#define CAN_ESR(can_base) MMIO32((can_base) + 0x018) /* CAN bit timing register (CAN_BTR) */ -#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) +#define CAN_BTR(can_base) MMIO32((can_base) + 0x01C) /* Registers in the offset range 0x020 to 0x17F are reserved. */ @@ -84,71 +84,71 @@ LGPL License Terms @ref lgpl_license #define CAN_FIFO1 0x1C0 /* CAN TX mailbox identifier register (CAN_TIxR) */ -#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) +#define CAN_TIxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x0) #define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) #define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) #define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) /* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ -#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) -#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) -#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) -#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) +#define CAN_TDTxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x4) +#define CAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0) +#define CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1) +#define CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2) /* CAN mailbox data low register (CAN_TDLxR) */ -#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) -#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) -#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) -#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) +#define CAN_TDLxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x8) +#define CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0) +#define CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1) +#define CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2) /* CAN mailbox data high register (CAN_TDHxR) */ -#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) -#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) -#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) -#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) +#define CAN_TDHxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0xC) +#define CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0) +#define CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1) +#define CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2) /* CAN RX FIFO identifier register (CAN_RIxR) */ -#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) -#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) -#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) +#define CAN_RIxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x0) +#define CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0) +#define CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1) /* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ -#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) -#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) -#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) +#define CAN_RDTxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x4) +#define CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0) +#define CAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1) /* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ -#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) -#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) -#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) +#define CAN_RDLxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x8) +#define CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0) +#define CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1) /* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ -#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) -#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) -#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) +#define CAN_RDHxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0xC) +#define CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0) +#define CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1) /* --- CAN filter registers ------------------------------------------------ */ /* CAN filter master register (CAN_FMR) */ -#define CAN_FMR(can_base) MMIO32(can_base + 0x200) +#define CAN_FMR(can_base) MMIO32((can_base) + 0x200) /* CAN filter mode register (CAN_FM1R) */ -#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) +#define CAN_FM1R(can_base) MMIO32((can_base) + 0x204) /* Register offset 0x208 is reserved. */ /* CAN filter scale register (CAN_FS1R) */ -#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) +#define CAN_FS1R(can_base) MMIO32((can_base) + 0x20C) /* Register offset 0x210 is reserved. */ /* CAN filter FIFO assignement register (CAN_FFA1R) */ -#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) +#define CAN_FFA1R(can_base) MMIO32((can_base) + 0x214) /* Register offset 0x218 is reserved. */ /* CAN filter activation register (CAN_FA1R) */ -#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) +#define CAN_FA1R(can_base) MMIO32((can_base) + 0x21C) /* Register offset 0x220 is reserved. */ @@ -159,10 +159,10 @@ LGPL License Terms @ref lgpl_license * Connectivity line devices have 28 banks so the bank ID spans 0..27 * all other devices have 14 banks so the bank ID spans 0..13. */ -#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \ - (bank * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \ - (bank * 0x8) + 0x4) +#define CAN_FiR1(can_base, bank) MMIO32((can_base) + 0x240 + \ + ((bank) * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32((can_base) + 0x240 + \ + ((bank) * 0x8) + 0x4) /* --- CAN_MCR values ------------------------------------------------------ */ diff --git a/include/libopencm3/stm32/common/adc_common_v1.h b/include/libopencm3/stm32/common/adc_common_v1.h index 3ab2dfd8..c8773fe6 100644 --- a/include/libopencm3/stm32/common/adc_common_v1.h +++ b/include/libopencm3/stm32/common/adc_common_v1.h @@ -49,19 +49,19 @@ specific memorymap.h header before including this header file.*/ /* --- ADC registers ------------------------------------------------------- */ /* ADC status register (ADC_SR) */ -#define ADC_SR(block) MMIO32(block + 0x00) +#define ADC_SR(block) MMIO32((block) + 0x00) /* ADC control register 1 (ADC_CR1) */ -#define ADC_CR1(block) MMIO32(block + 0x04) +#define ADC_CR1(block) MMIO32((block) + 0x04) /* ADC control register 2 (ADC_CR2) */ -#define ADC_CR2(block) MMIO32(block + 0x08) +#define ADC_CR2(block) MMIO32((block) + 0x08) /* ADC sample time register 1 (ADC_SMPR1) */ -#define ADC_SMPR1(block) MMIO32(block + 0x0c) +#define ADC_SMPR1(block) MMIO32((block) + 0x0c) /* ADC sample time register 2 (ADC_SMPR2) */ -#define ADC_SMPR2(block) MMIO32(block + 0x10) +#define ADC_SMPR2(block) MMIO32((block) + 0x10) #define ADC1_SR ADC_SR(ADC1) #define ADC1_CR1 ADC_CR1(ADC1) diff --git a/include/libopencm3/stm32/common/dma_common_f24.h b/include/libopencm3/stm32/common/dma_common_f24.h index 922a8b3a..e32114b1 100644 --- a/include/libopencm3/stm32/common/dma_common_f24.h +++ b/include/libopencm3/stm32/common/dma_common_f24.h @@ -60,8 +60,8 @@ specific memorymap.h header before including this header file.*/ /**@}*/ #define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n))) -#define DMA1_STREAM(n) DMA_STREAM(DMA1, n) -#define DMA2_STREAM(n) DMA_STREAM(DMA2, n) +#define DMA1_STREAM(n) DMA_STREAM(DMA1, (n)) +#define DMA2_STREAM(n) DMA_STREAM(DMA2, (n)) #define DMA1_STREAM0 DMA1_STREAM(0) #define DMA1_STREAM1 DMA1_STREAM(1) @@ -84,31 +84,31 @@ specific memorymap.h header before including this header file.*/ /* --- DMA controller registers -------------------------------------------- */ /* DMA low interrupt status register (DMAx_LISR) */ -#define DMA_LISR(port) MMIO32(port + 0x00) +#define DMA_LISR(port) MMIO32((port) + 0x00) #define DMA1_LISR DMA_LISR(DMA1) #define DMA2_LISR DMA_LISR(DMA2) /* DMA high interrupt status register (DMAx_HISR) */ -#define DMA_HISR(port) MMIO32(port + 0x04) +#define DMA_HISR(port) MMIO32((port) + 0x04) #define DMA1_HISR DMA_HISR(DMA1) #define DMA2_HISR DMA_HISR(DMA2) /* DMA low interrupt flag clear register (DMAx_LIFCR) */ -#define DMA_LIFCR(port) MMIO32(port + 0x08) +#define DMA_LIFCR(port) MMIO32((port) + 0x08) #define DMA1_LIFCR DMA_LIFCR(DMA1) #define DMA2_LIFCR DMA_LIFCR(DMA2) /* DMA high interrupt flag clear register (DMAx_HIFCR) */ -#define DMA_HIFCR(port) MMIO32(port + 0x0C) +#define DMA_HIFCR(port) MMIO32((port) + 0x0C) #define DMA1_HIFCR DMA_HIFCR(DMA1) #define DMA2_HIFCR DMA_HIFCR(DMA2) /* --- DMA stream registers ------------------------------------------------ */ /* DMA Stream x configuration register (DMA_SxCR) */ -#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00) -#define DMA1_SCR(n) DMA_SCR(DMA1, n) -#define DMA2_SCR(n) DMA_SCR(DMA2, n) +#define DMA_SCR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x00) +#define DMA1_SCR(n) DMA_SCR(DMA1, (n)) +#define DMA2_SCR(n) DMA_SCR(DMA2, (n)) #define DMA1_S0CR DMA1_SCR(0) #define DMA1_S1CR DMA1_SCR(1) @@ -129,9 +129,9 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7CR DMA2_SCR(7) /* DMA Stream x number of data register (DMA_SxNDTR) */ -#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04) -#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n) -#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n) +#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x04) +#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, (n)) +#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, (n)) #define DMA1_S0NDTR DMA1_SNDTR(0) #define DMA1_S1NDTR DMA1_SNDTR(1) @@ -153,9 +153,9 @@ specific memorymap.h header before including this header file.*/ /* DMA Stream x peripheral address register (DMA_SxPAR) */ #define DMA_SPAR(port, n) (*(volatile void **)\ - (DMA_STREAM(port, n) + 0x08)) -#define DMA1_SPAR(n) DMA_SPAR(DMA1, n) -#define DMA2_SPAR(n) DMA_SPAR(DMA2, n) + (DMA_STREAM((port), (n)) + 0x08)) +#define DMA1_SPAR(n) DMA_SPAR(DMA1, (n)) +#define DMA2_SPAR(n) DMA_SPAR(DMA2, (n)) #define DMA1_S0PAR DMA1_SPAR(0) #define DMA1_S1PAR DMA1_SPAR(1) @@ -177,9 +177,9 @@ specific memorymap.h header before including this header file.*/ /* DMA Stream x memory address 0 register (DMA_SxM0AR) */ #define DMA_SM0AR(port, n) (*(volatile void **) \ - (DMA_STREAM(port, n) + 0x0c)) -#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) -#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) + (DMA_STREAM((port), (n)) + 0x0c)) +#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, (n)) +#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, (n)) #define DMA1_S0M0AR DMA1_SM0AR(0) #define DMA1_S1M0AR DMA1_SM0AR(1) @@ -201,9 +201,9 @@ specific memorymap.h header before including this header file.*/ /* DMA Stream x memory address 1 register (DMA_SxM1AR) */ #define DMA_SM1AR(port, n) (*(volatile void **)\ - (DMA_STREAM(port, n) + 0x10)) -#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) -#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) + (DMA_STREAM((port), (n)) + 0x10)) +#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, (n)) +#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, (n)) #define DMA1_S0M1AR DMA1_SM1AR(0) #define DMA1_S1M1AR DMA1_SM1AR(1) @@ -224,9 +224,9 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7M1AR DMA2_SM1AR(7) /* DMA Stream x FIFO control register (DMA_SxFCR) */ -#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14) -#define DMA1_SFCR(n) DMA_SFCR(DMA1, n) -#define DMA2_SFCR(n) DMA_SFCR(DMA2, n) +#define DMA_SFCR(port, n) MMIO32(DMA_STREAM((port), (n)) + 0x14) +#define DMA1_SFCR(n) DMA_SFCR(DMA1, (n)) +#define DMA2_SFCR(n) DMA_SFCR(DMA2, (n)) #define DMA1_S0FCR DMA1_SFCR(0) #define DMA1_S1FCR DMA1_SFCR(1) @@ -269,7 +269,7 @@ being at the same relative location */ /* Offset within interrupt status register to start of stream interrupt flag * field */ -#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) +#define DMA_ISR_OFFSET(stream) (6*((stream) & 0x01)+16*(((stream) & 0x02) >> 1)) #define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ DMA_FEIF) #define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) @@ -501,7 +501,7 @@ being at the same relative location */ /**@}*/ #define DMA_SxCR_CHSEL_SHIFT 25 #define DMA_SxCR_CHSEL_MASK (7 << 25) -#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL(n) ((n) << DMA_SxCR_CHSEL_SHIFT) /* Reserved [31:28] */ diff --git a/include/libopencm3/stm32/common/dma_common_l1f013.h b/include/libopencm3/stm32/common/dma_common_l1f013.h index cb781a4c..a00834ab 100644 --- a/include/libopencm3/stm32/common/dma_common_l1f013.h +++ b/include/libopencm3/stm32/common/dma_common_l1f013.h @@ -48,17 +48,17 @@ specific memorymap.h header before including this header file.*/ /* --- DMA registers ------------------------------------------------------- */ /* DMA interrupt status register (DMAx_ISR) */ -#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA_ISR(dma_base) MMIO32((dma_base) + 0x00) #define DMA1_ISR DMA_ISR(DMA1) #define DMA2_ISR DMA_ISR(DMA2) /* DMA interrupt flag clear register (DMAx_IFCR) */ -#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA_IFCR(dma_base) MMIO32((dma_base) + 0x04) #define DMA1_IFCR DMA_IFCR(DMA1) #define DMA2_IFCR DMA_IFCR(DMA2) /* DMA channel configuration register (DMAx_CCRy) */ -#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ +#define DMA_CCR(dma_base, channel) MMIO32((dma_base) + 0x08 + \ (0x14 * ((channel) - 1))) #define DMA1_CCR(channel) DMA_CCR(DMA1, channel) @@ -78,7 +78,7 @@ specific memorymap.h header before including this header file.*/ #define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) /* DMA number of data register (DMAx_CNDTRy) */ -#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ +#define DMA_CNDTR(dma_base, channel) MMIO32((dma_base) + 0x0C + \ (0x14 * ((channel) - 1))) #define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) @@ -98,7 +98,7 @@ specific memorymap.h header before including this header file.*/ #define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) /* DMA peripheral address register (DMAx_CPARy) */ -#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ +#define DMA_CPAR(dma_base, channel) MMIO32((dma_base) + 0x10 + \ (0x14 * ((channel) - 1))) #define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) @@ -119,7 +119,7 @@ specific memorymap.h header before including this header file.*/ /* DMA memory address register (DMAx_CMARy) */ -#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ +#define DMA_CMAR(dma_base, channel) MMIO32((dma_base) + 0x14 + \ (0x14 * ((channel) - 1))) #define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) @@ -162,7 +162,7 @@ group. /* Offset within interrupt status register to start of channel interrupt flag * field */ -#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAG_OFFSET(channel) (4*((channel) - 1)) #define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ DMA_GIF) #define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) diff --git a/include/libopencm3/stm32/common/gpio_common_f234.h b/include/libopencm3/stm32/common/gpio_common_f234.h index e574a1b9..5fb03ae8 100644 --- a/include/libopencm3/stm32/common/gpio_common_f234.h +++ b/include/libopencm3/stm32/common/gpio_common_f234.h @@ -57,7 +57,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* Port mode register (GPIOx_MODER) */ -#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIO_MODER(port) MMIO32((port) + 0x00) #define GPIOA_MODER GPIO_MODER(GPIOA) #define GPIOB_MODER GPIO_MODER(GPIOB) #define GPIOC_MODER GPIO_MODER(GPIOC) @@ -66,7 +66,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_MODER GPIO_MODER(GPIOF) /* Port output type register (GPIOx_OTYPER) */ -#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIO_OTYPER(port) MMIO32((port) + 0x04) #define GPIOA_OTYPER GPIO_OTYPER(GPIOA) #define GPIOB_OTYPER GPIO_OTYPER(GPIOB) #define GPIOC_OTYPER GPIO_OTYPER(GPIOC) @@ -75,7 +75,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_OTYPER GPIO_OTYPER(GPIOF) /* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08) #define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) #define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) #define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) @@ -84,7 +84,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIO_PUPDR(port) MMIO32((port) + 0x0c) #define GPIOA_PUPDR GPIO_PUPDR(GPIOA) #define GPIOB_PUPDR GPIO_PUPDR(GPIOB) #define GPIOC_PUPDR GPIO_PUPDR(GPIOC) @@ -93,7 +93,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_PUPDR GPIO_PUPDR(GPIOF) /* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIO_IDR(port) MMIO32((port) + 0x10) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) @@ -102,7 +102,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_IDR GPIO_IDR(GPIOF) /* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIO_ODR(port) MMIO32((port) + 0x14) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) @@ -111,7 +111,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_ODR GPIO_ODR(GPIOF) /* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIO_BSRR(port) MMIO32((port) + 0x18) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) @@ -120,7 +120,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_BSRR GPIO_BSRR(GPIOF) /* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x1c) +#define GPIO_LCKR(port) MMIO32((port) + 0x1c) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) @@ -129,7 +129,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_LCKR GPIO_LCKR(GPIOF) /* Alternate function low register (GPIOx_AFRL) */ -#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIO_AFRL(port) MMIO32((port) + 0x20) #define GPIOA_AFRL GPIO_AFRL(GPIOA) #define GPIOB_AFRL GPIO_AFRL(GPIOB) #define GPIOC_AFRL GPIO_AFRL(GPIOC) @@ -138,7 +138,7 @@ specific memorymap.h header before including this header file.*/ #define GPIOF_AFRL GPIO_AFRL(GPIOF) /* Alternate function high register (GPIOx_AFRH) */ -#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIO_AFRH(port) MMIO32((port) + 0x24) #define GPIOA_AFRH GPIO_AFRH(GPIOA) #define GPIOB_AFRH GPIO_AFRH(GPIOB) #define GPIOC_AFRH GPIO_AFRH(GPIOC) @@ -148,7 +148,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIOx_MODER values -------------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE(n, mode) ((mode) << (2 * (n))) #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode @ingroup gpio_defines @@ -172,7 +172,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIOx_OSPEEDR values ------------------------------------------------ */ -#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED(n, speed) ((speed) << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @@ -185,7 +185,7 @@ specific memorymap.h header before including this header file.*/ /* --- GPIOx_PUPDR values -------------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD(n, pupd) ((pupd) << (2 * (n))) #define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_pup GPIO Output Pin Pullup @ingroup gpio_defines @@ -218,7 +218,7 @@ specific memorymap.h header before including this header file.*/ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See datasheet table 6 (pg. 48) for alternate function mappings. */ -#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR(n, af) ((af) << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) /** @defgroup gpio_af_num Alternate Function Pin Selection @ingroup gpio_defines diff --git a/include/libopencm3/stm32/common/rtc_common_l1f024.h b/include/libopencm3/stm32/common/rtc_common_l1f024.h index 677caf0b..154652e3 100644 --- a/include/libopencm3/stm32/common/rtc_common_l1f024.h +++ b/include/libopencm3/stm32/common/rtc_common_l1f024.h @@ -95,7 +95,7 @@ specific memorymap.h header before including this header file.*/ /* RTC backup registers (RTC_BKPxR) */ #define RTC_BKP_BASE (RTC_BASE + 0x50) -#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg)) +#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4 * (reg))) /* RTC time register (RTC_TR) ----------------------------------- */ diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h index 949fec1d..4e75669a 100644 --- a/include/libopencm3/stm32/common/spi_common_all.h +++ b/include/libopencm3/stm32/common/spi_common_all.h @@ -55,58 +55,58 @@ specific memorymap.h header before including this header file.*/ /* Control register 1 (SPIx_CR1) */ /* Note: Not used in I2S mode. */ -#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI_CR1(spi_base) MMIO32((spi_base) + 0x00) #define SPI1_CR1 SPI_CR1(SPI1_BASE) #define SPI2_CR1 SPI_CR1(SPI2_BASE) #define SPI3_CR1 SPI_CR1(SPI3_BASE) /* Control register 2 (SPIx_CR2) */ -#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI_CR2(spi_base) MMIO32((spi_base) + 0x04) #define SPI1_CR2 SPI_CR2(SPI1_BASE) #define SPI2_CR2 SPI_CR2(SPI2_BASE) #define SPI3_CR2 SPI_CR2(SPI3_BASE) /* Status register (SPIx_SR) */ -#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI_SR(spi_base) MMIO32((spi_base) + 0x08) #define SPI1_SR SPI_SR(SPI1_BASE) #define SPI2_SR SPI_SR(SPI2_BASE) #define SPI3_SR SPI_SR(SPI3_BASE) /* Data register (SPIx_DR) */ -#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI_DR(spi_base) MMIO32((spi_base) + 0x0c) #define SPI1_DR SPI_DR(SPI1_BASE) #define SPI2_DR SPI_DR(SPI2_BASE) #define SPI3_DR SPI_DR(SPI3_BASE) /* CRC polynomial register (SPIx_CRCPR) */ /* Note: Not used in I2S mode. */ -#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI_CRCPR(spi_base) MMIO32((spi_base) + 0x10) #define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) #define SPI2_CRCPR SPI_CRCPR(SPI2_BASE) #define SPI3_CRCPR SPI_CRCPR(SPI3_BASE) /* RX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ -#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI_RXCRCR(spi_base) MMIO32((spi_base) + 0x14) #define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) #define SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE) #define SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE) /* TX CRC register (SPIx_RXCRCR) */ /* Note: Not used in I2S mode. */ -#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI_TXCRCR(spi_base) MMIO32((spi_base) + 0x18) #define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) #define SPI2_TXCRCR SPI_TXCRCR(SPI2_BASE) #define SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE) /* I2S configuration register (SPIx_I2SCFGR) */ -#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI_I2SCFGR(spi_base) MMIO32((spi_base) + 0x1c) #define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) #define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE) #define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE) /* I2S prescaler register (SPIx_I2SPR) */ -#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI_I2SPR(spi_base) MMIO32((spi_base) + 0x20) #define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) #define SPI2_I2SPR SPI_I2SPR(SPI2_BASE) #define SPI3_I2SPR SPI_I2SPR(SPI3_BASE) diff --git a/include/libopencm3/stm32/common/spi_common_f03.h b/include/libopencm3/stm32/common/spi_common_f03.h index f9de9d4f..ac0f27d7 100644 --- a/include/libopencm3/stm32/common/spi_common_f03.h +++ b/include/libopencm3/stm32/common/spi_common_f03.h @@ -37,7 +37,7 @@ * applicable to the STM32F0/F3 series of devices */ -#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) +#define SPI_DR8(spi_base) MMIO8((spi_base) + 0x0c) #define SPI1_DR8 SPI_DR8(SPI1_BASE) #define SPI2_DR8 SPI_DR8(SPI2_BASE) #define SPI3_DR8 SPI_DR8(SPI3_BASE) diff --git a/include/libopencm3/stm32/common/timer_common_all.h b/include/libopencm3/stm32/common/timer_common_all.h index 4e5ee62c..e315afab 100644 --- a/include/libopencm3/stm32/common/timer_common_all.h +++ b/include/libopencm3/stm32/common/timer_common_all.h @@ -86,7 +86,7 @@ specific memorymap.h header before including this header file.*/ /* --- Timer registers ----------------------------------------------------- */ /* Control register 1 (TIMx_CR1) */ -#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM_CR1(tim_base) MMIO32((tim_base) + 0x00) #define TIM1_CR1 TIM_CR1(TIM1) #define TIM2_CR1 TIM_CR1(TIM2) #define TIM3_CR1 TIM_CR1(TIM3) @@ -106,7 +106,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CR1 TIM_CR1(TIM17) /* Control register 2 (TIMx_CR2) */ -#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM_CR2(tim_base) MMIO32((tim_base) + 0x04) #define TIM1_CR2 TIM_CR2(TIM1) #define TIM2_CR2 TIM_CR2(TIM2) #define TIM3_CR2 TIM_CR2(TIM3) @@ -120,7 +120,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CR2 TIM_CR2(TIM17) /* Slave mode control register (TIMx_SMCR) */ -#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM_SMCR(tim_base) MMIO32((tim_base) + 0x08) #define TIM1_SMCR TIM_SMCR(TIM1) #define TIM2_SMCR TIM_SMCR(TIM2) #define TIM3_SMCR TIM_SMCR(TIM3) @@ -132,7 +132,7 @@ specific memorymap.h header before including this header file.*/ #define TIM15_SMCR TIM_SMCR(TIM15) /* DMA/Interrupt enable register (TIMx_DIER) */ -#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM_DIER(tim_base) MMIO32((tim_base) + 0x0C) #define TIM1_DIER TIM_DIER(TIM1) #define TIM2_DIER TIM_DIER(TIM2) #define TIM3_DIER TIM_DIER(TIM3) @@ -152,7 +152,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_DIER TIM_DIER(TIM17) /* Status register (TIMx_SR) */ -#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM_SR(tim_base) MMIO32((tim_base) + 0x10) #define TIM1_SR TIM_SR(TIM1) #define TIM2_SR TIM_SR(TIM2) #define TIM3_SR TIM_SR(TIM3) @@ -172,7 +172,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_SR TIM_SR(TIM17) /* Event generation register (TIMx_EGR) */ -#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM_EGR(tim_base) MMIO32((tim_base) + 0x14) #define TIM1_EGR TIM_EGR(TIM1) #define TIM2_EGR TIM_EGR(TIM2) #define TIM3_EGR TIM_EGR(TIM3) @@ -192,7 +192,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_EGR TIM_EGR(TIM17) /* Capture/compare mode register 1 (TIMx_CCMR1) */ -#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM_CCMR1(tim_base) MMIO32((tim_base) + 0x18) #define TIM1_CCMR1 TIM_CCMR1(TIM1) #define TIM2_CCMR1 TIM_CCMR1(TIM2) #define TIM3_CCMR1 TIM_CCMR1(TIM3) @@ -210,7 +210,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CCMR1 TIM_CCMR1(TIM17) /* Capture/compare mode register 2 (TIMx_CCMR2) */ -#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM_CCMR2(tim_base) MMIO32((tim_base) + 0x1C) #define TIM1_CCMR2 TIM_CCMR2(TIM1) #define TIM2_CCMR2 TIM_CCMR2(TIM2) #define TIM3_CCMR2 TIM_CCMR2(TIM3) @@ -219,7 +219,7 @@ specific memorymap.h header before including this header file.*/ #define TIM8_CCMR2 TIM_CCMR2(TIM8) /* Capture/compare enable register (TIMx_CCER) */ -#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM_CCER(tim_base) MMIO32((tim_base) + 0x20) #define TIM1_CCER TIM_CCER(TIM1) #define TIM2_CCER TIM_CCER(TIM2) #define TIM3_CCER TIM_CCER(TIM3) @@ -237,7 +237,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CCER TIM_CCER(TIM17) /* Counter (TIMx_CNT) */ -#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM_CNT(tim_base) MMIO32((tim_base) + 0x24) #define TIM1_CNT TIM_CNT(TIM1) #define TIM2_CNT TIM_CNT(TIM2) #define TIM3_CNT TIM_CNT(TIM3) @@ -257,7 +257,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CNT TIM_CNT(TIM17) /* Prescaler (TIMx_PSC) */ -#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM_PSC(tim_base) MMIO32((tim_base) + 0x28) #define TIM1_PSC TIM_PSC(TIM1) #define TIM2_PSC TIM_PSC(TIM2) #define TIM3_PSC TIM_PSC(TIM3) @@ -277,7 +277,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_PSC TIM_PSC(TIM17) /* Auto-reload register (TIMx_ARR) */ -#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM_ARR(tim_base) MMIO32((tim_base) + 0x2C) #define TIM1_ARR TIM_ARR(TIM1) #define TIM2_ARR TIM_ARR(TIM2) #define TIM3_ARR TIM_ARR(TIM3) @@ -297,7 +297,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_ARR TIM_ARR(TIM17) /* Repetition counter register (TIMx_RCR) */ -#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM_RCR(tim_base) MMIO32((tim_base) + 0x30) #define TIM1_RCR TIM_RCR(TIM1) #define TIM8_RCR TIM_RCR(TIM8) #define TIM15_RCR TIM_RCR(TIM15) @@ -305,7 +305,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_RCR TIM_RCR(TIM17) /* Capture/compare register 1 (TIMx_CCR1) */ -#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM_CCR1(tim_base) MMIO32((tim_base) + 0x34) #define TIM1_CCR1 TIM_CCR1(TIM1) #define TIM2_CCR1 TIM_CCR1(TIM2) #define TIM3_CCR1 TIM_CCR1(TIM3) @@ -323,7 +323,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_CCR1 TIM_CCR1(TIM17) /* Capture/compare register 2 (TIMx_CCR2) */ -#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM_CCR2(tim_base) MMIO32((tim_base) + 0x38) #define TIM1_CCR2 TIM_CCR2(TIM1) #define TIM2_CCR2 TIM_CCR2(TIM2) #define TIM3_CCR2 TIM_CCR2(TIM3) @@ -335,7 +335,7 @@ specific memorymap.h header before including this header file.*/ #define TIM15_CCR2 TIM_CCR2(TIM15) /* Capture/compare register 3 (TIMx_CCR3) */ -#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM_CCR3(tim_base) MMIO32((tim_base) + 0x3C) #define TIM1_CCR3 TIM_CCR3(TIM1) #define TIM2_CCR3 TIM_CCR3(TIM2) #define TIM3_CCR3 TIM_CCR3(TIM3) @@ -344,7 +344,7 @@ specific memorymap.h header before including this header file.*/ #define TIM8_CCR3 TIM_CCR3(TIM8) /* Capture/compare register 4 (TIMx_CCR4) */ -#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM_CCR4(tim_base) MMIO32((tim_base) + 0x40) #define TIM1_CCR4 TIM_CCR4(TIM1) #define TIM2_CCR4 TIM_CCR4(TIM2) #define TIM3_CCR4 TIM_CCR4(TIM3) @@ -353,7 +353,7 @@ specific memorymap.h header before including this header file.*/ #define TIM8_CCR4 TIM_CCR4(TIM8) /* Break and dead-time register (TIMx_BDTR) */ -#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM_BDTR(tim_base) MMIO32((tim_base) + 0x44) #define TIM1_BDTR TIM_BDTR(TIM1) #define TIM8_BDTR TIM_BDTR(TIM8) #define TIM15_BDTR TIM_BDTR(TIM15) @@ -361,7 +361,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_BDTR TIM_BDTR(TIM17) /* DMA control register (TIMx_DCR) */ -#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM_DCR(tim_base) MMIO32((tim_base) + 0x48) #define TIM1_DCR TIM_DCR(TIM1) #define TIM2_DCR TIM_DCR(TIM2) #define TIM3_DCR TIM_DCR(TIM3) @@ -373,7 +373,7 @@ specific memorymap.h header before including this header file.*/ #define TIM17_DCR TIM_DCR(TIM17) /* DMA address for full transfer (TIMx_DMAR) */ -#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM_DMAR(tim_base) MMIO32((tim_base) + 0x4C) #define TIM1_DMAR TIM_DMAR(TIM1) #define TIM2_DMAR TIM_DMAR(TIM2) #define TIM3_DMAR TIM_DMAR(TIM3) diff --git a/include/libopencm3/stm32/common/timer_common_f24.h b/include/libopencm3/stm32/common/timer_common_f24.h index 67ba593c..6f483d86 100644 --- a/include/libopencm3/stm32/common/timer_common_f24.h +++ b/include/libopencm3/stm32/common/timer_common_f24.h @@ -41,7 +41,7 @@ specific memorymap.h header before including this header file.*/ */ /* Timer 2/5 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM5_OR TIM_OR(TIM5) diff --git a/include/libopencm3/stm32/common/usart_common_f124.h b/include/libopencm3/stm32/common/usart_common_f124.h index 0bb85148..cd6f56ff 100644 --- a/include/libopencm3/stm32/common/usart_common_f124.h +++ b/include/libopencm3/stm32/common/usart_common_f124.h @@ -40,7 +40,7 @@ specific memorymap.h header before including this header file.*/ /* --- USART registers ----------------------------------------------------- */ /* Status register (USARTx_SR) */ -#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART_SR(usart_base) MMIO32((usart_base) + 0x00) #define USART1_SR USART_SR(USART1_BASE) #define USART2_SR USART_SR(USART2_BASE) #define USART3_SR USART_SR(USART3_BASE) @@ -48,7 +48,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_SR USART_SR(UART5_BASE) /* Data register (USARTx_DR) */ -#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART_DR(usart_base) MMIO32((usart_base) + 0x04) #define USART1_DR USART_DR(USART1_BASE) #define USART2_DR USART_DR(USART2_BASE) #define USART3_DR USART_DR(USART3_BASE) @@ -56,7 +56,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_DR USART_DR(UART5_BASE) /* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART_BRR(usart_base) MMIO32((usart_base) + 0x08) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) @@ -64,7 +64,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_BRR USART_BRR(UART5_BASE) /* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART_CR1(usart_base) MMIO32((usart_base) + 0x0c) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) @@ -72,7 +72,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_CR1 USART_CR1(UART5_BASE) /* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART_CR2(usart_base) MMIO32((usart_base) + 0x10) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) @@ -80,7 +80,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_CR2 USART_CR2(UART5_BASE) /* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART_CR3(usart_base) MMIO32((usart_base) + 0x14) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) @@ -88,7 +88,7 @@ specific memorymap.h header before including this header file.*/ #define UART5_CR3 USART_CR3(UART5_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x18) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) diff --git a/include/libopencm3/stm32/f0/gpio.h b/include/libopencm3/stm32/f0/gpio.h index 85633c57..a5a22364 100644 --- a/include/libopencm3/stm32/f0/gpio.h +++ b/include/libopencm3/stm32/f0/gpio.h @@ -41,7 +41,7 @@ /* Register definitions */ /*****************************************************************************/ -#define GPIO_BRR(port) MMIO32(port + 0x28) +#define GPIO_BRR(port) MMIO32((port) + 0x28) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) diff --git a/include/libopencm3/stm32/f0/usart.h b/include/libopencm3/stm32/f0/usart.h index 8dba6833..a8d38985 100644 --- a/include/libopencm3/stm32/f0/usart.h +++ b/include/libopencm3/stm32/f0/usart.h @@ -44,67 +44,67 @@ /* Register definitions */ /*****************************************************************************/ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) #define USART4_CR1 USART_CR1(USART4_BASE) -#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) #define USART4_CR2 USART_CR2(USART4_BASE) -#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) #define USART4_CR3 USART_CR3(USART4_BASE) -#define USART_BRR(usart_base) MMIO32(usart_base + 0x0c) +#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0c) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) #define USART4_BRR USART_BRR(USART4_BASE) -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) #define USART4_GTPR USART_GTPR(USART4_BASE) -#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14) #define USART1_RTOR USART_RTOR(USART1_BASE) #define USART2_RTOR USART_RTOR(USART2_BASE) #define USART3_RTOR USART_RTOR(USART3_BASE) #define USART4_RTOR USART_RTOR(USART4_BASE) -#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18) #define USART1_RQR USART_RQR(USART1_BASE) #define USART2_RQR USART_RQR(USART2_BASE) #define USART3_RQR USART_RQR(USART3_BASE) #define USART4_RQR USART_RQR(USART4_BASE) -#define USART_ISR(usart_base) MMIO32(usart_base + 0x1c) +#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1c) #define USART1_ISR USART_ISR(USART1_BASE) #define USART2_ISR USART_ISR(USART2_BASE) #define USART3_ISR USART_ISR(USART3_BASE) #define USART4_ISR USART_ISR(USART4_BASE) -#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20) #define USART1_ICR USART_ICR(USART1_BASE) #define USART2_ICR USART_ICR(USART2_BASE) #define USART3_ICR USART_ICR(USART3_BASE) #define USART4_ICR USART_ICR(USART4_BASE) -#define USART_RDR(usart_base) MMIO8(usart_base + 0x24) +#define USART_RDR(usart_base) MMIO8((usart_base) + 0x24) #define USART1_RDR USART_RDR(USART1_BASE) #define USART2_RDR USART_RDR(USART2_BASE) #define USART3_RDR USART_RDR(USART3_BASE) #define USART4_RDR USART_RDR(USART4_BASE) -#define USART_TDR(usart_base) MMIO8(usart_base + 0x28) +#define USART_TDR(usart_base) MMIO8((usart_base) + 0x28) #define USART1_TDR USART_TDR(USART1_BASE) #define USART2_TDR USART_TDR(USART2_BASE) #define USART3_TDR USART_TDR(USART3_BASE) diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index ec7cabc0..d52a02c1 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -43,37 +43,37 @@ LGPL License Terms @ref lgpl_license /* --- Convenience macros -------------------------------------------------- */ /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x14) -#define ADC_JOFR2(block) MMIO32(block + 0x18) -#define ADC_JOFR3(block) MMIO32(block + 0x1c) -#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC_JOFR1(block) MMIO32((block) + 0x14) +#define ADC_JOFR2(block) MMIO32((block) + 0x18) +#define ADC_JOFR3(block) MMIO32((block) + 0x1c) +#define ADC_JOFR4(block) MMIO32((block) + 0x20) /* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC_HTR(block) MMIO32((block) + 0x24) /* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC_LTR(block) MMIO32((block) + 0x28) /* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC_SQR1(block) MMIO32((block) + 0x2c) /* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC_SQR2(block) MMIO32((block) + 0x30) /* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC_SQR3(block) MMIO32((block) + 0x34) /* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC_JSQR(block) MMIO32((block) + 0x38) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x3c) -#define ADC_JDR2(block) MMIO32(block + 0x40) -#define ADC_JDR3(block) MMIO32(block + 0x44) -#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC_JDR1(block) MMIO32((block) + 0x3c) +#define ADC_JDR2(block) MMIO32((block) + 0x40) +#define ADC_JDR3(block) MMIO32((block) + 0x44) +#define ADC_JDR4(block) MMIO32((block) + 0x48) /* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC_DR(block) MMIO32((block) + 0x4c) /* --- ADC Channels ------------------------------------------------------- */ #define ADC_CHANNEL_TEMP ADC_CHANNEL16 diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h index d520b216..2de19ce9 100644 --- a/include/libopencm3/stm32/f1/gpio.h +++ b/include/libopencm3/stm32/f1/gpio.h @@ -523,7 +523,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ /* Port configuration register low (GPIOx_CRL) */ -#define GPIO_CRL(port) MMIO32(port + 0x00) +#define GPIO_CRL(port) MMIO32((port) + 0x00) #define GPIOA_CRL GPIO_CRL(GPIOA) #define GPIOB_CRL GPIO_CRL(GPIOB) #define GPIOC_CRL GPIO_CRL(GPIOC) @@ -533,7 +533,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_CRL GPIO_CRL(GPIOG) /* Port configuration register low (GPIOx_CRH) */ -#define GPIO_CRH(port) MMIO32(port + 0x04) +#define GPIO_CRH(port) MMIO32((port) + 0x04) #define GPIOA_CRH GPIO_CRH(GPIOA) #define GPIOB_CRH GPIO_CRH(GPIOB) #define GPIOC_CRH GPIO_CRH(GPIOC) @@ -543,7 +543,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_CRH GPIO_CRH(GPIOG) /* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x08) +#define GPIO_IDR(port) MMIO32((port) + 0x08) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) @@ -553,7 +553,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_IDR GPIO_IDR(GPIOG) /* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x0c) +#define GPIO_ODR(port) MMIO32((port) + 0x0c) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) @@ -563,7 +563,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_ODR GPIO_ODR(GPIOG) /* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x10) +#define GPIO_BSRR(port) MMIO32((port) + 0x10) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) @@ -573,7 +573,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_BSRR GPIO_BSRR(GPIOG) /* Port bit reset register (GPIOx_BRR) */ -#define GPIO_BRR(port) MMIO16(port + 0x14) +#define GPIO_BRR(port) MMIO16((port) + 0x14) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) @@ -583,7 +583,7 @@ LGPL License Terms @ref lgpl_license #define GPIOG_BRR GPIO_BRR(GPIOG) /* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x18) +#define GPIO_LCKR(port) MMIO32((port) + 0x18) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index 56c97480..beb4bc4e 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -45,7 +45,7 @@ /*----------- ADC registers -------------------------------------- */ /* ADC interrupt and status register (ADCx_ISR, x=1..4) */ -#define ADC_ISR(adc_base) MMIO32(adc_base + 0x00) +#define ADC_ISR(adc_base) MMIO32((adc_base) + 0x00) #define ADC1_ISR ADC_ISR(ADC1_BASE) #define ADC2_ISR ADC_ISR(ADC2_BASE) #define ADC3_ISR ADC_ISR(ADC3_BASE) @@ -53,7 +53,7 @@ /* Interrupt Enable Register (ADCx_IER, x=1..4) IER */ -#define ADC_IER(adc_base) MMIO32(adc_base + 0x04) +#define ADC_IER(adc_base) MMIO32((adc_base) + 0x04) #define ADC1_IER ADC_IER(ADC1_BASE) #define ADC2_IER ADC_IER(ADC2_BASE) #define ADC3_IER ADC_IER(ADC3_BASE) @@ -61,7 +61,7 @@ /* Control Register (ADCx_CR, x=1..4) CR */ -#define ADC_CR(adc_base) MMIO32(adc_base + 0x08) +#define ADC_CR(adc_base) MMIO32((adc_base) + 0x08) #define ADC1_CR ADC_CR(ADC1_BASE) #define ADC2_CR ADC_CR(ADC2_BASE) #define ADC3_CR ADC_CR(ADC3_BASE) @@ -69,7 +69,7 @@ /* Configuration Register (ADCx_CFGR, x=1..4) CFGR */ -#define ADC_CFGR(adc_base) MMIO32(adc_base + 0x0C) +#define ADC_CFGR(adc_base) MMIO32((adc_base) + 0x0C) #define ADC1_CFGR ADC_CFGR(ADC1_BASE) #define ADC2_CFGR ADC_CFGR(ADC2_BASE) #define ADC3_CFGR ADC_CFGR(ADC3_BASE) @@ -77,7 +77,7 @@ /* Sample Time Register 1 (ADCx_SMPR1, x=1..4) SMPR1 */ -#define ADC_SMPR1(adc_base) MMIO32(adc_base + 0x14) +#define ADC_SMPR1(adc_base) MMIO32((adc_base) + 0x14) #define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) #define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) #define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) @@ -85,7 +85,7 @@ /* Sample Time Register 2 (ADCx_SMPR2, x=1..4) SMPR2 */ -#define ADC_SMPR2(adc_base) MMIO32(adc_base + 0x18) +#define ADC_SMPR2(adc_base) MMIO32((adc_base) + 0x18) #define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) #define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) #define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) @@ -93,7 +93,7 @@ /* Watchdog Threshold Register 1 (ADCx_TR1, x=1..4) TR1 */ -#define ADC_TR1(adc_base) MMIO32(adc_base + 0x20) +#define ADC_TR1(adc_base) MMIO32((adc_base) + 0x20) #define ADC1_TR1 ADC_TR1(ADC1_BASE) #define ADC2_TR1 ADC_TR1(ADC2_BASE) #define ADC3_TR1 ADC_TR1(ADC3_BASE) @@ -101,7 +101,7 @@ /* Watchdog Threshold Register 2 (ADCx_TR2, x=1..4) TR2 */ -#define ADC_TR2(adc_base) MMIO32(adc_base + 0x24) +#define ADC_TR2(adc_base) MMIO32((adc_base) + 0x24) #define ADC1_TR2 ADC_TR2(ADC1_BASE) #define ADC2_TR2 ADC_TR2(ADC2_BASE) #define ADC3_TR2 ADC_TR2(ADC3_BASE) @@ -109,7 +109,7 @@ /* Watchdog Threshold Register 3 (ADCx_TR3, x=1..4) TR3 */ -#define ADC_TR3(adc_base) MMIO32(adc_base + 0x28) +#define ADC_TR3(adc_base) MMIO32((adc_base) + 0x28) #define ADC1_TR3 ADC_TR3(ADC1_BASE) #define ADC2_TR3 ADC_TR3(ADC2_BASE) #define ADC3_TR3 ADC_TR3(ADC3_BASE) @@ -117,7 +117,7 @@ /* Regular Sequence Register 1 (ADCx_SQR1, x=1..4) SQR1 */ -#define ADC_SQR1(adc_base) MMIO32(adc_base + 0x30) +#define ADC_SQR1(adc_base) MMIO32((adc_base) + 0x30) #define ADC1_SQR1 ADC_SQR1(ADC1_BASE) #define ADC2_SQR1 ADC_SQR1(ADC2_BASE) #define ADC3_SQR1 ADC_SQR1(ADC3_BASE) @@ -125,7 +125,7 @@ /* Regular Sequence Register 2 (ADCx_SQR2, x=1..4) SQR2 */ -#define ADC_SQR2(adc_base) MMIO32(adc_base + 0x34) +#define ADC_SQR2(adc_base) MMIO32((adc_base) + 0x34) #define ADC1_SQR2 ADC_SQR2(ADC1_BASE) #define ADC2_SQR2 ADC_SQR2(ADC2_BASE) #define ADC3_SQR2 ADC_SQR2(ADC3_BASE) @@ -133,7 +133,7 @@ /* Regular Sequence Register 3 (ADCx_SQR3, x=1..4) SQR3 */ -#define ADC_SQR3(adc_base) MMIO32(adc_base + 0x38) +#define ADC_SQR3(adc_base) MMIO32((adc_base) + 0x38) #define ADC1_SQR3 ADC_SQR3(ADC1_BASE) #define ADC2_SQR3 ADC_SQR3(ADC2_BASE) #define ADC3_SQR3 ADC_SQR3(ADC3_BASE) @@ -141,7 +141,7 @@ /* Regular Sequence Register 4 (ADCx_SQR3, x=1..4) SQR4 */ -#define ADC_SQR4(adc_base) MMIO32(adc_base + 0x3C) +#define ADC_SQR4(adc_base) MMIO32((adc_base) + 0x3C) #define ADC1_SQR4 ADC_SQR4(ADC1_BASE) #define ADC2_SQR4 ADC_SQR4(ADC2_BASE) #define ADC3_SQR4 ADC_SQR4(ADC3_BASE) @@ -149,7 +149,7 @@ /* regular Data Register (ADCx_DR, x=1..4) DR */ -#define ADC_DR(adc_base) MMIO32(adc_base + 0x40) +#define ADC_DR(adc_base) MMIO32((adc_base) + 0x40) #define ADC1_DR ADC_DR(ADC1_BASE) #define ADC2_DR ADC_DR(ADC2_BASE) #define ADC3_DR ADC_DR(ADC3_BASE) @@ -157,7 +157,7 @@ /* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ -#define ADC_JSQR(adc_base) MMIO32(adc_base + 0x30) +#define ADC_JSQR(adc_base) MMIO32((adc_base) + 0x30) #define ADC1_JSQR ADC_JSQR(ADC1_BASE) #define ADC2_JSQR ADC_JSQR(ADC2_BASE) #define ADC3_JSQR ADC_JSQR(ADC3_BASE) @@ -165,25 +165,25 @@ /* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ -#define ADC_OFR1(adc_base) MMIO32(adc_base + 0x60) +#define ADC_OFR1(adc_base) MMIO32((adc_base) + 0x60) #define ADC1_OFR1 ADC_OFR1(ADC1_BASE) #define ADC2_OFR1 ADC_OFR1(ADC2_BASE) #define ADC3_OFR1 ADC_OFR1(ADC3_BASE) #define ADC4_OFR1 ADC_OFR1(ADC4_BASE) -#define ADC_OFR2(adc_base) MMIO32(adc_base + 0x64) +#define ADC_OFR2(adc_base) MMIO32((adc_base) + 0x64) #define ADC1_OFR2 ADC_OFR2(ADC1_BASE) #define ADC2_OFR2 ADC_OFR2(ADC2_BASE) #define ADC3_OFR2 ADC_OFR2(ADC3_BASE) #define ADC4_OFR2 ADC_OFR2(ADC4_BASE) -#define ADC_OFR3(adc_base) MMIO32(adc_base + 0x68) +#define ADC_OFR3(adc_base) MMIO32((adc_base) + 0x68) #define ADC1_OFR3 ADC_OFR3(ADC1_BASE) #define ADC2_OFR3 ADC_OFR3(ADC2_BASE) #define ADC3_OFR3 ADC_OFR3(ADC3_BASE) #define ADC4_OFR3 ADC_OFR3(ADC4_BASE) -#define ADC_OFR4(adc_base) MMIO32(adc_base + 0x6C) +#define ADC_OFR4(adc_base) MMIO32((adc_base) + 0x6C) #define ADC1_OFR4 ADC_OFR4(ADC1_BASE) #define ADC2_OFR4 ADC_OFR4(ADC2_BASE) #define ADC3_OFR4 ADC_OFR4(ADC3_BASE) @@ -191,25 +191,25 @@ /* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ -#define ADC_JDR1(adc_base) MMIO32(adc_base + 0x80) +#define ADC_JDR1(adc_base) MMIO32((adc_base) + 0x80) #define ADC1_JDR1 ADC_JDR1(ADC1_BASE) #define ADC2_JDR1 ADC_JDR1(ADC2_BASE) #define ADC3_JDR1 ADC_JDR1(ADC3_BASE) #define ADC4_JDR1 ADC_JDR1(ADC4_BASE) -#define ADC_JDR2(adc_base) MMIO32(adc_base + 0x84) +#define ADC_JDR2(adc_base) MMIO32((adc_base) + 0x84) #define ADC1_JDR2 ADC_JDR2(ADC1_BASE) #define ADC2_JDR2 ADC_JDR2(ADC2_BASE) #define ADC3_JDR2 ADC_JDR2(ADC3_BASE) #define ADC4_JDR2 ADC_JDR2(ADC4_BASE) -#define ADC_JDR3(adc_base) MMIO32(adc_base + 0x88) +#define ADC_JDR3(adc_base) MMIO32((adc_base) + 0x88) #define ADC1_JDR3 ADC_JDR3(ADC1_BASE) #define ADC2_JDR3 ADC_JDR3(ADC2_BASE) #define ADC3_JDR3 ADC_JDR3(ADC3_BASE) #define ADC4_JDR3 ADC_JDR3(ADC4_BASE) -#define ADC_JDR4(adc_base) MMIO32(adc_base + 0x8C) +#define ADC_JDR4(adc_base) MMIO32((adc_base) + 0x8C) #define ADC1_JDR4 ADC_JDR4(ADC1_BASE) #define ADC2_JDR4 ADC_JDR4(ADC2_BASE) #define ADC3_JDR4 ADC_JDR4(ADC3_BASE) @@ -217,7 +217,7 @@ /* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ -#define ADC_AWD2CR(adc_base) MMIO32(adc_base + 0xA0) +#define ADC_AWD2CR(adc_base) MMIO32((adc_base) + 0xA0) #define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) #define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) #define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) @@ -225,7 +225,7 @@ /* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ -#define ADC_AWD3CR(adc_base) MMIO32(adc_base + 0xA4) +#define ADC_AWD3CR(adc_base) MMIO32((adc_base) + 0xA4) #define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) #define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) #define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) @@ -233,7 +233,7 @@ /* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ -#define ADC_DIFSEL(adc_base) MMIO32(adc_base + 0xB0) +#define ADC_DIFSEL(adc_base) MMIO32((adc_base) + 0xB0) #define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) #define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) #define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) @@ -241,7 +241,7 @@ /* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ -#define ADC_CALFACT(adc_base) MMIO32(adc_base + 0xB4) +#define ADC_CALFACT(adc_base) MMIO32((adc_base) + 0xB4) #define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) #define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) #define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) diff --git a/include/libopencm3/stm32/f3/usart.h b/include/libopencm3/stm32/f3/usart.h index 86195634..e429ddc8 100644 --- a/include/libopencm3/stm32/f3/usart.h +++ b/include/libopencm3/stm32/f3/usart.h @@ -36,7 +36,7 @@ /* --- USART registers ----------------------------------------------------- */ /* Control register 1 (USARTx_CR1) */ -#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART_CR1(usart_base) MMIO32((usart_base) + 0x00) #define USART1_CR1 USART_CR1(USART1_BASE) #define USART2_CR1 USART_CR1(USART2_BASE) #define USART3_CR1 USART_CR1(USART3_BASE) @@ -44,7 +44,7 @@ #define UART5_CR1 USART_CR1(UART5_BASE) /* Control register 2 (USARTx_CR2) */ -#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART_CR2(usart_base) MMIO32((usart_base) + 0x04) #define USART1_CR2 USART_CR2(USART1_BASE) #define USART2_CR2 USART_CR2(USART2_BASE) #define USART3_CR2 USART_CR2(USART3_BASE) @@ -52,7 +52,7 @@ #define UART5_CR2 USART_CR2(UART5_BASE) /* Control register 3 (USARTx_CR3) */ -#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART_CR3(usart_base) MMIO32((usart_base) + 0x08) #define USART1_CR3 USART_CR3(USART1_BASE) #define USART2_CR3 USART_CR3(USART2_BASE) #define USART3_CR3 USART_CR3(USART3_BASE) @@ -60,7 +60,7 @@ #define UART5_CR3 USART_CR3(UART5_BASE) /* Baud rate register (USARTx_BRR) */ -#define USART_BRR(usart_base) MMIO32(usart_base + 0x0C) +#define USART_BRR(usart_base) MMIO32((usart_base) + 0x0C) #define USART1_BRR USART_BRR(USART1_BASE) #define USART2_BRR USART_BRR(USART2_BASE) #define USART3_BRR USART_BRR(USART3_BASE) @@ -68,7 +68,7 @@ #define UART5_BRR USART_BRR(UART5_BASE) /* Guard time and prescaler register (USARTx_GTPR) */ -#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART_GTPR(usart_base) MMIO32((usart_base) + 0x10) #define USART1_GTPR USART_GTPR(USART1_BASE) #define USART2_GTPR USART_GTPR(USART2_BASE) #define USART3_GTPR USART_GTPR(USART3_BASE) @@ -76,7 +76,7 @@ #define UART5_GTPR USART_GTPR(UART5_BASE) /* Receiver timeout register (USART_RTOR) */ -#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART_RTOR(usart_base) MMIO32((usart_base) + 0x14) #define USART1_RTOR USART_RTOR(USART1_BASE) #define USART2_RTOR USART_RTOR(USART2_BASE) #define USART3_RTOR USART_RTOR(USART3_BASE) @@ -84,7 +84,7 @@ #define UART5_RTOR USART_RTOR(UART5_BASE) /* Request register (USART_RQR) */ -#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART_RQR(usart_base) MMIO32((usart_base) + 0x18) #define USART1_RQR USART_RQR(USART1_BASE) #define USART2_RQR USART_RQR(USART2_BASE) #define USART3_RQR USART_RQR(USART3_BASE) @@ -92,7 +92,7 @@ #define UART5_RQR USART_RQR(UART5_BASE) /* Interrupt & status register (USART_ISR) */ -#define USART_ISR(usart_base) MMIO32(usart_base + 0x1C) +#define USART_ISR(usart_base) MMIO32((usart_base) + 0x1C) #define USART1_ISR USART_ISR(USART1_BASE) #define USART2_ISR USART_ISR(USART2_BASE) #define USART3_ISR USART_ISR(USART3_BASE) @@ -100,7 +100,7 @@ #define UART5_ISR USART_ISR(UART5_BASE) /* Interrupt flag clear register (USART_ICR) */ -#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART_ICR(usart_base) MMIO32((usart_base) + 0x20) #define USART1_ICR USART_ICR(USART1_BASE) #define USART2_ICR USART_ICR(USART2_BASE) #define USART3_ICR USART_ICR(USART3_BASE) @@ -108,7 +108,7 @@ #define UART5_ICR USART_ICR(UART5_BASE) /* Receive data register (USART_RDR) */ -#define USART_RDR(usart_base) MMIO32(usart_base + 0x24) +#define USART_RDR(usart_base) MMIO32((usart_base) + 0x24) #define USART1_RDR USART_RDR(USART1_BASE) #define USART2_RDR USART_RDR(USART2_BASE) #define USART3_RDR USART_RDR(USART3_BASE) @@ -116,7 +116,7 @@ #define UART5_RDR USART_RDR(UART5_BASE) /* Transmit data register (USART_TDR) */ -#define USART_TDR(usart_base) MMIO32(usart_base + 0x28) +#define USART_TDR(usart_base) MMIO32((usart_base) + 0x28) #define USART1_TDR USART_TDR(USART1_BASE) #define USART2_TDR USART_TDR(USART2_BASE) #define USART3_TDR USART_TDR(USART3_BASE) diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h index 56188f40..07addb52 100644 --- a/include/libopencm3/stm32/f4/adc.h +++ b/include/libopencm3/stm32/f4/adc.h @@ -44,37 +44,37 @@ LGPL License Terms @ref lgpl_license /* --- Convenience macros -------------------------------------------------- */ /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x14) -#define ADC_JOFR2(block) MMIO32(block + 0x18) -#define ADC_JOFR3(block) MMIO32(block + 0x1c) -#define ADC_JOFR4(block) MMIO32(block + 0x20) +#define ADC_JOFR1(block) MMIO32((block) + 0x14) +#define ADC_JOFR2(block) MMIO32((block) + 0x18) +#define ADC_JOFR3(block) MMIO32((block) + 0x1c) +#define ADC_JOFR4(block) MMIO32((block) + 0x20) /* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x24) +#define ADC_HTR(block) MMIO32((block) + 0x24) /* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x28) +#define ADC_LTR(block) MMIO32((block) + 0x28) /* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x2c) +#define ADC_SQR1(block) MMIO32((block) + 0x2c) /* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x30) +#define ADC_SQR2(block) MMIO32((block) + 0x30) /* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x34) +#define ADC_SQR3(block) MMIO32((block) + 0x34) /* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x38) +#define ADC_JSQR(block) MMIO32((block) + 0x38) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x3c) -#define ADC_JDR2(block) MMIO32(block + 0x40) -#define ADC_JDR3(block) MMIO32(block + 0x44) -#define ADC_JDR4(block) MMIO32(block + 0x48) +#define ADC_JDR1(block) MMIO32((block) + 0x3c) +#define ADC_JDR2(block) MMIO32((block) + 0x40) +#define ADC_JDR3(block) MMIO32((block) + 0x44) +#define ADC_JDR4(block) MMIO32((block) + 0x48) /* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x4c) +#define ADC_DR(block) MMIO32((block) + 0x4c) /* ADC common (shared) registers */ #define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) diff --git a/include/libopencm3/stm32/f4/fmc.h b/include/libopencm3/stm32/f4/fmc.h index 9367273c..8aa8c633 100644 --- a/include/libopencm3/stm32/f4/fmc.h +++ b/include/libopencm3/stm32/f4/fmc.h @@ -34,13 +34,13 @@ error "This file should not be included directly, it is included with fsmc.h" /* --- FMC registers ------------------------------------------------------ */ /* SDRAM Control Registers 1 .. 2 */ -#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * x) +#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x)) #define FMC_SDCR1 FMC_SDCR(0) #define FMC_SDCR2 FMC_SDCR(1) /* SDRAM Timing Registers 1 .. 2 */ -#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * x) +#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x)) #define FMC_SDTR1 FMC_SDTR(0) #define FMC_SDTR2 FMC_SDTR(1) diff --git a/include/libopencm3/stm32/f4/ltdc.h b/include/libopencm3/stm32/f4/ltdc.h index 6f5b3afe..adf54d01 100644 --- a/include/libopencm3/stm32/f4/ltdc.h +++ b/include/libopencm3/stm32/f4/ltdc.h @@ -45,51 +45,51 @@ #define LTDC_CDSR (MMIO32(LTDC_BASE + 0x48)) /* x == LTDC_LAYER_x */ -#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * (x - 1))) +#define LTDC_LxCR(x) (MMIO32(LTDC_BASE + 0x84 + 0x80 * ((x) - 1))) #define LTDC_L1CR LTDC_LxCR(LTDC_LAYER_1) #define LTDC_L2CR LTDC_LxCR(LTDC_LAYER_2) -#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * (x - 1))) +#define LTDC_LxWHPCR(x) (MMIO32(LTDC_BASE + 0x88 + 0x80 * ((x) - 1))) #define LTDC_L1WHPCR LTDC_LxWHPCR(LTDC_LAYER_1) #define LTDC_L2WHPCR LTDC_LxWHPCR(LTDC_LAYER_2) -#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * (x - 1))) +#define LTDC_LxWVPCR(x) (MMIO32(LTDC_BASE + 0x8C + 0x80 * ((x) - 1))) #define LTDC_L1WVPCR LTDC_LxWVPCR(LTDC_LAYER_1) #define LTDC_L2WVPCR LTDC_LxWVPCR(LTDC_LAYER_2) -#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * (x - 1))) +#define LTDC_LxCKCR(x) (MMIO32(LTDC_BASE + 0x90 + 0x80 * ((x) - 1))) #define LTDC_L1CKCR LTDC_LxCKCR(LTDC_LAYER_1) #define LTDC_L2CKCR LTDC_LxCKCR(LTDC_LAYER_2) -#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * (x - 1))) +#define LTDC_LxPFCR(x) (MMIO32(LTDC_BASE + 0x94 + 0x80 * ((x) - 1))) #define LTDC_L1PFCR LTDC_LxPFCR(LTDC_LAYER_1) #define LTDC_L2PFCR LTDC_LxPFCR(LTDC_LAYER_2) -#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * (x - 1))) +#define LTDC_LxCACR(x) (MMIO32(LTDC_BASE + 0x98 + 0x80 * ((x) - 1))) #define LTDC_L1CACR LTDC_LxCACR(LTDC_LAYER_1) #define LTDC_L2CACR LTDC_LxCACR(LTDC_LAYER_2) -#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * (x - 1))) +#define LTDC_LxDCCR(x) (MMIO32(LTDC_BASE + 0x9C + 0x80 * ((x) - 1))) #define LTDC_L1DCCR LTDC_LxDCCR(LTDC_LAYER_1) #define LTDC_L2DCCR LTDC_LxDCCR(LTDC_LAYER_2) -#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * (x - 1))) +#define LTDC_LxBFCR(x) (MMIO32(LTDC_BASE + 0xA0 + 0x80 * ((x) - 1))) #define LTDC_L1BFCR LTDC_LxBFCR(LTDC_LAYER_1) #define LTDC_L2BFCR LTDC_LxBFCR(LTDC_LAYER_2) -#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * (x - 1))) +#define LTDC_LxCFBAR(x) (MMIO32(LTDC_BASE + 0xAC + 0x80 * ((x) - 1))) #define LTDC_L1CFBAR LTDC_LxCFBAR(LTDC_LAYER_1) #define LTDC_L2CFBAR LTDC_LxCFBAR(LTDC_LAYER_2) -#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * (x - 1))) +#define LTDC_LxCFBLR(x) (MMIO32(LTDC_BASE + 0xB0 + 0x80 * ((x) - 1))) #define LTDC_L1CFBLR LTDC_LxCFBLR(LTDC_LAYER_1) #define LTDC_L2CFBLR LTDC_LxCFBLR(LTDC_LAYER_2) -#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * (x - 1))) +#define LTDC_LxCFBLNR(x) (MMIO32(LTDC_BASE + 0xB4 + 0x80 * ((x) - 1))) #define LTDC_L1CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_1) #define LTDC_L2CFBLNR LTDC_LxCFBLNR(LTDC_LAYER_2) -#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * (x - 1))) +#define LTDC_LxCLUTWR(x) (MMIO32(LTDC_BASE + 0xC4 + 0x80 * ((x) - 1))) #define LTDC_L1CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_1) #define LTDC_L2CLUTWR LTDC_LxCLUTWR(LTDC_LAYER_2) diff --git a/include/libopencm3/stm32/fsmc.h b/include/libopencm3/stm32/fsmc.h index 818251cb..2d8ed6a7 100644 --- a/include/libopencm3/stm32/fsmc.h +++ b/include/libopencm3/stm32/fsmc.h @@ -37,46 +37,46 @@ /* --- FSMC registers ------------------------------------------------------ */ /* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ -#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * (x)) #define FSMC_BCR1 FSMC_BCR(0) #define FSMC_BCR2 FSMC_BCR(1) #define FSMC_BCR3 FSMC_BCR(2) #define FSMC_BCR4 FSMC_BCR(3) /* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ -#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * (x)) #define FSMC_BTR1 FSMC_BTR(0) #define FSMC_BTR2 FSMC_BTR(1) #define FSMC_BTR3 FSMC_BTR(2) #define FSMC_BTR4 FSMC_BTR(3) /* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ -#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * (x)) #define FSMC_BWTR1 FSMC_BWTR(0) #define FSMC_BWTR2 FSMC_BWTR(1) #define FSMC_BWTR3 FSMC_BWTR(2) #define FSMC_BWTR4 FSMC_BWTR(3) /* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ -#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * (x)) #define FSMC_PCR2 FSMC_PCR(1) #define FSMC_PCR3 FSMC_PCR(2) #define FSMC_PCR4 FSMC_PCR(3) /* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ -#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * (x)) #define FSMC_SR2 FSMC_SR(1) #define FSMC_SR3 FSMC_SR(2) #define FSMC_SR4 FSMC_SR(3) /* Common memory space timing registers 2..4 (FSMC_PMEMx) */ -#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * (x)) #define FSMC_PMEM2 FSMC_PMEM(1) #define FSMC_PMEM3 FSMC_PMEM(2) #define FSMC_PMEM4 FSMC_PMEM(3) /* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ -#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * (x)) #define FSMC_PATT2 FSMC_PATT(1) #define FSMC_PATT3 FSMC_PATT(2) #define FSMC_PATT4 FSMC_PATT(3) @@ -85,7 +85,7 @@ #define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) /* ECC result registers 2/3 (FSMC_ECCRx) */ -#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * (x)) #define FSMC_ECCR2 FSMC_ECCR(1) #define FSMC_ECCR3 FSMC_ECCR(2) diff --git a/include/libopencm3/stm32/l0/gpio.h b/include/libopencm3/stm32/l0/gpio.h index 4292ec81..a1b48990 100644 --- a/include/libopencm3/stm32/l0/gpio.h +++ b/include/libopencm3/stm32/l0/gpio.h @@ -41,7 +41,7 @@ /* Register definitions */ /*****************************************************************************/ -#define GPIO_BRR(port) MMIO32(port + 0x28) +#define GPIO_BRR(port) MMIO32((port) + 0x28) #define GPIOA_BRR GPIO_BRR(GPIOA) #define GPIOB_BRR GPIO_BRR(GPIOB) #define GPIOC_BRR GPIO_BRR(GPIOC) diff --git a/include/libopencm3/stm32/l1/adc.h b/include/libopencm3/stm32/l1/adc.h index cd56d15a..a5f4909c 100644 --- a/include/libopencm3/stm32/l1/adc.h +++ b/include/libopencm3/stm32/l1/adc.h @@ -40,52 +40,52 @@ LGPL License Terms @ref lgpl_license #define ADC_MAX_CHANNELS 32 /* ADC sample time register 3 (ADC_SMPR3) */ -#define ADC_SMPR3(block) MMIO32(block + 0x14) +#define ADC_SMPR3(block) MMIO32((block) + 0x14) #define ADC1_SMPR3 ADC_SMPR3(ADC1) /* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ -#define ADC_JOFR1(block) MMIO32(block + 0x18) -#define ADC_JOFR2(block) MMIO32(block + 0x1c) -#define ADC_JOFR3(block) MMIO32(block + 0x20) -#define ADC_JOFR4(block) MMIO32(block + 0x24) +#define ADC_JOFR1(block) MMIO32((block) + 0x18) +#define ADC_JOFR2(block) MMIO32((block) + 0x1c) +#define ADC_JOFR3(block) MMIO32((block) + 0x20) +#define ADC_JOFR4(block) MMIO32((block) + 0x24) /* ADC watchdog high threshold register (ADC_HTR) */ -#define ADC_HTR(block) MMIO32(block + 0x28) +#define ADC_HTR(block) MMIO32((block) + 0x28) /* ADC watchdog low threshold register (ADC_LTR) */ -#define ADC_LTR(block) MMIO32(block + 0x2c) +#define ADC_LTR(block) MMIO32((block) + 0x2c) /* ADC regular sequence register 1 (ADC_SQR1) */ -#define ADC_SQR1(block) MMIO32(block + 0x30) +#define ADC_SQR1(block) MMIO32((block) + 0x30) /* ADC regular sequence register 2 (ADC_SQR2) */ -#define ADC_SQR2(block) MMIO32(block + 0x34) +#define ADC_SQR2(block) MMIO32((block) + 0x34) /* ADC regular sequence register 3 (ADC_SQR3) */ -#define ADC_SQR3(block) MMIO32(block + 0x38) +#define ADC_SQR3(block) MMIO32((block) + 0x38) /* ADC regular sequence register 4 (ADC_SQR4) */ -#define ADC_SQR4(block) MMIO32(block + 0x3c) +#define ADC_SQR4(block) MMIO32((block) + 0x3c) #define ADC1_SQR4 ADC_SQR4(ADC1) /* ADC regular sequence register 5 (ADC_SQR5) */ -#define ADC_SQR5(block) MMIO32(block + 0x40) +#define ADC_SQR5(block) MMIO32((block) + 0x40) #define ADC1_SQR5 ADC_SQR5(ADC1) /* ADC injected sequence register (ADC_JSQR) */ -#define ADC_JSQR(block) MMIO32(block + 0x44) +#define ADC_JSQR(block) MMIO32((block) + 0x44) /* ADC injected data register x (ADC_JDRx) (x=1..4) */ -#define ADC_JDR1(block) MMIO32(block + 0x48) -#define ADC_JDR2(block) MMIO32(block + 0x4c) -#define ADC_JDR3(block) MMIO32(block + 0x50) -#define ADC_JDR4(block) MMIO32(block + 0x54) +#define ADC_JDR1(block) MMIO32((block) + 0x48) +#define ADC_JDR2(block) MMIO32((block) + 0x4c) +#define ADC_JDR3(block) MMIO32((block) + 0x50) +#define ADC_JDR4(block) MMIO32((block) + 0x54) /* ADC regular data register (ADC_DR) */ -#define ADC_DR(block) MMIO32(block + 0x58) +#define ADC_DR(block) MMIO32((block) + 0x58) /* ADC sample time register 0 (ADC_SMPR0) (high/med+ only) */ -#define ADC_SMPR0(block) MMIO32(block + 0x5c) +#define ADC_SMPR0(block) MMIO32((block) + 0x5c) #define ADC1_SMPR0 ADC_SMPR0(ADC1) #define ADC_CSR MMIO32(ADC1 + 0x300) diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h index f2c607ce..c2970e2a 100644 --- a/include/libopencm3/stm32/l1/gpio.h +++ b/include/libopencm3/stm32/l1/gpio.h @@ -57,7 +57,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ /* Port mode register (GPIOx_MODER) */ -#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIO_MODER(port) MMIO32((port) + 0x00) #define GPIOA_MODER GPIO_MODER(GPIOA) #define GPIOB_MODER GPIO_MODER(GPIOB) #define GPIOC_MODER GPIO_MODER(GPIOC) @@ -66,7 +66,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_MODER GPIO_MODER(GPIOH) /* Port output type register (GPIOx_OTYPER) */ -#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIO_OTYPER(port) MMIO32((port) + 0x04) #define GPIOA_OTYPER GPIO_OTYPER(GPIOA) #define GPIOB_OTYPER GPIO_OTYPER(GPIOB) #define GPIOC_OTYPER GPIO_OTYPER(GPIOC) @@ -75,7 +75,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_OTYPER GPIO_OTYPER(GPIOH) /* Port output speed register (GPIOx_OSPEEDR) */ -#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIO_OSPEEDR(port) MMIO32((port) + 0x08) #define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) #define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) #define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) @@ -84,7 +84,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) /* Port pull-up/pull-down register (GPIOx_PUPDR) */ -#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIO_PUPDR(port) MMIO32((port) + 0x0c) #define GPIOA_PUPDR GPIO_PUPDR(GPIOA) #define GPIOB_PUPDR GPIO_PUPDR(GPIOB) #define GPIOC_PUPDR GPIO_PUPDR(GPIOC) @@ -93,7 +93,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_PUPDR GPIO_PUPDR(GPIOH) /* Port input data register (GPIOx_IDR) */ -#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIO_IDR(port) MMIO32((port) + 0x10) #define GPIOA_IDR GPIO_IDR(GPIOA) #define GPIOB_IDR GPIO_IDR(GPIOB) #define GPIOC_IDR GPIO_IDR(GPIOC) @@ -102,7 +102,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_IDR GPIO_IDR(GPIOH) /* Port output data register (GPIOx_ODR) */ -#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIO_ODR(port) MMIO32((port) + 0x14) #define GPIOA_ODR GPIO_ODR(GPIOA) #define GPIOB_ODR GPIO_ODR(GPIOB) #define GPIOC_ODR GPIO_ODR(GPIOC) @@ -111,7 +111,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_ODR GPIO_ODR(GPIOH) /* Port bit set/reset register (GPIOx_BSRR) */ -#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIO_BSRR(port) MMIO32((port) + 0x18) #define GPIOA_BSRR GPIO_BSRR(GPIOA) #define GPIOB_BSRR GPIO_BSRR(GPIOB) #define GPIOC_BSRR GPIO_BSRR(GPIOC) @@ -120,7 +120,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_BSRR GPIO_BSRR(GPIOH) /* Port configuration lock register (GPIOx_LCKR) */ -#define GPIO_LCKR(port) MMIO32(port + 0x1C) +#define GPIO_LCKR(port) MMIO32((port) + 0x1C) #define GPIOA_LCKR GPIO_LCKR(GPIOA) #define GPIOB_LCKR GPIO_LCKR(GPIOB) #define GPIOC_LCKR GPIO_LCKR(GPIOC) @@ -129,7 +129,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_LCKR GPIO_LCKR(GPIOH) /* Alternate function low register (GPIOx_AFRL) */ -#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIO_AFRL(port) MMIO32((port) + 0x20) #define GPIOA_AFRL GPIO_AFRL(GPIOA) #define GPIOB_AFRL GPIO_AFRL(GPIOB) #define GPIOC_AFRL GPIO_AFRL(GPIOC) @@ -138,7 +138,7 @@ LGPL License Terms @ref lgpl_license #define GPIOH_AFRL GPIO_AFRL(GPIOH) /* Alternate function high register (GPIOx_AFRH) */ -#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIO_AFRH(port) MMIO32((port) + 0x24) #define GPIOA_AFRH GPIO_AFRH(GPIOA) #define GPIOB_AFRH GPIO_AFRH(GPIOB) #define GPIOC_AFRH GPIO_AFRH(GPIOC) @@ -148,7 +148,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIOx_MODER values-------------------------------------------- */ -#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE(n, mode) ((mode) << (2 * (n))) #define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode @ingroup gpio_defines @@ -171,7 +171,7 @@ LGPL License Terms @ref lgpl_license /**@}*/ /* Output speed values */ -#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED(n, speed) ((speed) << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed @ingroup gpio_defines @@ -184,7 +184,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIOx_PUPDR values ------------------------------------------- */ -#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD(n, pupd) ((pupd) << (2 * (n))) #define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_pup GPIO Output Pin Pullup @ingroup gpio_defines @@ -217,7 +217,7 @@ LGPL License Terms @ref lgpl_license /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* See datasheet table 5, page 35 for the definitions */ -#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR(n, af) ((af) << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) /** @defgroup gpio_af_num Alternate Function Pin Selection @ingroup gpio_defines diff --git a/include/libopencm3/stm32/l1/timer.h b/include/libopencm3/stm32/l1/timer.h index fbe1504d..f2e3cd6d 100644 --- a/include/libopencm3/stm32/l1/timer.h +++ b/include/libopencm3/stm32/l1/timer.h @@ -43,7 +43,7 @@ LGPL License Terms @ref lgpl_license */ /* Timer 2/3 option register (TIMx_OR) */ -#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM_OR(tim_base) MMIO32((tim_base) + 0x50) #define TIM2_OR TIM_OR(TIM2) #define TIM3_OR TIM_OR(TIM3) |