Merge remote-tracking branch 'origin/master' into master-gitlab

158 files changed, 4233 insertions, 1876 deletions

diff --git a/lib/cm3/dwt.c b/lib/cm3/dwt.c
index b4408b0c..91a67029 100644
--- a/lib/cm3/dwt.c
+++ b/lib/cm3/dwt.c
@@ -1,3 +1,29 @@
+/** @defgroup CM3_dwt_file DWT
+ *
+ * @ingroup CM3_files
+ *
+ * @brief <b>libopencm3 Cortex-M Data Watchpoint and Trace unit</b>
+ *
+ * The DWT provides
+ * * Comparators, that support
+ *   * watch points
+ *   * data tracing
+ *   * signalling to ETM
+ *   * PC value tracing
+ *   * cycle count matching
+ * * extra PC sampling
+ *   * Sampling as a result of a clock count
+ *   * external access for sampling
+ * * exception trace
+ * * performance profiling counters.
+ *
+ * Which of these features are available is unfortunately implementation defined.
+ *
+ * @see ARMv7m Architecture Reference Manual (Chapter ARMv7-M Debug)
+ *
+ * LGPL License Terms @ref lgpl_license
+ * @{
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -75,3 +101,5 @@ uint32_t dwt_read_cycle_counter(void)
 	}
 #endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c
index 6c2188a8..7b20941f 100644
--- a/lib/cm3/nvic.c
+++ b/lib/cm3/nvic.c
@@ -51,7 +51,7 @@
  *
  * Enables a user interrupt.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  */
 
 void nvic_enable_irq(uint8_t irqn)
@@ -64,7 +64,7 @@ void nvic_enable_irq(uint8_t irqn)
  *
  * Disables a user interrupt.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  */
 
 void nvic_disable_irq(uint8_t irqn)
@@ -77,7 +77,7 @@ void nvic_disable_irq(uint8_t irqn)
  *
  * True if the interrupt has occurred and is waiting for service.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  * @return Boolean. Interrupt pending.
  */
 
@@ -92,7 +92,7 @@ uint8_t nvic_get_pending_irq(uint8_t irqn)
  * Force a user interrupt to a pending state. This has no effect if the
  * interrupt is already pending.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  */
 
 void nvic_set_pending_irq(uint8_t irqn)
@@ -106,7 +106,7 @@ void nvic_set_pending_irq(uint8_t irqn)
  * Force remove a user interrupt from a pending state. This has no effect if
  * the interrupt is actively being serviced.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  */
 
 void nvic_clear_pending_irq(uint8_t irqn)
@@ -119,7 +119,7 @@ void nvic_clear_pending_irq(uint8_t irqn)
 /*---------------------------------------------------------------------------*/
 /** @brief NVIC Return Enabled Interrupt
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  * @return Boolean. Interrupt enabled.
  */
 
@@ -144,7 +144,7 @@ uint8_t nvic_get_irq_enabled(uint8_t irqn)
  * There are 4 priority levels only, given by the upper two bits of the
  * priority byte, as required by ARM standards. No grouping available.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  * @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of
  * 16)
  */
@@ -170,7 +170,7 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority)
  *
  * Interrupt has occurred and is currently being serviced.
  *
- * @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint
+ * @param[in] irqn Unsigned int8. Interrupt number @ref CM3_nvic_defines_irqs
  * @return Boolean. Interrupt active.
  */
 
diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c
index 8c5a2f3a..52f38e81 100644
--- a/lib/cm3/scb.c
+++ b/lib/cm3/scb.c
@@ -1,3 +1,23 @@
+/** @defgroup CM3_scb_file SCB
+ *
+ * @ingroup CM3_files
+ *
+ * @brief <b>libopencm3 Cortex-M System Control Block</b>
+ *
+ * The System Control Block (SCB) is a section of the System Control Space
+ * which provides status information and control features for the processor core.
+ * It allows, amongst other:
+ * * software reset control
+ * * exception management and grouping
+ * * fault information
+ * * power management
+ * * debug status information
+ *
+ * @see ARMv7m Architecture Reference Manual (Chapter B3.2.1 About the SCB)
+ *
+ * LGPL License Terms @ref lgpl_license
+ * @{
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -45,3 +65,5 @@ void scb_set_priority_grouping(uint32_t prigroup)
 	SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
 }
 #endif
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c
index a99593b6..d775dd06 100644
--- a/lib/cm3/systick.c
+++ b/lib/cm3/systick.c
@@ -48,7 +48,7 @@
  *
  * @note The systick counter value might be undefined upon startup. To get
  * predictable behavior, it is a good idea to set or clear the counter after
- * set reload. @seealso systick_clear
+ * set reload. @sa systick_clear
  *
  * @param[in] value uint32_t. 24 bit reload value.
  */
diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c
index 3c12350d..0d4dd519 100644
--- a/lib/dispatch/vector_nvic.c
+++ b/lib/dispatch/vector_nvic.c
@@ -16,6 +16,11 @@
 #	include "../stm32/l1/vector_nvic.c"
 #elif defined(STM32L4)
 #	include "../stm32/l4/vector_nvic.c"
+#elif defined(STM32G0)
+#	include "../stm32/g0/vector_nvic.c"
+
+#elif defined(GD32F1X0)
+#	include "../gd32/f1x0/vector_nvic.c"
 
 #elif defined(EFM32TG)
 #	include "../efm32/tg/vector_nvic.c"
@@ -66,6 +71,9 @@
 #elif defined(MSP432E4)
 #       include "../msp432/e4/vector_nvic.c"
 
+#elif defined(SWM050)
+#       include "../swm050/vector_nvic.c"
+
 #else
 #	warning "no interrupts defined for chipset;"\
 	"not allocating space in the vector table"
diff --git a/lib/efm32/common/acmp_common.c b/lib/efm32/common/acmp_common.c
new file mode 100644
index 00000000..1095d673
--- /dev/null
+++ b/lib/efm32/common/acmp_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup acmp_file ACMP peripheral API
+ * @ingroup peripheral_apis
+ * @brief Analog Comparator helper functions.
+ * 
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/acmp.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/adc_common.c b/lib/efm32/common/adc_common.c
index 980c7151..4c7a1481 100644
--- a/lib/efm32/common/adc_common.c
+++ b/lib/efm32/common/adc_common.c
@@ -1,3 +1,6 @@
+/** @addtogroup adc_file ADC peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -19,6 +22,8 @@
 
 #include <libopencm3/efm32/adc.h>
 
+/**@{*/
+
 /**
  * Set ADC over sampling
  * @param[in] adc ADC (use ADCx)
@@ -633,6 +638,7 @@ uint32_t adc_scan_data_peak(uint32_t adc)
 /**
  * Set ADC scan gain calibration
  * @param[in] adc ADC (use ADCx)
+ * @param scan_gain calibration of gain for internal ref
  */
 void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain)
 {
@@ -642,6 +648,7 @@ void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain)
 /**
  * Set ADC scan offset calibration
  * @param[in] adc ADC (use ADCx)
+ * @param scan_offset calibration of offset for internal ref
  */
 void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset)
 {
@@ -651,6 +658,7 @@ void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset)
 /**
  * Set ADC single gain calibration
  * @param[in] adc ADC (use ADCx)
+ * @param single_gain calibration of gain for internal ref
  */
 void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain)
 {
@@ -660,8 +668,11 @@ void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain)
 /**
  * Set ADC single offset calibration
  * @param[in] adc ADC (use ADCx)
+ * @param single_offset calibration of offset for internal ref
  */
 void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset)
 {
 	ADC_CAL(adc) = (ADC_CAL(adc) & ADC_CAL_SINGLEOFF_MASK) | single_offset;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/burtc_common.c b/lib/efm32/common/burtc_common.c
new file mode 100644
index 00000000..e909f8cd
--- /dev/null
+++ b/lib/efm32/common/burtc_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup burtc_file BURTC peripheral API
+ * @ingroup peripheral_apis
+ * @brief Backup RTC helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/burtc.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/cmu_common.c b/lib/efm32/common/cmu_common.c
index 6edc42dd..8a577516 100644
--- a/lib/efm32/common/cmu_common.c
+++ b/lib/efm32/common/cmu_common.c
@@ -1,3 +1,6 @@
+/** @addtogroup cmu_file CMU peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -20,6 +23,8 @@
 #include <libopencm3/efm32/cmu.h>
 #include <libopencm3/efm32/msc.h>
 
+/**@{*/
+
 /**
  * Enable CMU registers lock.
  */
@@ -54,7 +59,7 @@ bool cmu_get_lock_flag(void)
  *
  * Enable the clock on particular peripheral.
  *
- * @param[in] periph enum cmu_periph_clken Peripheral Name
+ * @param[in] clken Peripheral Name
  *
  * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
  * example)
@@ -69,7 +74,7 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken)
  * @brief Disable Peripheral Clock in running mode.
  * Disable the clock on particular peripheral.
  *
- * @param[in] periph enum cmu_periph_clken Peripheral Name
+ * @param[in] clken Peripheral Name
  *
  * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
  * example)
@@ -270,3 +275,5 @@ void cmu_clock_setup_in_hfxo_out_48mhz(void)
 	/* wait till HFXO not selected */
 	while (cmu_get_hfclk_source() != HFXO);
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/dac_common.c b/lib/efm32/common/dac_common.c
index 8a211afc..4d982401 100644
--- a/lib/efm32/common/dac_common.c
+++ b/lib/efm32/common/dac_common.c
@@ -1,3 +1,6 @@
+/** @addtogroup dac_file DAC peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -22,6 +25,8 @@
 
 #include <libopencm3/efm32/dac.h>
 
+/**@{*/
+
 /**
  * Set DAC refresh cycle
  * @param[in] dac DAC (use DACx)
@@ -95,8 +100,8 @@ void dac_disable_sine(uint32_t dac)
 /**
  * Set PRS trigger source on DAC channel
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
- * @param[in] prs_ch PRS Channel (use PRS_CHx)
+ * @param[in] dac_chan DAC Channel (use DAC_CHx)
+ * @param[in] prs_chan PRS Channel (use PRS_CHx)
  */
 void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan,
 			 enum prs_ch prs_chan)
@@ -110,7 +115,7 @@ void dac_set_prs_trigger(uint32_t dac, enum dac_ch dac_chan,
 /**
  * Enable PRS triggerring
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
+ * @param[in] ch DAC Channel (use DAC_CHx)
  */
 void dac_enable_prs_trigger(uint32_t dac, enum dac_ch ch)
 {
@@ -120,7 +125,7 @@ void dac_enable_prs_trigger(uint32_t dac, enum dac_ch ch)
 /**
  * Disable PRS triggerring
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
+ * @param[in] ch DAC Channel (use DAC_CHx)
  */
 void dac_disable_prs_trigger(uint32_t dac, enum dac_ch ch)
 {
@@ -130,7 +135,7 @@ void dac_disable_prs_trigger(uint32_t dac, enum dac_ch ch)
 /**
  * Enable auto refresh
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
+ * @param[in] ch DAC Channel (use DAC_CHx)
  */
 void dac_enable_auto_refresh(uint32_t dac, enum dac_ch ch)
 {
@@ -140,7 +145,7 @@ void dac_enable_auto_refresh(uint32_t dac, enum dac_ch ch)
 /**
  * Disable auto refresh
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
+ * @param[in] ch DAC Channel (use DAC_CHx)
  */
 void dac_disable_auto_refresh(uint32_t dac, enum dac_ch ch)
 {
@@ -150,7 +155,7 @@ void dac_disable_auto_refresh(uint32_t dac, enum dac_ch ch)
 /**
  * Enable channel
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
+ * @param[in] ch DAC Channel (use DAC_CHx)
  */
 void dac_enable_channel(uint32_t dac, enum dac_ch ch)
 {
@@ -160,9 +165,11 @@ void dac_enable_channel(uint32_t dac, enum dac_ch ch)
 /**
  * Disable channel
  * @param[in] dac DAC (use DACx)
- * @param[in] dac_ch DAC Channel (use DAC_CHx)
+ * @param[in] ch DAC Channel (use DAC_CHx)
  */
 void dac_disable_channel(uint32_t dac, enum dac_ch ch)
 {
 	DAC_CHx_CTRL(dac, ch) &= ~DAC_CH_CTRL_REFREN;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/dma_common.c b/lib/efm32/common/dma_common.c
index e6967bfe..e6a18ced 100644
--- a/lib/efm32/common/dma_common.c
+++ b/lib/efm32/common/dma_common.c
@@ -1,3 +1,6 @@
+/** @addtogroup dma_file DMA peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -19,6 +22,8 @@
 
 #include <libopencm3/efm32/dma.h>
 
+/**@{*/
+
 #define CHANNEL_SUPPORT_LOOP(ch) (((ch) == DMA_CH0) || ((ch) == DMA_CH1))
 
 /**
@@ -563,8 +568,8 @@ static inline uint32_t dma_calc_end_from_start(uint32_t start, uint8_t inc,
  *            descriptor
  * @param[in] ch Channel (use DMA_CHx)
  * @param[in] src_start Source data start address
- * @param[in] this function use dma_desc_set_count() and dma_desc_set_src_inc()
- *            set value to calculate the src data end address from @a src_start
+ * this function uses @ref dma_calc_end_from_start to calculate the
+ * src data end address from @a src_start
  * @note dma_desc_set_count() should be called first.
  * @note dma_desc_set_src_inc() should be called first.
  */
@@ -586,9 +591,8 @@ void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch,
  *            descriptor
  * @param[in] ch Channel (use DMA_CHx)
  * @param[in] dest_start Destination data start address
- * @param[in] this function use dma_desc_set_count() and
- *            dma_desc_set_dest_inc() set value to calculate the dest data end
- *            address from @a dest_start
+ * this function uses @ref dma_calc_end_from_start to calculate the
+ * dest data end address from @a dest_start
  * @note dma_desc_set_count() should be called first.
  * @note dma_desc_set_dest_inc() should be called first.
  */
@@ -619,3 +623,5 @@ void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode)
 	cfg |= DMA_DESC_CH_CFG_CYCLE_CTRL(mode);
 	DMA_DESC_CHx_CFG(desc_base, ch) = cfg;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/emu_common.c b/lib/efm32/common/emu_common.c
new file mode 100644
index 00000000..1015e8e0
--- /dev/null
+++ b/lib/efm32/common/emu_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup emu_file EMU peripheral API
+ * @ingroup peripheral_apis
+ * @brief Energy Management Unit helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/emu.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/gpio_common.c b/lib/efm32/common/gpio_common.c
index 23574228..0c768ca4 100644
--- a/lib/efm32/common/gpio_common.c
+++ b/lib/efm32/common/gpio_common.c
@@ -1,3 +1,6 @@
+/** @addtogroup gpio_file GPIO peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -19,6 +22,8 @@
 
 #include <libopencm3/efm32/gpio.h>
 
+/**@{*/
+
 /**
  * Enable GPIO registers lock.
  * @see gpio_disable_lock()
@@ -173,3 +178,5 @@ void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios)
 {
 	GPIO_P_PINLOCKN(gpio_port) = ~gpios;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/i2c_common.c b/lib/efm32/common/i2c_common.c
new file mode 100644
index 00000000..304f12e6
--- /dev/null
+++ b/lib/efm32/common/i2c_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup i2c_file I2C peripheral API
+ * @ingroup peripheral_apis
+ * @brief I²C helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/i2c.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/letimer_common.c b/lib/efm32/common/letimer_common.c
new file mode 100644
index 00000000..7c1ba9cb
--- /dev/null
+++ b/lib/efm32/common/letimer_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup letimer_file LETIMER peripheral API
+ * @ingroup peripheral_apis
+ * @brief Low Energy Timer helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/letimer.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/msc_common.c b/lib/efm32/common/msc_common.c
new file mode 100644
index 00000000..a542898d
--- /dev/null
+++ b/lib/efm32/common/msc_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup msc_file MSC peripheral API
+ * @ingroup peripheral_apis
+ * @brief Memory Systems Controller helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/msc.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/prs_common.c b/lib/efm32/common/prs_common.c
index bcd47f7f..877c5c07 100644
--- a/lib/efm32/common/prs_common.c
+++ b/lib/efm32/common/prs_common.c
@@ -1,3 +1,10 @@
+/** @addtogroup prs_file PRS peripheral API
+ * @ingroup peripheral_apis
+ * @brief EFM32 Peripheral Reflex System (PRS).
+ * The Peripheral Reflex System (PRS) system is a network which allows the
+ * different peripheral modules to communicate directly with each other
+ * without involving the CPU.
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -19,6 +26,8 @@
 
 #include <libopencm3/efm32/prs.h>
 
+/**@{*/
+
 /**
  * Enable PRS output to GPIO.
  * @param[in] ch Channel (use PRS_CHx)
@@ -138,3 +147,5 @@ void prs_set_signal(enum prs_ch ch, uint32_t signal)
 	PRS_CHx_CTRL(ch) = (PRS_CHx_CTRL(ch) & ~PRS_CH_CTRL_SIGSEL_MASK)
 			   | signal;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/rmu_common.c b/lib/efm32/common/rmu_common.c
new file mode 100644
index 00000000..1b0a8cfd
--- /dev/null
+++ b/lib/efm32/common/rmu_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup rmu_file RMU peripheral API
+ * @ingroup peripheral_apis
+ * @brief Reset Management Unit helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/rmu.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/rtc_common.c b/lib/efm32/common/rtc_common.c
new file mode 100644
index 00000000..b7898ae6
--- /dev/null
+++ b/lib/efm32/common/rtc_common.c
@@ -0,0 +1,16 @@
+/** @addtogroup rtc_file RTC peripheral API
+ * @ingroup peripheral_apis
+ * @brief Real Time Clock helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @sa rtc_defines
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/rtc.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/timer_common.c b/lib/efm32/common/timer_common.c
index 22664954..8f82fcfe 100644
--- a/lib/efm32/common/timer_common.c
+++ b/lib/efm32/common/timer_common.c
@@ -1,3 +1,6 @@
+/** @addtogroup timer_file TIMER peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -19,6 +22,8 @@
 
 #include <libopencm3/efm32/timer.h>
 
+/**@{*/
+
 #define HAS_DEAD_TIME_INSERTION(timer) (timer == TIMER0)
 
 /**
@@ -60,3 +65,5 @@ void timer_set_top(uint32_t timer, uint32_t top)
 {
 	TIMER_TOP(timer) = top;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/common/usart_common.c b/lib/efm32/common/usart_common.c
new file mode 100644
index 00000000..ef49f42c
--- /dev/null
+++ b/lib/efm32/common/usart_common.c
@@ -0,0 +1,18 @@
+/** @addtogroup usart_file UART/USART peripheral API
+ * @ingroup peripheral_apis
+ * @brief UART/USART helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @sa usart_defines
+ * @sa uart_defines
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/uart.h>
+#include <libopencm3/efm32/usart.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/common/wdog_common.c b/lib/efm32/common/wdog_common.c
new file mode 100644
index 00000000..a926ab92
--- /dev/null
+++ b/lib/efm32/common/wdog_common.c
@@ -0,0 +1,15 @@
+/** @addtogroup wdog_file WDOG peripheral API
+ * @ingroup peripheral_apis
+ * @brief Watchdog Module helper functions.
+ *
+ * <b>NO</b> helper functions exist. Only header definitions are available.
+ * Delete these lines if/when you add actual helper APIs.
+ * @copyright See @ref lgpl_license
+ */
+
+#include <libopencm3/efm32/wdog.h>
+
+/**@{*/
+
+/**@}*/
+
diff --git a/lib/efm32/ezr32wg/Makefile b/lib/efm32/ezr32wg/Makefile
index 70b1a252..28026b8c 100644
--- a/lib/efm32/ezr32wg/Makefile
+++ b/lib/efm32/ezr32wg/Makefile
@@ -24,10 +24,8 @@ SRCLIBDIR	?= ../..
 FAMILY		= EZR32WG
 
 FP_FLAGS        ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -38,14 +36,27 @@ TGT_CFLAGS	= -Os \
 TGT_CFLAGS      += $(DEBUG_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		=
 
-OBJS		= gpio_common.o cmu_common.o prs_common.o
-OBJS		+= adc_common.o dma_common.o timer_common.o
-OBJS		+= dac_common.o
+OBJS += acmp_common.o
+OBJS += adc_common.o
+OBJS += burtc_common.o
+OBJS += cmu_common.o
+OBJS += dac_common.o
+OBJS += dma_common.o
+OBJS += emu_common.o
+OBJS += gpio_common.o
+OBJS += i2c_common.o
+OBJS += letimer_common.o
+OBJS += msc_common.o
+OBJS += prs_common.o
+OBJS += rmu_common.o
+OBJS += rtc_common.o
+OBJS += timer_common.o
+OBJS += usart_common.o
+OBJS += wdog_common.o
 
-OBJS            += usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS            += usb_efm32.o
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += usb_efm32.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/efm32/g/Makefile b/lib/efm32/g/Makefile
index 1aace7c6..f1f3568b 100644
--- a/lib/efm32/g/Makefile
+++ b/lib/efm32/g/Makefile
@@ -22,10 +22,8 @@ LIBNAME		= libopencm3_efm32g
 SRCLIBDIR	?= ../..
 FAMILY		= EFM32G
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
diff --git a/lib/efm32/gg/Makefile b/lib/efm32/gg/Makefile
index a96b3df8..231cec2c 100644
--- a/lib/efm32/gg/Makefile
+++ b/lib/efm32/gg/Makefile
@@ -22,10 +22,8 @@ LIBNAME		= libopencm3_efm32gg
 SRCLIBDIR	?= ../..
 FAMILY		= EFM32GG
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
diff --git a/lib/efm32/hg/Makefile b/lib/efm32/hg/Makefile
index f5b897d8..c6f7ba5a 100644
--- a/lib/efm32/hg/Makefile
+++ b/lib/efm32/hg/Makefile
@@ -24,10 +24,8 @@ LIBNAME		= libopencm3_efm32hg
 SRCLIBDIR	?= ../..
 FAMILY		= EFM32HG
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -40,9 +38,12 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 
 ARFLAGS		= rcs
 
-OBJS		= cmu.o gpio_common.o timer_common.o
-OBJS		+= usb.o usb_control.o usb_standard.o usb_msc.o \
-		   usb_dwc_common.o usb_efm32hg.o
+OBJS += cmu.o
+OBJS += gpio_common.o
+OBJS += timer_common.o
+
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += usb_dwc_common.o usb_efm32hg.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/efm32/hg/cmu.c b/lib/efm32/hg/cmu.c
index db28680d..3d678eeb 100644
--- a/lib/efm32/hg/cmu.c
+++ b/lib/efm32/hg/cmu.c
@@ -1,3 +1,6 @@
+/** @addtogroup cmu_file CMU peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -20,6 +23,8 @@
 
 #include <libopencm3/efm32/cmu.h>
 
+/**@{*/
+
 /**
  * Enable CMU registers lock.
  */
@@ -54,7 +59,7 @@ bool cmu_get_lock_flag(void)
  *
  * Enable the clock on particular peripheral.
  *
- * @param[in] periph enum cmu_periph_clken Peripheral Name
+ * @param[in] clken Peripheral Name
  *
  * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
  * example)
@@ -69,7 +74,7 @@ void cmu_periph_clock_enable(enum cmu_periph_clken clken)
  * @brief Disable Peripheral Clock in running mode.
  * Disable the clock on particular peripheral.
  *
- * @param[in] periph enum cmu_periph_clken Peripheral Name
+ * @param[in] clken Peripheral Name
  *
  * For available constants, see @a enum::cmu_periph_clken (CMU_LEUART1 for
  * example)
@@ -105,6 +110,9 @@ void cmu_osc_on(enum cmu_osc osc)
 	case AUXHFRCO:
 		CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCOEN;
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 }
 
@@ -133,6 +141,9 @@ void cmu_osc_off(enum cmu_osc osc)
 	case AUXHFRCO:
 		CMU_OSCENCMD = CMU_OSCENCMD_AUXHFRCODIS;
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 }
 
@@ -163,6 +174,9 @@ bool cmu_osc_ready_flag(enum cmu_osc osc)
 	case AUXHFRCO:
 		return (CMU_STATUS & CMU_STATUS_AUXHFRCORDY) != 0;
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 
 	return false;
@@ -193,6 +207,9 @@ void cmu_wait_for_osc_ready(enum cmu_osc osc)
 	case AUXHFRCO:
 		while ((CMU_STATUS & CMU_STATUS_AUXHFRCORDY) == 0);
 		break;
+	default:
+		/* not applicable */
+		break;
 	}
 }
 
@@ -218,6 +235,9 @@ void cmu_set_hfclk_source(enum cmu_osc osc)
 	case LFRCO:
 		CMU_CMD = CMU_CMD_HFCLKSEL_LFRCO;
 		break;
+	case USHFRCODIV2:
+		CMU_CMD = CMU_CMD_HFCLKSEL_USHFRCODIV2;
+		break;
 	default:
 		/* not applicable */
 		return;
@@ -239,6 +259,8 @@ enum cmu_osc cmu_get_hfclk_source(void)
 		return HFXO;
 	} else if (status & CMU_STATUS_HFRCOSEL) {
 		return HFRCO;
+	} else if (status & CMU_STATUS_USHFRCODIV2SEL) {
+		return USHFRCODIV2;
 	}
 
 	/* never reached */
@@ -247,7 +269,7 @@ enum cmu_osc cmu_get_hfclk_source(void)
 
 /**
  * Set USBCLK clock source
- * @retval enum cmu_osc Oscillator name
+ * @param osc Oscillator name
  */
 void cmu_set_usbclk_source(enum cmu_osc osc)
 {
@@ -288,3 +310,5 @@ void cmu_wait_for_usbclk_selected(enum cmu_osc osc)
 		return;
 	}
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile
index a0163677..da0ef81d 100644
--- a/lib/efm32/lg/Makefile
+++ b/lib/efm32/lg/Makefile
@@ -23,10 +23,8 @@ LIBNAME		= libopencm3_efm32lg
 SRCLIBDIR	?= ../..
 FAMILY		= EFM32LG
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -38,14 +36,27 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		=
 
-OBJS		= gpio_common.o cmu_common.o prs_common.o
-OBJS		+= adc_common.o dma_common.o timer_common.o
-OBJS		+= dac_common.o
+OBJS += acmp_common.o
+OBJS += adc_common.o
+OBJS += burtc_common.o
+OBJS += cmu_common.o
+OBJS += dac_common.o
+OBJS += dma_common.o
+OBJS += emu_common.o
+OBJS += gpio_common.o
+OBJS += i2c_common.o
+OBJS += letimer_common.o
+OBJS += msc_common.o
+OBJS += prs_common.o
+OBJS += rmu_common.o
+OBJS += rtc_common.o
+OBJS += timer_common.o
+OBJS += usart_common.o
+OBJS += wdog_common.o
 
-OBJS            += usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS            += usb_efm32.o
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += usb_efm32.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/efm32/tg/Makefile b/lib/efm32/tg/Makefile
index 43ab711c..d29ade3e 100644
--- a/lib/efm32/tg/Makefile
+++ b/lib/efm32/tg/Makefile
@@ -22,10 +22,8 @@ LIBNAME		= libopencm3_efm32tg
 SRCLIBDIR	?= ../..
 FAMILY		= EFM32TG
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
diff --git a/lib/efm32/wg/Makefile b/lib/efm32/wg/Makefile
index f2a767c5..0df4b0b6 100644
--- a/lib/efm32/wg/Makefile
+++ b/lib/efm32/wg/Makefile
@@ -24,10 +24,8 @@ SRCLIBDIR	?= ../..
 FAMILY		= EFM32WG
 
 FP_FLAGS        ?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -38,14 +36,27 @@ TGT_CFLAGS	= -Os \
 TGT_CFLAGS      += $(DEBUG_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		=
 
-OBJS		= gpio_common.o cmu_common.o prs_common.o
-OBJS		+= adc_common.o dma_common.o timer_common.o
-OBJS		+= dac_common.o
+OBJS += acmp_common.o
+OBJS += adc_common.o
+OBJS += burtc_common.o
+OBJS += cmu_common.o
+OBJS += dac_common.o
+OBJS += dma_common.o
+OBJS += emu_common.o
+OBJS += gpio_common.o
+OBJS += i2c_common.o
+OBJS += letimer_common.o
+OBJS += msc_common.o
+OBJS += prs_common.o
+OBJS += rmu_common.o
+OBJS += rtc_common.o
+OBJS += timer_common.o
+OBJS += usart_common.o
+OBJS += wdog_common.o
 
-OBJS            += usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS            += usb_efm32.o
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += usb_efm32.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/ethernet/mac_stm32fxx7.c b/lib/ethernet/mac_stm32fxx7.c
index 2a404b61..525f6229 100644
--- a/lib/ethernet/mac_stm32fxx7.c
+++ b/lib/ethernet/mac_stm32fxx7.c
@@ -371,7 +371,7 @@ void eth_smi_bit_clear(uint8_t phy, uint8_t reg, uint16_t clearbits)
  *
  * @param[in] phy uint8_t ID of the PHY (defaults to 1)
  * @param[in] reg uint8_t Register address
- * @param[in] bits uint16_t Bits that have to be set (or'ed)
+ * @param[in] setbits uint16_t Bits that have to be set (or'ed)
  */
 void eth_smi_bit_set(uint8_t phy, uint8_t reg, uint16_t setbits)
 {
diff --git a/lib/gd32/f1x0/Makefile b/lib/gd32/f1x0/Makefile
new file mode 100755
index 00000000..fb5cd4d6
--- /dev/null
+++ b/lib/gd32/f1x0/Makefile
@@ -0,0 +1,42 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME		= libopencm3_gd32f1x0
+SRCLIBDIR	?= ../..
+
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
+TGT_CFLAGS	= -Os \
+		  -Wall -Wextra -Wimplicit-function-declaration \
+		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
+		  -Wundef -Wshadow \
+		  -I../../../include -fno-common \
+		  -mcpu=cortex-m3 $(FP_FLAGS) -mthumb -Wstrict-prototypes \
+		  -ffunction-sections -fdata-sections -MD -DGD32F1X0
+TGT_CFLAGS      += $(DEBUG_FLAGS)
+# ARFLAGS	= rcsv
+ARFLAGS		= rcs
+
+OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += rcc.o rcc_common_all.o
+
+VPATH += ../:../../cm3:../common:../../stm32/common
+
+include ../../Makefile.include
diff --git a/lib/gd32/f1x0/flash.c b/lib/gd32/f1x0/flash.c
new file mode 100644
index 00000000..4f222082
--- /dev/null
+++ b/lib/gd32/f1x0/flash.c
@@ -0,0 +1,153 @@
+/** @defgroup flash_file  FLASH peripheral API
+ *
+ * @ingroup peripheral_apis
+ *
+ * @brief <b>libopencm3 GD32F1x0 FLASH</b>
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2013
+ * Frantisek Burian <BuFran@seznam.cz>
+ *
+ * @date 14 January 2014
+ *
+ * FLASH memory may be used for data storage as well as code, and may be
+ * programmatically modified. Note that for firmware upload the GD32F1x0
+ * provides a built-in bootloader in system memory that can be entered from a
+ * running program.
+ *
+ * FLASH must first be unlocked before programming. In this module a write to
+ * FLASH is a blocking operation until the end-of-operation flag is asserted.
+ *
+ * @note: don't forget to lock it again when all operations are complete.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/gd32/flash.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Clear All Status Flags
+
+Program error, end of operation, write protect error, busy.
+*/
+
+void flash_clear_status_flags(void)
+{
+	flash_clear_pgerr_flag();
+	flash_clear_eop_flag();
+	flash_clear_wrprterr_flag();
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Read All Status Flags
+
+The programming error, end of operation, write protect error and busy flags
+are returned in the order of appearance in the status register.
+
+@returns uint32_t. bit 0: busy, bit 2: programming error, bit 4: write protect
+error, bit 5: end of operation.
+*/
+
+uint32_t flash_get_status_flags(void)
+{
+	return FLASH_SR & (FLASH_SR_PGERR |
+			FLASH_SR_EOP |
+			FLASH_SR_WRPRTERR |
+			FLASH_SR_BSY);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Program a Half Word to FLASH
+
+This performs all operations necessary to program a 16 bit word to FLASH memory.
+The program error flag should be checked separately for the event that memory
+was not properly erased.
+
+Status bit polling is used to detect end of operation.
+
+@param[in] address Full address of flash half word to be programmed.
+@param[in] data half word to write
+*/
+
+void flash_program_half_word(uint32_t address, uint16_t data)
+{
+	flash_wait_for_last_operation();
+
+	FLASH_CR |= FLASH_CR_PG;
+
+	MMIO16(address) = data;
+
+	flash_wait_for_last_operation();
+
+	FLASH_CR &= ~FLASH_CR_PG;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Erase a Page of FLASH
+
+This performs all operations necessary to erase a page in FLASH memory.
+The page should be checked to ensure that it was properly erased. A page must
+first be fully erased before attempting to program it.
+
+Note that the page sizes differ between devices. See the reference manual or
+the FLASH programming manual for details.
+
+@param[in] page_address Full address of flash page to be erased.
+*/
+
+void flash_erase_page(uint32_t page_address)
+{
+	flash_wait_for_last_operation();
+
+	FLASH_CR |= FLASH_CR_PER;
+	FLASH_AR = page_address;
+	FLASH_CR |= FLASH_CR_STRT;
+
+	flash_wait_for_last_operation();
+
+	FLASH_CR &= ~FLASH_CR_PER;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Erase All FLASH
+
+This performs all operations necessary to erase all user pages in the FLASH
+memory. The information block is unaffected.
+*/
+
+void flash_erase_all_pages(void)
+{
+	flash_wait_for_last_operation();
+
+	FLASH_CR |= FLASH_CR_MER;		/* Enable mass erase. */
+	FLASH_CR |= FLASH_CR_STRT;		/* Trigger the erase. */
+
+	flash_wait_for_last_operation();
+	FLASH_CR &= ~FLASH_CR_MER;		/* Disable mass erase. */
+
+}
+
+/**@}*/
+
diff --git a/lib/gd32/f1x0/rcc.c b/lib/gd32/f1x0/rcc.c
new file mode 100644
index 00000000..729a71eb
--- /dev/null
+++ b/lib/gd32/f1x0/rcc.c
@@ -0,0 +1,654 @@
+/** @defgroup rcc_file RCC peripheral API
+
+@ingroup peripheral_apis
+
+@brief <b>libopencm3 GD32F1x0 Reset and Clock Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009
+Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+This library supports the Reset and Clock Control System in the GD32F1x0
+series of ARM Cortex Microcontrollers by GigaDevice.
+
+@note Full support for F170 and F190 devices is not yet provided.
+
+Clock settings and resets for many peripherals are given here rather than in
+the corresponding peripheral library.
+
+The library also provides a number of common configurations for the processor
+system clock. Not all possible configurations are included.
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2009 Federico Ruiz-Ugalde <memeruiz at gmail dot com>
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/cm3/assert.h>
+#include <libopencm3/gd32/rcc.h>
+#include <libopencm3/gd32/flash.h>
+
+/** Set the default clock frequencies */
+uint32_t rcc_apb1_frequency = 8000000;
+uint32_t rcc_apb2_frequency = 8000000;
+uint32_t rcc_ahb_frequency = 8000000;
+
+const struct rcc_clock_scale rcc_hsi_configs[] = {
+	{ /* 48MHz */
+		.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL12,
+		.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+		.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
+		.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+		.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
+		.use_hse = false,
+		.ahb_frequency	= 48000000,
+		.apb1_frequency = 24000000,
+		.apb2_frequency = 48000000,
+	},
+	{ /* 64MHz */
+		.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL16,
+		.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+		.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
+		.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+		.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
+		.use_hse = false,
+		.ahb_frequency	= 64000000,
+		.apb1_frequency = 32000000,
+		.apb2_frequency = 64000000,
+	}
+};
+
+const struct rcc_clock_scale rcc_hse8_configs[] = {
+	{ /* 72MHz */
+		.pllmul = RCC_CFGR_PLLMUL_PLL_CLK_MUL9,
+		.hpre = RCC_CFGR_HPRE_SYSCLK_NODIV,
+		.ppre1 = RCC_CFGR_PPRE1_HCLK_DIV2,
+		.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
+		.adcpre = RCC_CFGR_ADCPRE_PCLK2_DIV8,
+		.usbpre = RCC_CFGR_USBPRE_PLL_CLK_DIV1_5,
+		.use_hse = true,
+		.pll_hse_prediv = RCC_CFGR2_PREDIV_NODIV,
+		.ahb_frequency	= 72000000,
+		.apb1_frequency = 36000000,
+		.apb2_frequency = 72000000,
+	},
+};
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Clear the Oscillator Ready Interrupt Flag
+
+Clear the interrupt flag that was set when a clock oscillator became ready to
+use.
+
+@param[in] osc Oscillator ID
+*/
+
+void rcc_osc_ready_int_clear(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CIR |= RCC_CIR_PLLRDYC;
+		break;
+	case RCC_HSE:
+		RCC_CIR |= RCC_CIR_HSERDYC;
+		break;
+	case RCC_HSI:
+		RCC_CIR |= RCC_CIR_HSIRDYC;
+		break;
+	case RCC_LSE:
+		RCC_CIR |= RCC_CIR_LSERDYC;
+		break;
+	case RCC_LSI:
+		RCC_CIR |= RCC_CIR_LSIRDYC;
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Enable the Oscillator Ready Interrupt
+
+@param[in] osc Oscillator ID
+*/
+
+void rcc_osc_ready_int_enable(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CIR |= RCC_CIR_PLLRDYIE;
+		break;
+	case RCC_HSE:
+		RCC_CIR |= RCC_CIR_HSERDYIE;
+		break;
+	case RCC_HSI:
+		RCC_CIR |= RCC_CIR_HSIRDYIE;
+		break;
+	case RCC_LSE:
+		RCC_CIR |= RCC_CIR_LSERDYIE;
+		break;
+	case RCC_LSI:
+		RCC_CIR |= RCC_CIR_LSIRDYIE;
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Disable the Oscillator Ready Interrupt
+
+@param[in] osc Oscillator ID
+*/
+
+void rcc_osc_ready_int_disable(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CIR &= ~RCC_CIR_PLLRDYIE;
+		break;
+	case RCC_HSE:
+		RCC_CIR &= ~RCC_CIR_HSERDYIE;
+		break;
+	case RCC_HSI:
+		RCC_CIR &= ~RCC_CIR_HSIRDYIE;
+		break;
+	case RCC_LSE:
+		RCC_CIR &= ~RCC_CIR_LSERDYIE;
+		break;
+	case RCC_LSI:
+		RCC_CIR &= ~RCC_CIR_LSIRDYIE;
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Read the Oscillator Ready Interrupt Flag
+
+@param[in] osc Oscillator ID
+@returns int. Boolean value for flag set.
+*/
+
+int rcc_osc_ready_int_flag(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0);
+		break;
+	case RCC_HSE:
+		return ((RCC_CIR & RCC_CIR_HSERDYF) != 0);
+		break;
+	case RCC_HSI:
+		return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0);
+		break;
+	case RCC_LSE:
+		return ((RCC_CIR & RCC_CIR_LSERDYF) != 0);
+		break;
+	case RCC_LSI:
+		return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0);
+		break;
+	}
+
+	cm3_assert_not_reached();
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Clear the Clock Security System Interrupt Flag
+
+*/
+
+void rcc_css_int_clear(void)
+{
+	RCC_CIR |= RCC_CIR_CSSC;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Read the Clock Security System Interrupt Flag
+
+@returns int. Boolean value for flag set.
+*/
+
+int rcc_css_int_flag(void)
+{
+	return ((RCC_CIR & RCC_CIR_CSSF) != 0);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Wait for Oscillator Ready.
+
+@param[in] osc Oscillator ID
+*/
+
+void rcc_wait_for_osc_ready(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		while ((RCC_CR & RCC_CR_PLLRDY) == 0);
+		break;
+	case RCC_HSE:
+		while ((RCC_CR & RCC_CR_HSERDY) == 0);
+		break;
+	case RCC_HSI:
+		while ((RCC_CR & RCC_CR_HSIRDY) == 0);
+		break;
+	case RCC_LSE:
+		while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0);
+		break;
+	case RCC_LSI:
+		while ((RCC_CSR & RCC_CSR_LSIRDY) == 0);
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Turn on an Oscillator.
+
+Enable an oscillator and power on. Each oscillator requires an amount of time
+to settle to a usable state. Refer to datasheets for time delay information. A
+status flag is available to indicate when the oscillator becomes ready (see
+@ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready).
+
+@note The LSE clock is in the backup domain and cannot be enabled until the
+backup domain write protection has been removed (see @ref
+pwr_disable_backup_domain_write_protect).
+
+@param[in] osc Oscillator ID
+*/
+
+void rcc_osc_on(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CR |= RCC_CR_PLLON;
+		break;
+	case RCC_HSE:
+		RCC_CR |= RCC_CR_HSEON;
+		break;
+	case RCC_HSI:
+		RCC_CR |= RCC_CR_HSION;
+		break;
+	case RCC_LSE:
+		RCC_BDCR |= RCC_BDCR_LSEON;
+		break;
+	case RCC_LSI:
+		RCC_CSR |= RCC_CSR_LSION;
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Turn off an Oscillator.
+
+Disable an oscillator and power off.
+
+@note An oscillator cannot be turned off if it is selected as the system clock.
+@note The LSE clock is in the backup domain and cannot be disabled until the
+backup domain write protection has been removed (see
+@ref pwr_disable_backup_domain_write_protect) or the backup domain has been
+(see reset @ref rcc_backupdomain_reset).
+
+@param[in] osc Oscillator ID
+*/
+
+void rcc_osc_off(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CR &= ~RCC_CR_PLLON;
+		break;
+	case RCC_HSE:
+		RCC_CR &= ~RCC_CR_HSEON;
+		break;
+	case RCC_HSI:
+		RCC_CR &= ~RCC_CR_HSION;
+		break;
+	case RCC_LSE:
+		RCC_BDCR &= ~RCC_BDCR_LSEON;
+		break;
+	case RCC_LSI:
+		RCC_CSR &= ~RCC_CSR_LSION;
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Enable the Clock Security System.
+
+*/
+
+void rcc_css_enable(void)
+{
+	RCC_CR |= RCC_CR_CSSON;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Disable the Clock Security System.
+
+*/
+
+void rcc_css_disable(void)
+{
+	RCC_CR &= ~RCC_CR_CSSON;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the Source for the System Clock.
+
+@param[in] clk System Clock Selection @ref rcc_cfgr_scs
+*/
+
+void rcc_set_sysclk_source(uint32_t clk)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_SW) |
+			(clk << RCC_CFGR_SW_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the PLL Multiplication Factor.
+
+@note This only has effect when the PLL is disabled.
+
+@param[in] mul PLL multiplication factor @ref rcc_cfgr_pmf
+*/
+
+void rcc_set_pll_multiplication_factor(uint32_t mul)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLMUL_0_3 & ~RCC_CFGR_PLLMUL_4) |
+			((mul & 0xf) << RCC_CFGR_PLLMUL_0_3_SHIFT) |
+			((!!(mul & 0x10)) << RCC_CFGR_PLLMUL_4_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the PLL Clock Source.
+
+@note This only has effect when the PLL is disabled.
+
+@param[in] pllsrc PLL clock source @ref rcc_cfgr_pcs
+*/
+
+void rcc_set_pll_source(uint32_t pllsrc)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLSRC) |
+			(pllsrc << 16);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source.
+
+@note This only has effect when the PLL is disabled.
+
+@param[in] pllxtpre HSE division factor @ref rcc_cfgr_hsepre
+*/
+
+void rcc_set_pllxtpre(uint32_t pllxtpre)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PLLXTPRE) |
+			(pllxtpre << 17);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC RTC Clock Enabled Flag
+
+@returns uint32_t. Nonzero if the RTC Clock is enabled.
+*/
+
+uint32_t rcc_rtc_clock_enabled_flag(void)
+{
+	return RCC_BDCR & RCC_BDCR_RTCEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Enable the RTC clock
+
+*/
+
+void rcc_enable_rtc_clock(void)
+{
+	RCC_BDCR |= RCC_BDCR_RTCEN;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the Source for the RTC clock
+
+@param[in] clock_source RTC clock source. Only HSE/128, LSE and LSI.
+*/
+
+void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
+{
+	uint32_t reg32;
+
+	switch (clock_source) {
+	case RCC_LSE:
+		/* Turn the LSE on and wait while it stabilises. */
+		RCC_BDCR |= RCC_BDCR_LSEON;
+		while ((reg32 = (RCC_BDCR & RCC_BDCR_LSERDY)) == 0);
+
+		/* Choose LSE as the RTC clock source. */
+		RCC_BDCR &= ~((1 << 8) | (1 << 9));
+		RCC_BDCR |= (1 << 8);
+		break;
+	case RCC_LSI:
+		/* Turn the LSI on and wait while it stabilises. */
+		RCC_CSR |= RCC_CSR_LSION;
+		while ((reg32 = (RCC_CSR & RCC_CSR_LSIRDY)) == 0);
+
+		/* Choose LSI as the RTC clock source. */
+		RCC_BDCR &= ~((1 << 8) | (1 << 9));
+		RCC_BDCR |= (1 << 9);
+		break;
+	case RCC_HSE:
+		/* Turn the HSE on and wait while it stabilises. */
+		RCC_CR |= RCC_CR_HSEON;
+		while ((reg32 = (RCC_CR & RCC_CR_HSERDY)) == 0);
+
+		/* Choose HSE as the RTC clock source. */
+		RCC_BDCR &= ~((1 << 8) | (1 << 9));
+		RCC_BDCR |= (1 << 9) | (1 << 8);
+		break;
+	case RCC_PLL:
+	case RCC_HSI:
+		/* Unusable clock source, here to prevent warnings. */
+		/* Turn off clock sources to RTC. */
+		RCC_BDCR &= ~((1 << 8) | (1 << 9));
+		break;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Setup the A/D Clock
+
+The ADC's have a common clock prescale setting.
+
+@param[in] adcpre Prescale divider taken from @ref rcc_cfgr_adcpre
+*/
+
+void rcc_set_adcpre(uint32_t adcpre)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_ADCPRE) |
+			(adcpre << RCC_CFGR_ADCPRE_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the APB2 Prescale Factor.
+
+@param[in] ppre2 APB2 prescale factor @ref rcc_cfgr_apb2pre
+*/
+
+void rcc_set_ppre2(uint32_t ppre2)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE2) |
+			(ppre2 << RCC_CFGR_PPRE2_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the APB1 Prescale Factor.
+
+@note The APB1 clock frequency must not exceed 36MHz.
+
+@param[in] ppre1 APB1 prescale factor @ref rcc_cfgr_apb1pre
+*/
+
+void rcc_set_ppre1(uint32_t ppre1)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_PPRE1) |
+			(ppre1 << RCC_CFGR_PPRE1_SHIFT);
+
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the AHB Prescale Factor.
+
+@param[in] hpre AHB prescale factor @ref rcc_cfgr_ahbpre
+*/
+
+void rcc_set_hpre(uint32_t hpre)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_HPRE) |
+			(hpre << RCC_CFGR_HPRE_SHIFT);
+
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Set the USB Prescale Factor.
+
+The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
+48MHz, or 1.5 to generate the 48MHz USB clock from a 64MHz PLL clock.
+
+@note This bit cannot be reset while the USB clock is enabled.
+
+@param[in] usbpre USB prescale factor @ref rcc_cfgr_usbpre
+*/
+
+void rcc_set_usbpre(uint32_t usbpre)
+{
+	RCC_CFGR = (RCC_CFGR & ~RCC_CFGR_USBPRE) | usbpre;
+}
+
+void rcc_set_prediv(uint32_t prediv)
+{
+	RCC_CFGR2 = (RCC_CFGR2 & ~RCC_CFGR2_PREDIV) | prediv;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Get the System Clock Source.
+
+@returns Unsigned int32. System clock source:
+@li 00 indicates HSE
+@li 01 indicates LSE
+@li 02 indicates PLL
+*/
+
+uint32_t rcc_system_clock_source(void)
+{
+	/* Return the clock source which is used as system clock. */
+	return (RCC_CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_SHIFT;
+}
+
+/*---------------------------------------------------------------------------*/
+/*
+ * These functions are setting up the whole clock system for the most common
+ * input clock and output clock configurations.
+ */
+/*---------------------------------------------------------------------------*/
+/**
+ * Setup clocks to run from PLL.
+ * The arguments provide the pll source, multipliers, dividers, all that's
+ * needed to establish a system clock.
+ * @param clock clock information structure
+ */
+void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
+{
+	if (clock->use_hse) {
+		/* Enable external high-speed oscillator. */
+		rcc_osc_on(RCC_HSE);
+		rcc_wait_for_osc_ready(RCC_HSE);
+		rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
+	} else {
+		/* Enable internal high-speed oscillator. */
+		rcc_osc_on(RCC_HSI);
+		rcc_wait_for_osc_ready(RCC_HSI);
+		rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
+	}
+
+	/*
+	 * Set prescalers for AHB, ADC, APB1, APB2 and USB.
+	 * Do this before touching the PLL (TODO: why?).
+	 */
+	rcc_set_hpre(clock->hpre);
+	rcc_set_ppre1(clock->ppre1);
+	rcc_set_ppre2(clock->ppre2);
+
+	rcc_set_adcpre(clock->adcpre);
+	if (clock->use_hse)
+		rcc_set_usbpre(clock->usbpre);
+
+	/* Set the PLL multiplication factor. */
+	rcc_set_pll_multiplication_factor(clock->pllmul);
+
+	if (clock->use_hse) {
+		/* Select HSE as PLL source. */
+		rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
+
+		/*
+		 * External frequency undivided before entering PLL
+		 * (only valid/needed for HSE).
+		 */
+		rcc_set_prediv(clock->pll_hse_prediv);
+	} else {
+		/* Select HSI/2 as PLL source. */
+		rcc_set_pll_source(RCC_CFGR_PLLSRC_HSI_CLK_DIV2);
+	}
+
+	/* Enable PLL oscillator and wait for it to stabilize. */
+	rcc_osc_on(RCC_PLL);
+	rcc_wait_for_osc_ready(RCC_PLL);
+
+	/* Select PLL as SYSCLK source. */
+	rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
+
+	/* Set the peripheral clock frequencies used */
+	rcc_ahb_frequency = clock->ahb_frequency;
+	rcc_apb1_frequency = clock->apb1_frequency;
+	rcc_apb2_frequency = clock->apb2_frequency;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief RCC Reset the Backup Domain
+
+The backup domain registers are reset to disable RTC controls and clear user
+data.
+*/
+
+void rcc_backupdomain_reset(void)
+{
+	/* Set the backup domain software reset. */
+	RCC_BDCR |= RCC_BDCR_BDRST;
+
+	/* Clear the backup domain software reset. */
+	RCC_BDCR &= ~RCC_BDCR_BDRST;
+}
+
+/**@}*/
+
diff --git a/lib/lm3s/Makefile b/lib/lm3s/Makefile
index 7bce6313..287ccacc 100644
--- a/lib/lm3s/Makefile
+++ b/lib/lm3s/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_lm3s
 SRCLIBDIR	?= ..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -35,7 +33,12 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio.o vector.o assert.o rcc.o usart.o
+
+OBJS += assert.o
+OBJS += gpio.o
+OBJS += rcc.o
+OBJS += usart.o
+OBJS += vector.o
 
 VPATH += ../cm3
 
diff --git a/lib/lm3s/rcc.c b/lib/lm3s/rcc.c
index 96c09504..248ff815 100644
--- a/lib/lm3s/rcc.c
+++ b/lib/lm3s/rcc.c
@@ -7,7 +7,7 @@
 @version 1.0.0
 
 @author @htmlonly &copy; @endhtmlonly 2015
-Daniele Lacamera <root at danielinux dot net>
+Daniele Lacamera \<root at danielinux dot net\>
 
 @date 21 November 2015
 
diff --git a/lib/lm4f/Makefile b/lib/lm4f/Makefile
index 2cb3853a..ab23f083 100644
--- a/lib/lm4f/Makefile
+++ b/lib/lm4f/Makefile
@@ -22,10 +22,8 @@ LIBNAME		= libopencm3_lm4f
 SRCLIBDIR	?= ..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -37,9 +35,16 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio.o vector.o assert.o systemcontrol.o rcc.o uart.o \
-		  usb_lm4f.o usb.o usb_control.o usb_standard.o
-OBJS		+= usb_msc.o
+
+OBJS += assert.o
+OBJS += gpio.o
+OBJS += rcc.o
+OBJS += systemcontrol.o
+OBJS += uart.o
+OBJS += vector.o
+
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += usb_lm4f.o
 
 VPATH += ../usb:../cm3
 
diff --git a/lib/lpc13xx/Makefile b/lib/lpc13xx/Makefile
index 5b6ec485..7d12597e 100644
--- a/lib/lpc13xx/Makefile
+++ b/lib/lpc13xx/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_lpc13xx
 SRCLIBDIR	?= ..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -35,7 +33,8 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio.o
+
+OBJS += gpio.o
 
 VPATH += ../cm3
 
diff --git a/lib/lpc17xx/Makefile b/lib/lpc17xx/Makefile
index 5a34606e..eaaef8c8 100644
--- a/lib/lpc17xx/Makefile
+++ b/lib/lpc17xx/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_lpc17xx
 SRCLIBDIR	?= ..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -35,7 +33,9 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio.o pwr.o
+
+OBJS += gpio.o
+OBJS += pwr.o
 
 VPATH += ../cm3
 
diff --git a/lib/lpc43xx/m0/Makefile b/lib/lpc43xx/m0/Makefile
index e05b799c..6f36574b 100644
--- a/lib/lpc43xx/m0/Makefile
+++ b/lib/lpc43xx/m0/Makefile
@@ -22,10 +22,8 @@
 LIBNAME		= libopencm3_lpc43xx_m0
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -O2 -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m0 -mthumb -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DLPC43XX -DLPC43XX_M0
diff --git a/lib/lpc43xx/m4/Makefile b/lib/lpc43xx/m4/Makefile
index 4c022f92..e9ca7eaf 100644
--- a/lib/lpc43xx/m4/Makefile
+++ b/lib/lpc43xx/m4/Makefile
@@ -24,10 +24,8 @@ LIBNAME		= libopencm3_lpc43xx
 SRCLIBDIR	?= ../..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -O2 \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
diff --git a/lib/msp432/e4/Makefile b/lib/msp432/e4/Makefile
index 61abb1ab..53d20f78 100644
--- a/lib/msp432/e4/Makefile
+++ b/lib/msp432/e4/Makefile
@@ -23,10 +23,8 @@ LIBNAME		= libopencm3_msp432e4
 SRCLIBDIR	?= ../..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX	        ?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -40,7 +38,8 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
 
-OBJS		= systemcontrol.o
+OBJS += gpio.o
+OBJS += systemcontrol.o
 
 VPATH += ../:../../cm3:../common
 
diff --git a/lib/msp432/e4/gpio.c b/lib/msp432/e4/gpio.c
new file mode 100644
index 00000000..f4b082cf
--- /dev/null
+++ b/lib/msp432/e4/gpio.c
@@ -0,0 +1,448 @@
+/** @defgroup gpio_file General-Purpose I/O
+ *
+ * @ingroup MSP432E4xx
+ *
+ * @brief libopencm3 MSP432E4xx General Purpose Input/Outputs
+ *
+ * @version 1.0.0
+ *
+ * @date 23 September 2018
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
+ * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Copyright (C) 2018 Dmitry Rezvanov <dmitry.rezvanov@yandex.ru>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/msp432/e4/gpio.h>
+#include <libopencm3/msp432/e4/systemcontrol.h>
+
+/** @brief General Purpose Input/Outputs Set Pin Mode
+ *
+ * Sets the Pin Direction, Analog/Digital Mode and Output Pin Pull,
+ * for a set of GPIO pins on a given GPIO port.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] mode Pin mode @ref gpio_mode
+ *            - GPIO_MODE_OUTPUT -- Configure pin as output
+ *            - GPIO_MODE_INPUT  -- Configure pin as input
+ *            - GPIO_MODE_ANALOG -- Configure pin as analog function
+ * @param[in] pull_up_down Pin pull up/down configuration @ref gpio_pull_up_down
+ *            - GPIO_PUPD_NONE     -- Do not pull the pin high or low
+ *            - GPIO_PUPD_PULLUP   -- Pull the pin high
+ *            - GPIO_PUPD_PULLDOWN -- Pull the pin low
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be set, use bitwise OR '|' to separate them.
+ */
+void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode,
+	enum gpio_pull_up_down pull_up_down, uint8_t gpios)
+{
+	GPIO_AFSEL(gpioport) &= ~gpios;
+
+	switch (mode) {
+	case GPIO_MODE_OUTPUT:
+		GPIO_DIR(gpioport) |= gpios;
+		GPIO_DEN(gpioport) |= gpios;
+		GPIO_AMSEL(gpioport) &= ~gpios;
+		break;
+	case GPIO_MODE_INPUT:
+		GPIO_DIR(gpioport) &= ~gpios;
+		GPIO_DEN(gpioport) |= gpios;
+		GPIO_AMSEL(gpioport) &= ~gpios;
+		break;
+	case GPIO_MODE_ANALOG:
+		GPIO_AFSEL(gpioport) |= gpios;
+		GPIO_DEN(gpioport) &= ~gpios;
+		GPIO_AMSEL(gpioport) |= gpios;
+		break;
+	default:
+		/* Don't do anything */
+		break;
+	}
+
+	/*
+	 * Setting a bit in the GPIO_PDR register clears the corresponding bit
+	 * in the GPIO_PUR register, and vice-versa.
+	 */
+	switch (pull_up_down) {
+	case GPIO_PUPD_PULLUP:
+		GPIO_PDR(gpioport) &= ~gpios;
+		GPIO_PUR(gpioport) |= gpios;
+		break;
+	case GPIO_PUPD_PULLDOWN:
+		GPIO_PUR(gpioport) &= ~gpios;
+		GPIO_PDR(gpioport) |= gpios;
+		break;
+	case GPIO_PUPD_NONE: /* Fall through */
+	default:
+		GPIO_PUR(gpioport) &= ~gpios;
+		GPIO_PDR(gpioport) &= ~gpios;
+		break;
+	}
+}
+
+/** @brief General Purpose Input/Outputs Set Output Options
+ *
+ * When the pin is set to output mode, this sets the configuration
+ * (open drain/push pull), drive strength, speed and slew rate control,
+ * for a set of GPIO pins on a given GPIO port.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] otype Output driver configuration @ref gpio_output_type
+ *            - GPIO_OTYPE_PP -- Configure pin driver as push-pull \n
+ *            - GPIO_OTYPE_OD -- Configure pin driver as open drain
+ * @param[in] drive Pin drive strength @ref gpio_drive_strength
+ *            - GPIO_DRIVE_2MA  -- 2mA drive \n
+ *            - GPIO_DRIVE_4MA  -- 4mA drive \n
+ *            - GPIO_DRIVE_6MA  -- 4mA drive \n
+ *            - GPIO_DRIVE_8MA  -- 8mA drive \n
+ *            - GPIO_DRIVE_10MA -- 10mA drive \n
+ *            - GPIO_DRIVE_12MA -- 12mA drive
+ * @param[in] slewctl Pin slew rate control select @ref gpio_slew_ctl
+ *            @note Available only for 8, 10 and 12-ma drive strength.
+ *            - GPIO_SLEW_CTL_ENABLE  -- Slew rate control enable
+ *            - GPIO_SLEW_CTL_DISABLE -- Slew rate control disable
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be set, use bitwise OR '|' to separate them.
+ */
+void gpio_set_output_options(uint32_t gpioport,
+	enum gpio_output_type otype,
+	enum gpio_drive_strength drive,
+	enum gpio_slew_ctl slewctl,
+	uint8_t gpios)
+{
+	uint8_t i;
+	uint8_t pin_mask;
+
+	if (otype == GPIO_OTYPE_OD) {
+		GPIO_ODR(gpioport) |= gpios;
+	} else {
+		GPIO_ODR(gpioport) &= ~gpios;
+	}
+
+	GPIO_PP(gpioport) |= GPIO_PP_EDE;
+
+	for (i = 0; i < 8; i++) {
+		pin_mask = (1 << i);
+
+		if (!(gpios & pin_mask)) {
+			continue;
+		}
+
+		GPIO_PC(gpioport) &= ~GPIO_PC_EDM_MASK(i);
+		GPIO_PC(gpioport) |= GPIO_PC_EDM(i, GPIO_PC_EDM_FULL_RANGE);
+	}
+
+	GPIO_DR4R(gpioport) &= ~gpios;
+	GPIO_DR8R(gpioport) &= ~gpios;
+	GPIO_DR12R(gpioport) &= ~gpios;
+
+	switch (drive) {
+	case GPIO_DRIVE_4MA:
+		GPIO_DR4R(gpioport) |= gpios;
+		break;
+	case GPIO_DRIVE_6MA:
+		GPIO_DR8R(gpioport) |= gpios;
+		break;
+	case GPIO_DRIVE_8MA:
+		GPIO_DR4R(gpioport) |= gpios;
+		GPIO_DR8R(gpioport) |= gpios;
+		break;
+	case GPIO_DRIVE_10MA:
+		GPIO_DR8R(gpioport) |= gpios;
+		GPIO_DR12R(gpioport) |= gpios;
+		break;
+	case GPIO_DRIVE_12MA:
+		GPIO_DR4R(gpioport) |= gpios;
+		GPIO_DR8R(gpioport) |= gpios;
+		GPIO_DR12R(gpioport) |= gpios;
+		break;
+	case GPIO_DRIVE_2MA: /* Fall through */
+	default:
+		/* don't anything */
+		break;
+	}
+
+	if ((slewctl == GPIO_SLEW_CTL_ENABLE) &&
+		((drive == GPIO_DRIVE_8MA) || (drive == GPIO_DRIVE_10MA) ||
+		(drive == GPIO_DRIVE_12MA))) {
+		GPIO_SLR(gpioport) |= gpios;
+	} else {
+		GPIO_SLR(gpioport) &= ~gpios;
+	}
+}
+
+/** @brief General Purpose Input/Outputs Set Alternate Function Selection
+ *
+ * Mux the pin or group of pins to the given alternate function. Note that a
+ * number of pins may be set but only with a single AF number.
+ *
+ * Because AF0 is not used on the MSP432E4,
+ * passing GPIO_AF_DISABLE as the alt_func_num parameter will disable
+ * the alternate function of the given pins.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] alt_func_num Pin alternate function number or GPIO_AF_DISABLE to
+ * disable the alternate function multiplexing.
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be set, use bitwise OR '|' to separate them.
+ */
+void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios)
+{
+	uint32_t pctl32;
+	uint8_t pin_mask;
+	uint8_t i;
+
+	/* Did we mean to disable the alternate function? */
+	if (alt_func_num == 0) {
+		GPIO_AFSEL(gpioport) &= ~gpios;
+		return;
+	}
+
+	/* Enable the alternate function */
+	GPIO_AFSEL(gpioport) |= gpios;
+
+	/* Now take care of the actual multiplexing */
+	pctl32 = GPIO_PCTL(gpioport);
+	for (i = 0; i < 8; i++) {
+		pin_mask = (1 << i);
+
+		if (!(gpios & pin_mask)) {
+			continue;
+		}
+
+		pctl32 &= ~GPIO_PCTL_MASK(i);
+		pctl32 |= GPIO_PCTL_AF(i, (alt_func_num & 0xf));
+	}
+
+	GPIO_PCTL(gpioport) = pctl32;
+}
+
+/** @brief General Purpose Input/Outputs Configure Interrupt Trigger
+ *
+ * Sets the trigger level/edge, for a set of GPIO pins on a given GPIO port.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] trigger Trigger configuration @ref gpio_trigger
+ *            - GPIO_TRIG_LVL_LOW   -- Trigger on low level
+ *            - GPIO_TRIG_LVL_HIGH  -- Trigger on high level
+ *            - GPIO_TRIG_EDGE_FALL -- Trigger on falling edges
+ *            - GPIO_TRIG_EDGE_RISE -- Trigger on rising edges
+ *            - GPIO_TRIG_EDGE_BOTH -- Trigger on all edges
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be configure, use bitwise OR '|' to separate them.
+ */
+void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger,
+	uint8_t gpios)
+{
+	switch (trigger) {
+	case GPIO_TRIG_LVL_LOW:
+		GPIO_IS(gpioport) |= gpios;
+		GPIO_IEV(gpioport) &= ~gpios;
+		break;
+	case GPIO_TRIG_LVL_HIGH:
+		GPIO_IS(gpioport) |= gpios;
+		GPIO_IEV(gpioport) |= gpios;
+		break;
+	case GPIO_TRIG_EDGE_FALL:
+		GPIO_IS(gpioport) &= ~gpios;
+		GPIO_IBE(gpioport) &= ~gpios;
+		GPIO_IEV(gpioport) &= ~gpios;
+		break;
+	case GPIO_TRIG_EDGE_RISE:
+		GPIO_IS(gpioport) &= ~gpios;
+		GPIO_IBE(gpioport) &= ~gpios;
+		GPIO_IEV(gpioport) |= gpios;
+		break;
+	case GPIO_TRIG_EDGE_BOTH:
+		GPIO_IS(gpioport) &= ~gpios;
+		GPIO_IBE(gpioport) |= gpios;
+		break;
+	default:
+		/* Don't do anything */
+		break;
+	}
+}
+
+/** @brief General Purpose Input/Outputs Set a Group of Pins Atomic
+ *
+ * Set one or more pins of the given GPIO port to 1 in an atomic operation.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be changed, use bitwise OR '|' to separate them.
+ */
+void gpio_set(uint32_t gpioport, uint8_t gpios)
+{
+	GPIO_DATA(gpioport)[gpios] = 0xFF;
+}
+
+/** @brief General Purpose Input/Outputs Clear a Group of Pins Atomic
+ *
+ * Clear one or more pins of the given GPIO port to 0 in an atomic operation.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be changed, use bitwise OR '|' to separate them.
+ */
+void gpio_clear(uint32_t gpioport, uint8_t gpios)
+{
+	GPIO_DATA(gpioport)[gpios] = 0x0;
+}
+
+/** @brief General Purpose Input/Outputs Read a Group of Pins
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be read, use bitwise OR '|' to separate them.
+ *
+ * @return Unsigned int8 value of the pin values. The bit position of the pin
+	   value returned corresponds to the pin number.
+ */
+uint8_t gpio_get(uint32_t gpioport, uint8_t gpios)
+{
+	return (uint8_t)GPIO_DATA(gpioport)[gpios];
+}
+
+/** @brief General Purpose Input/Outputs Toggle a Group of Pins
+ *
+ * Toggle one or more pins of the given GPIO port.
+ * The non-toggled pins are not affected.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be changed, use bitwise OR '|' to separate them.
+ */
+void gpio_toggle(uint32_t gpioport, uint8_t gpios)
+{
+	/* The mask makes sure we only toggle the GPIOs we want to */
+	GPIO_DATA(gpioport)[gpios] ^= GPIO_ALL;
+}
+
+/** @brief General Purpose Input/Outputs Read from a Port
+ *
+ * Read the current value of the given GPIO port.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ *
+ * @return Unsigned int8. The value held in the specified GPIO port.
+ */
+uint8_t gpio_port_read(uint32_t gpioport)
+{
+	return (uint8_t)GPIO_DATA(gpioport)[GPIO_ALL];
+}
+
+/** @brief General Purpose Input/Outputs Write to a Port
+ *
+ * Write a value to the given GPIO port.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] data Unsigned int8. The value to be written to the GPIO port.
+ */
+void gpio_port_write(uint32_t gpioport, uint8_t data)
+{
+	GPIO_DATA(gpioport)[GPIO_ALL] = data;
+}
+
+/** @brief General Purpose Input/Outputs Enable Interrupts on specified pins
+ *
+ * Enable interrupts on the specified GPIO pins.
+ *
+ * @note The NVIC must be enabled and properly configured for the interrupt
+ *       to be routed to the CPU.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base)
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id.
+ *            Pins whose interrupts to enable.
+ *            If multiple pins are to be enable interrupt,
+ *            use bitwise OR '|' to separate them.
+ */
+void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios)
+{
+	GPIO_IM(gpioport) |= gpios;
+}
+
+/** @brief General Purpose Input/Outputs Disable interrupts on specified pins
+ *
+ * Disable interrupts on the specified GPIO pins.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id.
+ *            Pins whose interrupts to disable.
+ *            If multiple pins are to be disable interrupt,
+ *            use bitwise OR '|' to separate them.
+ */
+void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios)
+{
+	GPIO_IM(gpioport) &= ~gpios;
+}
+
+/** @brief General Purpose Input/Outputs Unlock The Commit Control
+ *
+ * Unlocks the commit control of the given pin or group of pins. If a pin is a
+ * JTAG/SWD or NMI, the pin may then be reconfigured as a GPIO pin. If the pin
+ * is not locked by default, this has no effect.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id.
+ *            If multiple pins are to be unlock,
+ *            use bitwise OR '|' to separate them.
+ */
+void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios)
+{
+	/* Unlock the GPIO_CR register */
+	GPIO_LOCK(gpioport) = GPIO_LOCK_UNLOCK_CODE;
+	/* Enable committing changes */
+	GPIO_CR(gpioport) |= gpios;
+	/* Lock the GPIO_CR register */
+	GPIO_LOCK(gpioport) = ~GPIO_LOCK_UNLOCK_CODE;
+}
+
+/** @brief General Purpose Input/Outputs Determine if interrupt is generated
+ *         by the given pin
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Source pin identifiers @ref gpio_pin_id.
+ *            If multiple pins are to be check,
+ *            use bitwise OR '|' to separate them.
+ *
+ * @return Unsigned int8. The bit position of the pin
+	   value returned corresponds to the pin number.
+ */
+uint8_t gpio_is_interrupt_source(uint32_t gpioport, uint8_t gpios)
+{
+	return GPIO_MIS(gpioport) & gpios;
+}
+
+/** @brief General Purpose Input/Outputs Mark Interrupt as Serviced
+ *
+ * After an interrupt is services, its flag must be cleared. If the flag is not
+ * cleared, then execution will jump back to the start of the ISR after the ISR
+ * returns.
+ *
+ * @param[in] gpioport GPIO block register address base @ref gpio_reg_base
+ * @param[in] gpios Pin identifiers @ref gpio_pin_id. If multiple pins are
+ *            to be clear interrupt flag, use bitwise OR '|' to separate them.
+ */
+void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios)
+{
+	GPIO_ICR(gpioport) |= gpios;
+}
diff --git a/lib/msp432/e4/systemcontrol.c b/lib/msp432/e4/systemcontrol.c
index 8a441175..01a20739 100644
--- a/lib/msp432/e4/systemcontrol.c
+++ b/lib/msp432/e4/systemcontrol.c
@@ -44,9 +44,9 @@
  * @param[in] periph ::msp432_periph Peripheral block
  */
 void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode,
-                                enum msp432_periph periph)
+	enum msp432_periph periph)
 {
-    _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph);
+	_SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) |= _SYSCTL_BIT(periph);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -56,9 +56,9 @@ void sysctl_periph_clock_enable(enum msp432_clock_mode clock_mode,
  * @param[in] periph ::msp432_periph Peripheral block
  */
 void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode,
-                                 enum msp432_periph periph)
+	enum msp432_periph periph)
 {
-    _SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph);
+	_SYSCTL_REG(SYSCTL_BASE + clock_mode, periph) &= ~_SYSCTL_BIT(periph);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -68,7 +68,7 @@ void sysctl_periph_clock_disable(enum msp432_clock_mode clock_mode,
  */
 void sysctl_periph_reset(enum msp432_periph periph)
 {
-    _SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph);
+	_SYSCTL_REG((uint32_t) &SYSCTL_SRWD, periph) |= _SYSCTL_BIT(periph);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -78,7 +78,7 @@ void sysctl_periph_reset(enum msp432_periph periph)
  */
 void sysctl_periph_clear_reset(enum msp432_periph periph)
 {
-    _SYSCTL_REG((uint32_t)&SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph);
+	_SYSCTL_REG((uint32_t) &SYSCTL_SRWD, periph) &= ~_SYSCTL_BIT(periph);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -88,10 +88,10 @@ void sysctl_periph_clear_reset(enum msp432_periph periph)
  */
 bool sysctl_periph_is_present(enum msp432_periph periph)
 {
-    uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PPWD, periph);
-    uint32_t mask = _SYSCTL_BIT(periph);
+	uint32_t reg32 = _SYSCTL_REG((uint32_t) &SYSCTL_PPWD, periph);
+	uint32_t mask = _SYSCTL_BIT(periph);
 
-    return ((reg32 & mask) != 0);
+	return((reg32 & mask) != 0);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -101,10 +101,10 @@ bool sysctl_periph_is_present(enum msp432_periph periph)
  */
 bool sysctl_periph_is_ready(enum msp432_periph periph)
 {
-    uint32_t reg32 = _SYSCTL_REG((uint32_t)&SYSCTL_PRWD, periph);
-    uint32_t mask = _SYSCTL_BIT(periph);
+	uint32_t reg32 = _SYSCTL_REG((uint32_t) &SYSCTL_PRWD, periph);
+	uint32_t mask = _SYSCTL_BIT(periph);
 
-    return ((reg32 & mask) != 0);
+	return((reg32 & mask) != 0);
 }
 
 /*----------------------------------------------------------------------------*/
@@ -117,13 +117,13 @@ bool sysctl_periph_is_ready(enum msp432_periph periph)
  * is powered and receives a clock regardless of the value of power mode.
  */
 void sysctl_periph_set_power_state(enum msp432_power_mode power_mode,
-                                   enum msp432_periph periph)
+	enum msp432_periph periph)
 {
-    if(power_mode == POWER_ENABLE) {
-        _SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph);
-    } else {
-        _SYSCTL_REG((uint32_t)&SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph);
-    }
+	if (power_mode == POWER_ENABLE) {
+		_SYSCTL_REG((uint32_t) &SYSCTL_PCWD, periph) |= _SYSCTL_BIT(periph);
+	} else {
+		_SYSCTL_REG((uint32_t) &SYSCTL_PCWD, periph) &= ~_SYSCTL_BIT(periph);
+	}
 }
 
 #undef _SYSCTL_REG
diff --git a/lib/sam/3a/Makefile b/lib/sam/3a/Makefile
index 5b9293d7..61183ae4 100644
--- a/lib/sam/3a/Makefile
+++ b/lib/sam/3a/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_sam3a
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAM3A
@@ -31,7 +29,10 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o
+
+OBJS += gpio_common_all.o gpio_common_3a3u3x.o
+OBJS += pmc.o
+OBJS += usart_common_all.o usart_common_3.o
 
 VPATH += ../../usb:../../cm3:../common
 
diff --git a/lib/sam/3n/Makefile b/lib/sam/3n/Makefile
index 2baa2ee2..167e9093 100644
--- a/lib/sam/3n/Makefile
+++ b/lib/sam/3n/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_sam3n
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAM3N
@@ -31,7 +29,10 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio_common_all.o gpio_common_3n3s.o pmc.o usart_common_all.o usart_common_3.o
+
+OBJS += gpio_common_all.o gpio_common_3n3s.o
+OBJS += pmc.o
+OBJS += usart_common_all.o usart_common_3.o
 
 VPATH += ../../cm3:../common
 
diff --git a/lib/sam/3s/Makefile b/lib/sam/3s/Makefile
index 4ec0b12b..e20931e2 100644
--- a/lib/sam/3s/Makefile
+++ b/lib/sam/3s/Makefile
@@ -21,10 +21,8 @@
 LIBNAME		= libopencm3_sam3s
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAM3S
@@ -32,7 +30,10 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio_common_all.o gpio_common_3n3s.o pmc.o usart_common_all.o usart_common_3.o
+
+OBJS += gpio_common_all.o gpio_common_3n3s.o
+OBJS += pmc.o
+OBJS += usart_common_all.o usart_common_3.o
 
 VPATH += ../../usb:../../cm3:../common
 
diff --git a/lib/sam/3u/Makefile b/lib/sam/3u/Makefile
index 4b0ab0ce..5dce7e92 100644
--- a/lib/sam/3u/Makefile
+++ b/lib/sam/3u/Makefile
@@ -21,10 +21,8 @@
 LIBNAME		= libopencm3_sam3u
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAM3U
@@ -32,7 +30,10 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o
+
+OBJS += gpio_common_all.o gpio_common_3a3u3x.o
+OBJS += pmc.o
+OBJS += usart_common_all.o usart_common_3.o
 
 VPATH += ../../usb:../../cm3:../common
 
diff --git a/lib/sam/3x/Makefile b/lib/sam/3x/Makefile
index c3dbc02d..5fa4c419 100644
--- a/lib/sam/3x/Makefile
+++ b/lib/sam/3x/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_sam3x
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m3 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAM3X
@@ -31,7 +29,10 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= gpio_common_all.o gpio_common_3a3u3x.o pmc.o usart_common_all.o usart_common_3.o
+
+OBJS += gpio_common_all.o gpio_common_3a3u3x.o
+OBJS += pmc.o
+OBJS += usart_common_all.o usart_common_3.o
 
 VPATH += ../../usb:../../cm3:../common
 
diff --git a/lib/sam/4l/Makefile b/lib/sam/4l/Makefile
index 42a507f0..fd8d825b 100644
--- a/lib/sam/4l/Makefile
+++ b/lib/sam/4l/Makefile
@@ -18,18 +18,21 @@
 LIBNAME		= libopencm3_sam4l
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
 FP_FLAGS ?= -msoft-float
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAM4L
 TGT_CFLAGS      += $(DEBUG_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= adcife.o gpio.o scif.o pm.o usart_common_all.o usart.o
+
+OBJS += adcife.o
+OBJS += gpio.o
+OBJS += pm.o
+OBJS += scif.o
+OBJS += usart_common_all.o usart.o
 
 VPATH += ../../usb:../../cm3:../common
 
diff --git a/lib/sam/d/Makefile b/lib/sam/d/Makefile
index 0a2a5c89..380ade30 100644
--- a/lib/sam/d/Makefile
+++ b/lib/sam/d/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_samd
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os -Wall -Wextra -I../../../include -fno-common \
 		  -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DSAMD
diff --git a/lib/stm32/can.c b/lib/stm32/can.c
index 37599c9b..f404a4a7 100644
--- a/lib/stm32/can.c
+++ b/lib/stm32/can.c
@@ -464,7 +464,7 @@ void can_fifo_release(uint32_t canport, uint8_t fifo)
 @param[out] fmi Unsigned int8 pointer. ID of the matched filter.
 @param[out] length Unsigned int8 pointer. Length of message payload.
 @param[out] data Unsigned int8[]. Message payload data.
-@param[out] timestamp. Pointer to store the message timestamp.
+@param[out] timestamp Pointer to store the message timestamp.
 			Only valid on time triggered CAN. Use NULL to ignore.
  */
 void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id,
diff --git a/lib/stm32/common/adc_common_f47.c b/lib/stm32/common/adc_common_f47.c
new file mode 100644
index 00000000..50abf2b2
--- /dev/null
+++ b/lib/stm32/common/adc_common_f47.c
@@ -0,0 +1,124 @@
+/** @addtogroup adc_file ADC peripheral API
+@ingroup peripheral_apis
+
+@author @htmlonly &copy; @endhtmlonly 2012
+Ken Sarkies <ksarkies@internode.on.net>
+
+@date 30 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/adc.h>
+
+/**@{*/
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for a Single Channel
+
+The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
+adc_channel
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+ * NOTE Common with f1, f2 and f37x
+*/
+void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
+{
+	uint32_t reg32;
+
+	if (channel < 10) {
+		reg32 = ADC_SMPR2(adc);
+		reg32 &= ~(0x7 << (channel * 3));
+		reg32 |= (time << (channel * 3));
+		ADC_SMPR2(adc) = reg32;
+	} else {
+		reg32 = ADC_SMPR1(adc);
+		reg32 &= ~(0x7 << ((channel - 10) * 3));
+		reg32 |= (time << ((channel - 10) * 3));
+		ADC_SMPR1(adc) = reg32;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set the Sample Time for All Channels
+
+The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same
+for all channels.
+
+@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
+@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
+ * NOTE Common with f1, f2 and f37x
+*/
+void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
+{
+	uint8_t i;
+	uint32_t reg32 = 0;
+
+	for (i = 0; i <= 9; i++) {
+		reg32 |= (time << (i * 3));
+	}
+	ADC_SMPR2(adc) = reg32;
+
+	for (i = 10; i <= 17; i++) {
+		reg32 |= (time << ((i - 10) * 3));
+	}
+	ADC_SMPR1(adc) = reg32;
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Set Dual/Triple Mode
+
+The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave
+arrangement. This setting is applied to ADC1 only.
+
+The various modes possible are described in the reference manual.
+
+@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode
+*/
+void adc_set_multi_mode(uint32_t mode)
+{
+	ADC_CCR |= mode;
+}
+
+
+/** Enable The VBat Sensor.
+ * This enables the battery voltage measurements on ADC1 channel 18. On
+ * STM32F42x and STM32F43x, this must be disabled when the temperature sensor
+ * is enabled. If both are enabled, only the VBat conversion is performed.
+ */
+void adc_enable_vbat_sensor(void)
+{
+	ADC_CCR |= ADC_CCR_VBATE;
+}
+
+/** Disable The VBat Sensor.
+ * Disabling this will reduce power consumption from the battery voltage
+ * measurement.
+ */
+void adc_disable_vbat_sensor(void)
+{
+	ADC_CCR &= ~ADC_CCR_VBATE;
+}
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/f4/adc.c b/lib/stm32/common/adc_common_v1_multi.c
index 020db884..eb368cde 100644
--- a/lib/stm32/f4/adc.c
+++ b/lib/stm32/common/adc_common_v1_multi.c
@@ -14,10 +14,14 @@ registers.  However all the A/D converters share a common clock which is
 prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum
 of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits.
 
-Each A/D converter has up to 19 channels:
-@li On ADC1 the analog channels 16 is internally connected to the temperature
-sensor, channel 17 to V<sub>REFINT</sub>, and channel 18 to V<sub>BAT</sub>.
-@li On ADC2 and ADC3 the analog channels 16 - 18 are not used.
+Each A/D converter has multiple channels, not all of which might be available
+externally.  Internal channels can be used for the the temperature sensor,
+VBat monitoring, and the internal reference voltage VREFINT.  Consult the
+Reference manual for the specifics of your part.
+@sa ADC_MAX_CHANNELS
+@sa ADC_CHANNEL_TEMP
+@sa ADC_CHANNEL_VREF
+@sa ADC_CHANNEL_VBAT
 
 The conversions can occur as a one-off conversion whereby the process stops
 once conversion is complete. The conversions can also be continuous wherein a
@@ -36,7 +40,7 @@ Injected conversions allow a second group of channels to be converted
 separately from the regular group. An interrupt can be set to occur at the end
 of conversion, which occurs after all channels have been scanned.
 
-@section adc_f4_api_ex Basic ADC Handling API.
+@section adc_api_ex Basic ADC Handling API.
 
 Example 1: Simple single channel conversion polled. Enable the peripheral clock
 and ADC, reset ADC and set the prescaler divider. Set the sample time to a
@@ -83,61 +87,6 @@ LGPL License Terms @ref lgpl_license
 
 /**@{*/
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Sample Time for a Single Channel
-
-The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref
-adc_channel
-@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
- * NOTE Common with f1, f2 and f37x
-*/
-
-void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time)
-{
-	uint32_t reg32;
-
-	if (channel < 10) {
-		reg32 = ADC_SMPR2(adc);
-		reg32 &= ~(0x7 << (channel * 3));
-		reg32 |= (time << (channel * 3));
-		ADC_SMPR2(adc) = reg32;
-	} else {
-		reg32 = ADC_SMPR1(adc);
-		reg32 &= ~(0x7 << ((channel - 10) * 3));
-		reg32 |= (time << ((channel - 10) * 3));
-		ADC_SMPR1(adc) = reg32;
-	}
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Set the Sample Time for All Channels
-
-The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same
-for all channels.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
- * NOTE Common with f1, f2 and f37x
-*/
-
-void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
-{
-	uint8_t i;
-	uint32_t reg32 = 0;
-
-	for (i = 0; i <= 9; i++) {
-		reg32 |= (time << (i * 3));
-	}
-	ADC_SMPR2(adc) = reg32;
-
-	for (i = 10; i <= 17; i++) {
-		reg32 |= (time << ((i - 10) * 3));
-	}
-	ADC_SMPR1(adc) = reg32;
-}
 
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Power On
@@ -157,11 +106,9 @@ void adc_power_on(uint32_t adc)
 
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Set Clock Prescale
-
-The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
-
-@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
-adc_ccr_adcpre
+The ADC clock can be prescaled.
+The Clock sources and scaler values are part specific.
+@param[in] prescale  Prescale value for ADC Clock @ref adc_ccr_adcpre
 */
 
 void adc_set_clk_prescale(uint32_t prescale)
@@ -171,22 +118,6 @@ void adc_set_clk_prescale(uint32_t prescale)
 }
 
 /*---------------------------------------------------------------------------*/
-/** @brief ADC Set Dual/Triple Mode
-
-The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave
-arrangement. This setting is applied to ADC1 only.
-
-The various modes possible are described in the reference manual.
-
-@param[in] mode Unsigned int32. Multiple mode selection from @ref adc_multi_mode
-*/
-
-void adc_set_multi_mode(uint32_t mode)
-{
-	ADC_CCR |= mode;
-}
-
-/*---------------------------------------------------------------------------*/
 /** @brief ADC Enable an External Trigger for Regular Channels
 
 This enables an external trigger for set of defined regular channels, and sets
@@ -403,8 +334,8 @@ bool adc_awd(uint32_t adc)
 /*---------------------------------------------------------------------------*/
 /** @brief ADC Enable The Temperature Sensor
 
-This enables both the sensor and the reference voltage measurements on ADC1
-channels 16 and 17. On STM32F42x and STM32F43x, the temperature sensor is
+This enables both the sensor and the reference voltage measurements on ADC1.
+On STM32F42x and STM32F43x, the temperature sensor is
 connected to ADC1 channel 18, the same as VBat. If both are enabled, only the
 VBat conversion is performed.
 */
@@ -426,23 +357,4 @@ void adc_disable_temperature_sensor(void)
 	ADC_CCR &= ~ADC_CCR_TSVREFE;
 }
 
-/** Enable The VBat Sensor.
- * This enables the battery voltage measurements on ADC1 channel 18. On
- * STM32F42x and STM32F43x, this must be disabled when the temperature sensor
- * is enabled. If both are enabled, only the VBat conversion is performed.
- */
-void adc_enable_vbat_sensor(void)
-{
-	ADC_CCR |= ADC_CCR_VBATE;
-}
-
-/** Disable The VBat Sensor.
- * Disabling this will reduce power consumption from the battery voltage
- * measurement.
- */
-void adc_disable_vbat_sensor(void)
-{
-	ADC_CCR &= ~ADC_CCR_VBATE;
-}
-
 /**@}*/
diff --git a/lib/stm32/common/adc_common_v2.c b/lib/stm32/common/adc_common_v2.c
index fb22d273..7fd26476 100644
--- a/lib/stm32/common/adc_common_v2.c
+++ b/lib/stm32/common/adc_common_v2.c
@@ -155,7 +155,7 @@ void adc_power_off(uint32_t adc)
  */
 void adc_calibrate_async(uint32_t adc)
 {
-	ADC_CR(adc) = ADC_CR_ADCAL;
+	ADC_CR(adc) |= ADC_CR_ADCAL;
 }
 
 /**
@@ -389,4 +389,24 @@ void adc_start_conversion_regular(uint32_t adc)
 	ADC_CR(adc) |= ADC_CR_ADSTART;
 }
 
+/** @brief Enable circular mode for DMA transfers
+ *
+ * For this to work it needs to be ebabled on the DMA side as well.
+ *
+ * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
+ */
+void adc_enable_dma_circular_mode(uint32_t adc)
+{
+	ADC_CFGR1(adc) |= ADC_CFGR1_DMACFG;
+}
+
+/** @brief Disable circular mode for DMA transfers
+ *
+ * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
+ */
+void adc_disable_dma_circular_mode(uint32_t adc)
+{
+	ADC_CFGR1(adc) &= ~ADC_CFGR1_DMACFG;
+}
+
 /**@}*/
diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c
index a8a0daf8..5d1893c1 100644
--- a/lib/stm32/common/dac_common_all.c
+++ b/lib/stm32/common/dac_common_all.c
@@ -1,12 +1,13 @@
-/** @addtogroup dac_file
+/** @addtogroup dac_file DAC peripheral API
+ * @ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
 
 This library supports the Digital to Analog Conversion System in the
-STM32F series of ARM Cortex Microcontrollers by ST Microelectronics.
+STM32 series of ARM Cortex Microcontrollers by ST Microelectronics.
 
-The DAC is present only in a limited set of devices, notably some
-of the connection line, high density and XL devices.
+The DAC peripheral found on many of the devices in the STM32 lineup,
+sometimes with only one channel, but normally with two channels.
 
 Two DAC channels are available, however unlike the ADC channels these
 are separate DAC devices controlled by the same register block.
diff --git a/lib/stm32/f3/timer.c b/lib/stm32/common/dma2d_common_f47.c
index 0e9ac3d4..013292a0 100644
--- a/lib/stm32/f3/timer.c
+++ b/lib/stm32/common/dma2d_common_f47.c
@@ -1,16 +1,14 @@
-/** @defgroup timer_file TIMER
+/** @defgroup dma2d_file DMA2D peripheral API
  *
- * @ingroup STM32F3xx
- *
- * @brief <b>libopencm3 STM32F3xx Timers</b>
+ * @ingroup peripheral_apis
  *
  * @version 1.0.0
  *
- * @date 11 July 2013
+ * This library supports the DMA2D Peripheral in the STM32F4xx and STM32F7xx
+ * series of ARM Cortex Microcontrollers by ST Microelectronics.
  *
  * LGPL License Terms @ref lgpl_license
  */
-
 /*
  * This file is part of the libopencm3 project.
  *
@@ -28,6 +26,8 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <libopencm3/stm32/timer.h>
+#include <libopencm3/stm32/common/dma2d_common_f47.h>
 
+/**@{*/
 
+/**@}*/
diff --git a/lib/stm32/common/dma_common_csel.c b/lib/stm32/common/dma_common_csel.c
new file mode 100644
index 00000000..4cf1fca9
--- /dev/null
+++ b/lib/stm32/common/dma_common_csel.c
@@ -0,0 +1,46 @@
+/** @addtogroup dma_file DMA peripheral API
+@ingroup peripheral_apis
+
+LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/dma.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief DMA Channel Set Request Selection
+
+Set DMA request mapping selection for given channel. Refer to datasheet for channel
+request mapping tables.
+
+@param[in] dma DMA controller base address: DMA1 or DMA2
+@param[in] channel Channel number:  1-7 for DMA1 or 1-5 for DMA2
+@param[in] request DMA request mapping.
+*/
+
+void dma_set_channel_request(uint32_t dma, uint8_t channel, uint8_t request)
+{
+	uint32_t reg32 = DMA_CSELR(dma) & ~(DMA_CSELR_CxS_MASK << DMA_CSELR_CxS_SHIFT(channel));
+	DMA_CSELR(dma) = reg32 | ((DMA_CSELR_CxS_MASK & request) << DMA_CSELR_CxS_SHIFT(channel));
+}
+
+/**@}*/
diff --git a/lib/stm32/common/dma_common_f24.c b/lib/stm32/common/dma_common_f24.c
index d706674f..2c61b548 100644
--- a/lib/stm32/common/dma_common_f24.c
+++ b/lib/stm32/common/dma_common_f24.c
@@ -1,4 +1,5 @@
-/** @addtogroup dma_file
+/** @addtogroup dma_file DMA peripheral API
+@ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2012
 Ken Sarkies <ksarkies@internode.on.net>
diff --git a/lib/stm32/common/dma_common_l1f013.c b/lib/stm32/common/dma_common_l1f013.c
index 47abfa24..2f9190a4 100644
--- a/lib/stm32/common/dma_common_l1f013.c
+++ b/lib/stm32/common/dma_common_l1f013.c
@@ -1,4 +1,5 @@
-/** @addtogroup dma_file
+/** @addtogroup dma_file DMA peripheral API
+@ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
 
diff --git a/lib/stm32/f0/pwr.c b/lib/stm32/common/dsi_common_f47.c
index 8a3ffd2e..17d875d7 100644
--- a/lib/stm32/f0/pwr.c
+++ b/lib/stm32/common/dsi_common_f47.c
@@ -1,15 +1,12 @@
-/** @defgroup pwr_file PWR
+/** @defgroup dsi_file DSI peripheral API
  *
- * @ingroup STM32F0xx
- *
- * @brief <b>libopencm3 STM32F0xx Power Control</b>
+ * @ingroup peripheral_apis
  *
  * @version 1.0.0
  *
- * @date 11 July 2013
- *
- * This library supports the power control system for the
- * STM32F0 series of ARM Cortex Microcontrollers by ST Microelectronics.
+ * This library supports the Display Serial Interface Host and Wrapper in
+ * the STM32F4xx and STM32F7xx series of ARM Cortex Microcontrollers by
+ * ST Microelectronics.
  *
  * LGPL License Terms @ref lgpl_license
  */
@@ -30,9 +27,8 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/**@{*/
+#include <libopencm3/stm32/common/dsi_common_f47.h>
 
-#include <libopencm3/stm32/pwr.h>
+/**@{*/
 
 /**@}*/
-
diff --git a/lib/stm32/common/exti_common_all.c b/lib/stm32/common/exti_common_all.c
index d2135f29..7135a964 100644
--- a/lib/stm32/common/exti_common_all.c
+++ b/lib/stm32/common/exti_common_all.c
@@ -1,3 +1,6 @@
+/** @addtogroup exti_file EXTI peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -17,7 +20,7 @@
  * You should have received a copy of the GNU Lesser General Public License
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  *
- * This provides the code for the "next gen" EXTI block provided in F2/F4/L1
+ * This provides the code for the "next gen" EXTI block provided in F2/F4/F7/L1
  * devices.  (differences only in the source selection)
  */
 /**@{*/
@@ -25,8 +28,17 @@
 
 #include <libopencm3/stm32/exti.h>
 #include <libopencm3/stm32/gpio.h>
-#if !defined(AFIO_BASE)
-#       include <libopencm3/stm32/syscfg.h>
+
+#if defined(EXTI_EXTICR)
+	#define EXTICR_SELECTION_FIELDSIZE	EXTI_EXTICR_FIELDSIZE
+	#define EXTICR_SELECTION_REG(x)	EXTI_EXTICR(x)
+#elif defined(AFIO_EXTICR)
+	#define EXTICR_SELECTION_FIELDSIZE	AFIO_EXTICR_FIELDSIZE
+	#define EXTICR_SELECTION_REG(x)	AFIO_EXTICR(x)
+#else
+	#include <libopencm3/stm32/syscfg.h>
+	#define EXTICR_SELECTION_FIELDSIZE	SYSCFG_EXTICR_FIELDSIZE
+	#define EXTICR_SELECTION_REG(x)	SYSCFG_EXTICR(x)
 #endif
 
 void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig)
@@ -71,7 +83,12 @@ void exti_disable_request(uint32_t extis)
  */
 void exti_reset_request(uint32_t extis)
 {
+#if defined(EXTI_RPR1) && defined(EXTI_FPR1)
+	EXTI_RPR1 = extis;
+	EXTI_FPR1 = extis;
+#else
 	EXTI_PR = extis;
+#endif
 }
 
 /*
@@ -79,7 +96,11 @@ void exti_reset_request(uint32_t extis)
  * */
 uint32_t exti_get_flag_status(uint32_t exti)
 {
+#if defined(EXTI_RPR1) && defined(EXTI_FPR1)
+	return (EXTI_RPR1 & exti) | (EXTI_FPR1 & exti);
+#else
 	return EXTI_PR & exti;
+#endif
 }
 
 /*
@@ -96,7 +117,7 @@ void exti_select_source(uint32_t exti, uint32_t gpioport)
 			continue;
 		}
 
-		uint32_t bits = 0, mask = 0x0F;
+		uint32_t bits = 0;
 
 		switch (gpioport) {
 		case GPIOA:
@@ -148,16 +169,11 @@ void exti_select_source(uint32_t exti, uint32_t gpioport)
 #endif
 		}
 
-		uint8_t shift = (uint8_t)(4 * (line % 4));
+		uint8_t shift = (uint8_t)(EXTICR_SELECTION_FIELDSIZE * (line % 4));
+		uint32_t mask = ((1 << EXTICR_SELECTION_FIELDSIZE) - 1) << shift;
 		uint32_t reg = line / 4;
-		bits <<= shift;
-		mask <<= shift;
 
-#if defined(AFIO_BASE)
-		AFIO_EXTICR(reg) = (AFIO_EXTICR(reg) & ~mask) | bits;
-#else
-		SYSCFG_EXTICR(reg) = (SYSCFG_EXTICR(reg) & ~mask) | bits;
-#endif
+		EXTICR_SELECTION_REG(reg) = (EXTICR_SELECTION_REG(reg) & ~mask) | (bits << shift);
 	};
 }
 /**@}*/
diff --git a/lib/stm32/common/flash_common_all.c b/lib/stm32/common/flash_common_all.c
index 98821796..b369d903 100644
--- a/lib/stm32/common/flash_common_all.c
+++ b/lib/stm32/common/flash_common_all.c
@@ -1,5 +1,5 @@
-/** @addtogroup flash_file
- *
+/** @addtogroup flash_file FLASH peripheral API
+ * @ingroup peripheral_apis
  */
 
 /*
diff --git a/lib/stm32/common/flash_common_f.c b/lib/stm32/common/flash_common_f.c
index 291fad9b..0b867def 100644
--- a/lib/stm32/common/flash_common_f.c
+++ b/lib/stm32/common/flash_common_f.c
@@ -43,3 +43,4 @@ void flash_clear_eop_flag(void)
 	FLASH_SR |= FLASH_SR_EOP;
 }
 
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/common/flash_common_idcache.c b/lib/stm32/common/flash_common_idcache.c
index ebfdd0ad..c7da2066 100644
--- a/lib/stm32/common/flash_common_idcache.c
+++ b/lib/stm32/common/flash_common_idcache.c
@@ -55,4 +55,5 @@ void flash_icache_reset(void)
 	FLASH_ACR |= FLASH_ACR_ICRST;
 }
 
+/**@}*/
 
diff --git a/lib/stm32/common/flash_common_l01.c b/lib/stm32/common/flash_common_l01.c
index 9eceb45f..9fb1212b 100644
--- a/lib/stm32/common/flash_common_l01.c
+++ b/lib/stm32/common/flash_common_l01.c
@@ -89,6 +89,14 @@ void flash_lock(void)
 	flash_lock_pecr();
 }
 
+/** @brief Unlock RUN_PD bit from FLASH_ACR register.
+ */
+void flash_unlock_acr(void)
+{
+	FLASH_PDKEYR = FLASH_PDKEYR_PDKEY1;
+	FLASH_PDKEYR = FLASH_PDKEYR_PDKEY2;
+}
+
 /** @brief Write a word to eeprom
  *
  * @param address assumed to be in the eeprom space, no checking
diff --git a/lib/stm32/f4/fmc.c b/lib/stm32/common/fmc_common_f47.c
index 1c30dd67..1a5bc027 100644
--- a/lib/stm32/f4/fmc.c
+++ b/lib/stm32/common/fmc_common_f47.c
@@ -1,3 +1,11 @@
+/** @addtogroup fmc_file FMC peripheral API
+@ingroup peripheral_apis
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
+This library supports the Flexible Memory Controller in the STM32F4xx and
+STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
+*/
 /*
  *
  * This file is part of the libopencm3 project.
@@ -21,6 +29,8 @@
 #include <stdint.h>
 #include <libopencm3/stm32/fsmc.h>
 
+/**@{*/
+
 /*
  * Install various timing values into the correct place in the
  * SDRAM Timing Control Register format.
@@ -97,3 +107,5 @@ sdram_command(enum fmc_sdram_bank bank,
 	/* Send the next command */
 	FMC_SDCMR = tmp_reg;
 }
+
+/**@}*/
diff --git a/lib/stm32/common/gpio_common_all.c b/lib/stm32/common/gpio_common_all.c
index 98d15ad4..9602a999 100644
--- a/lib/stm32/common/gpio_common_all.c
+++ b/lib/stm32/common/gpio_common_all.c
@@ -1,4 +1,5 @@
-/** @addtogroup gpio_file
+/** @addtogroup gpio_file GPIO peripheral API
+ * @ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
 
diff --git a/lib/stm32/common/hash_common_f24.c b/lib/stm32/common/hash_common_f24.c
index 24d489c1..b5046dd8 100644
--- a/lib/stm32/common/hash_common_f24.c
+++ b/lib/stm32/common/hash_common_f24.c
@@ -1,4 +1,6 @@
-/** @addtogroup hash_file
+/** @addtogroup hash_file HASH Peripheral API
+ *
+ * @ingroup peripheral_apis
  *
  * @author @htmlonly &copy; @endhtmlonly 2013
  * Mikhail Avkhimenia <mikhail@avkhimenia.net>
@@ -145,7 +147,6 @@ void hash_digest()
 Makes a copy of the resulting hash.
 
 @param[out] data unsigned int32. Hash 4\5 words long depending on the algorithm.
-@param[in] algorithm unsigned int8. Hash algorithm: @ref hash_algorithm
 */
 
 void hash_get_result(uint32_t *data)
diff --git a/lib/stm32/common/iwdg_common_all.c b/lib/stm32/common/iwdg_common_all.c
index f2b1c1d8..44b3b9b3 100644
--- a/lib/stm32/common/iwdg_common_all.c
+++ b/lib/stm32/common/iwdg_common_all.c
@@ -70,45 +70,44 @@ loading a previous value.
 @param[in] period uint32_t Period in milliseconds (< 32760) from a watchdog
 reset until a system reset is issued.
 */
-
 void iwdg_set_period_ms(uint32_t period)
 {
-	uint32_t count, prescale, reload, exponent;
-
-	/* Set the count to represent ticks of the 32kHz LSI clock */
-	count = (period << 5);
-
-	/* Strip off the first 12 bits to get the prescale value required */
-	prescale = (count >> 12);
-	if (prescale > 256) {
-		exponent = IWDG_PR_DIV256; reload = COUNT_MASK;
-	} else if (prescale > 128) {
-		exponent = IWDG_PR_DIV256; reload = (count >> 8);
-	} else if (prescale > 64) {
-		exponent = IWDG_PR_DIV128; reload = (count >> 7);
-	} else if (prescale > 32) {
-		exponent = IWDG_PR_DIV64;  reload = (count >> 6);
-	} else if (prescale > 16) {
-		exponent = IWDG_PR_DIV32;  reload = (count >> 5);
-	} else if (prescale > 8) {
-		exponent = IWDG_PR_DIV16;  reload = (count >> 4);
-	} else if (prescale > 4) {
-		exponent = IWDG_PR_DIV8;   reload = (count >> 3);
-	} else {
-		exponent = IWDG_PR_DIV4;   reload = (count >> 2);
-	}
+	const int PRESCALER_MAX = 6;
+	uint8_t prescale = 0;
 
-	/* Avoid the undefined situation of a zero count */
+	/* Set the count to represent ticks of 8kHz clock (the 32kHz LSI clock
+	 * divided by 4 = lowest prescaler setting)
+	 */
+	uint32_t count = period << 3;
+
+	/* Prevent underflow */
 	if (count == 0) {
 		count = 1;
 	}
 
+	/* Shift count while increasing prescaler as many times as needed to
+	 * fit into IWDG_RLR
+	 */
+	while ((count - 1) >> COUNT_LENGTH) {
+		count >>= 1;
+		prescale++;
+	}
+
+	/* IWDG_RLR actually holds count - 1 */
+	count--;
+
+	/* Clamp to max possible period */
+	if (prescale > PRESCALER_MAX) {
+		count = COUNT_MASK;
+		prescale = PRESCALER_MAX;
+	}
+
 	while (iwdg_prescaler_busy());
 	IWDG_KR = IWDG_KR_UNLOCK;
-	IWDG_PR = exponent;
+	IWDG_PR = prescale;
 	while (iwdg_reload_busy());
 	IWDG_KR = IWDG_KR_UNLOCK;
-	IWDG_RLR = (reload & COUNT_MASK);
+	IWDG_RLR = count & COUNT_MASK;
 }
 
 /*---------------------------------------------------------------------------*/
diff --git a/lib/stm32/common/lptimer_common_all.c b/lib/stm32/common/lptimer_common_all.c
new file mode 100644
index 00000000..1dc4e0ab
--- /dev/null
+++ b/lib/stm32/common/lptimer_common_all.c
@@ -0,0 +1,294 @@
+/** @addtogroup lptimer_file LPTIM peripheral API
+ * @ingroup peripheral_apis
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * @date 2 July 2019
+ *
+ * LGPL License Terms @ref lgpl_license
+ *
+ * @section lptim_api_ex Basic LPTIMER handling API.
+ *
+ * Example: LPTIM1 with 2x clock prescaler, from internal clock (LSE), irq on match and reload.
+ *
+ * @code
+ *
+ *	rcc_set_peripheral_clk_sel(LPTIM1, RCC_CCIPR_LPTIM1SEL_LSE);
+ *
+ *	rcc_periph_clock_enable(RCC_LPTIM1);
+ *
+ *	lptimer_set_internal_clock_source(LPTIM1);
+ *	lptimer_enable_trigger(LPTIM1, LPTIM_CFGR_TRIGEN_SW);
+ *	lptimer_set_prescaler(LPTIM1, LPTIM_CFGR_PRESC_2);
+ *
+ *	lptimer_enable(LPTIM1);
+ *
+ *	lptimer_set_period(LPTIM1, 0xffff);
+ *	lptimer_set_compare(LPTIM1, 1234);
+ *
+ *	lptimer_enable_irq(LPTIM1, LPTIM_IER_ARRMIE | LPTIM_IER_CMPMIE);
+ *	nvic_enable_irq(NVIC_LPTIM1_IRQ);
+ *
+ *	lptimer_start_counter(LPTIM1, LPTIM_CR_CNTSTRT);
+ *
+ * @endcode
+ *
+ * Note: LPTIM internal clock source selection is device specific, see clock tree
+ * and rcc section of reference manual.
+ *
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/lptimer.h>
+
+/** @brief Set lptimer Counter
+ *
+ * Set the value of a lptimer counter.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] count Counter value.
+*/
+void lptimer_set_counter(uint32_t lptimer_peripheral, uint16_t count)
+{
+	LPTIM_CNT(lptimer_peripheral) = count;
+}
+
+/** @brief Read lptimer Counter
+ *
+ * Read back the value of lptimer counter.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @returns Counter value.
+ */
+uint16_t lptimer_get_counter(uint32_t lptimer_peripheral)
+{
+	return LPTIM_CNT(lptimer_peripheral);
+}
+
+/** @brief Clear lptimer Status Flag.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] flag Status Register clear flag (@ref lptim_icr)
+ */
+void lptimer_clear_flag(uint32_t lptimer_peripheral, uint32_t flag)
+{
+	LPTIM_ICR(lptimer_peripheral) = flag;
+}
+
+/** @brief Read lptimer Status Flag.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] flag Status Register flag (@ref lptim_isr)
+ * @returns flag set.
+ */
+bool lptimer_get_flag(uint32_t lptimer_peripheral, uint32_t flag)
+{
+	return (LPTIM_ISR(lptimer_peripheral) & flag);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable lptimer interrupts.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] irq Logical or of all interrupt enable bits to be set (@ref lptim_ier)
+ */
+void lptimer_enable_irq(uint32_t lptimer_peripheral, uint32_t irq)
+{
+	LPTIM_IER(lptimer_peripheral) |= irq;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable lptimer Interrupts.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] irq Logical or of all interrupt enable bits to be cleared (@ref lptim_ier)
+ */
+void lptimer_disable_irq(uint32_t lptimer_peripheral, uint32_t irq)
+{
+	LPTIM_IER(lptimer_peripheral) &= ~irq;
+}
+
+/** @brief Enable lptimer.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_enable(uint32_t lptimer_peripheral)
+{
+	LPTIM_CR(lptimer_peripheral) |= LPTIM_CR_ENABLE;
+}
+
+/** @brief Disable lptimer.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_disable(uint32_t lptimer_peripheral)
+{
+	LPTIM_CR(lptimer_peripheral) &= ~LPTIM_CR_ENABLE;
+}
+
+/** @brief Start lptimer in a given mode.
+ *
+ * Starts the timer in specified mode - Either Single (@ref LPTIM_CR_SNGSTRT) or
+ * Continuous mode (@ref LPTIM_CR_CNTSTRT). In Single mode, the timer will stop at
+ * next match on compare or period value.
+ * If LPTIM_CR_SNGSTRT is set while timer is started in countious mode, it
+ * will stop at next match on compare or period value.
+ * If Software trigger is disabled, start will be delayed until programmed
+ * triggers is detected.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] mode lptimer start mode (@ref LPTIM_CR_SNGSTRT or @ref LPTIM_CR_CNTSTRT)
+ */
+void lptimer_start_counter(uint32_t lptimer_peripheral, uint32_t mode)
+{
+	LPTIM_CR(lptimer_peripheral) |= mode;
+}
+
+/** @brief Set lptimer clock prescaler.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] prescaler Clock prescaler (@ref lptim_cfgr_presc)
+ */
+void lptimer_set_prescaler(uint32_t lptimer_peripheral, uint32_t prescaler)
+{
+	uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral);
+	reg32 &= ~(LPTIM_CFGR_PRESC_MASK << LPTIM_CFGR_PRESC_SHIFT);
+	LPTIM_CFGR(lptimer_peripheral) = reg32 | prescaler;
+}
+
+/** @brief Enable lptimer External Trigger
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel)
+ */
+void lptimer_enable_trigger(uint32_t lptimer_peripheral, uint32_t trigen)
+{
+	uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral);
+	reg32 &= ~(LPTIM_CFGR_TRIGEN_MASK << LPTIM_CFGR_TRIGEN_SHIFT);
+	LPTIM_CFGR(lptimer_peripheral) = reg32 | trigen;
+}
+
+/** @brief Select lptimer Trigger Source
+ *
+ * Select timer external trigger source.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] trigger Trigger selector (@ref lptim_cfgr_trigsel)
+ */
+void lptimer_select_trigger_source(uint32_t lptimer_peripheral, uint32_t trigger_source)
+{
+	uint32_t reg32 = LPTIM_CFGR(lptimer_peripheral);
+	reg32 &= ~(LPTIM_CFGR_TRIGSEL_MASK << LPTIM_CFGR_TRIGSEL_SHIFT);
+	LPTIM_CFGR(lptimer_peripheral) = reg32 | trigger_source;
+}
+
+/** @brief Set lptimer counter Compare Value
+ *
+ * Set the timer compare value. Must only be set with timer enabled.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] compare_value Compare value.
+ */
+void lptimer_set_compare(uint32_t lptimer_peripheral, uint16_t compare_value)
+{
+	LPTIM_CMP(lptimer_peripheral) = compare_value;
+}
+
+/** @brief Set lptimer period
+ *
+ * Set the timer period in the auto-reload register. Must only be set with timer
+ * enabled.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ * @param[in] period_value Autoreload value. Must be greater that CMP value.
+ */
+void lptimer_set_period(uint32_t lptimer_peripheral, uint16_t period_value)
+{
+	LPTIM_ARR(lptimer_peripheral) = period_value;
+}
+
+/** @brief Enable lptimer Preload mode.
+ *
+ * Enable lptimer preload mode, delaying update of period and compare registers
+ * to the end of current period.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_enable_preload(uint32_t lptimer_peripheral)
+{
+	LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_PRELOAD;
+}
+
+/** @brief Disable lptimer Preload mode.
+ *
+ * Disable lptimer preload mode, ensureing updated period and compare registers
+ * values are taken in account immediatly.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_disable_preload(uint32_t lptimer_peripheral)
+{
+	LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_PRELOAD;
+}
+
+
+/** @brief Set lptimer Internal Clock source
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_set_internal_clock_source(uint32_t lptimer_peripheral)
+{
+	LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_CKSEL;
+}
+
+/** @brief Set lptimer External Clock source
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_set_external_clock_source(uint32_t lptimer_peripheral)
+{
+	LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_CKSEL;
+}
+
+/** @brief Set lptimer Waveform Output Polarity High
+ *
+ * Set lptimer waveform output to reflect compare result between LPTIN_CNT
+ * and LPTIM_CMP.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_set_waveform_polarity_high(uint32_t lptimer_peripheral)
+{
+	LPTIM_CFGR(lptimer_peripheral) |= LPTIM_CFGR_WAVPOL;
+}
+
+/** @brief Set lptimer Waveform Output Polarity Low
+ *
+ * Set lptimer waveform output to reflect the inverse of the compare result
+ * between LPTIN_CNT and LPTIM_CMP.
+ *
+ * @param[in] lptimer_peripheral lptimer base address (@ref lptim_reg_base)
+ */
+void lptimer_set_waveform_polarity_low(uint32_t lptimer_peripheral)
+{
+	LPTIM_CFGR(lptimer_peripheral) &= ~LPTIM_CFGR_WAVPOL;
+}
+
+/**@}*/
diff --git a/lib/stm32/f4/ltdc.c b/lib/stm32/common/ltdc_common_f47.c
index 83a13961..3255f356 100644
--- a/lib/stm32/f4/ltdc.c
+++ b/lib/stm32/common/ltdc_common_f47.c
@@ -1,8 +1,6 @@
-/** @defgroup ltdc_file LTDC
+/** @defgroup ltdc_file LTDC peripheral API
  *
- * @ingroup STM32F4xx
- *
- * @brief <b>libopencm3 STM32F4xx LTDC</b>
+ * @ingroup peripheral_apis
  *
  * @version 1.0.0
  *
@@ -11,12 +9,8 @@
  *
  * @date 5 December 2014
  *
- * This library supports the LCD controller (LTDC) in the STM32F4
- * series of ARM Cortex Microcontrollers by ST Microelectronics.
- *
- * For the STM32F4xx, LTDC is described in LCD-TFT Controller (LTDC)
- * section 16 of the STM32F4xx Reference Manual (RM0090,Rev8).
- *
+ * This library supports the LCD controller (LTDC) in the STM32F4xx and
+ * STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
  *
  * LGPL License Terms @ref lgpl_license
  */
@@ -40,7 +34,9 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <libopencm3/stm32/f4/ltdc.h>
+/**@{*/
+
+#include <libopencm3/stm32/common/ltdc_common_f47.h>
 
 void ltdc_set_tft_sync_timings(uint16_t sync_width,    uint16_t sync_height,
 			       uint16_t h_back_porch,  uint16_t v_back_porch,
@@ -87,3 +83,5 @@ void ltdc_setup_windowing(uint8_t  layer_number,
 				     (v_back_porch << 0);
 }
 
+/**@}*/
+
diff --git a/lib/stm32/common/pwr_common_v1.c b/lib/stm32/common/pwr_common_v1.c
index 820dfcab..d4c44b3d 100644
--- a/lib/stm32/common/pwr_common_v1.c
+++ b/lib/stm32/common/pwr_common_v1.c
@@ -1,4 +1,5 @@
-/** @addtogroup pwr_file
+/** @addtogroup pwr_file PWR peripheral API
+@ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2012
 Ken Sarkies <ksarkies@internode.on.net>
diff --git a/lib/stm32/common/pwr_common_v2.c b/lib/stm32/common/pwr_common_v2.c
index b895e7d0..940b29e5 100644
--- a/lib/stm32/common/pwr_common_v2.c
+++ b/lib/stm32/common/pwr_common_v2.c
@@ -1,4 +1,5 @@
-/** @addtogroup pwr_file
+/** @addtogroup pwr_file PWR peripheral API
+ * @ingroup peripheral_apis
  *
  * @author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
  */
diff --git a/lib/stm32/common/rcc_common_all.c b/lib/stm32/common/rcc_common_all.c
index e338dcea..5852b675 100644
--- a/lib/stm32/common/rcc_common_all.c
+++ b/lib/stm32/common/rcc_common_all.c
@@ -1,3 +1,6 @@
+/** @addtogroup rcc_file RCC peripheral API
+ * @ingroup peripheral_apis
+ */
 /*
  * This file is part of the libopencm3 project.
  *
diff --git a/lib/stm32/common/rng_common_v1.c b/lib/stm32/common/rng_common_v1.c
index 7ed1e635..e26b6880 100644
--- a/lib/stm32/common/rng_common_v1.c
+++ b/lib/stm32/common/rng_common_v1.c
@@ -1,7 +1,10 @@
-/** @addtogroup rng_file
+/** @addtogroup rng_file RNG peripheral API
+ * @ingroup peripheral_apis
  *
- * This library supports the random number generator peripheral (RNG) in the
- * STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics.
+ * This library supports "version 1" of the random number generator
+ * peripheral (RNG) in the STM32 series of ARM Cortex Microcontrollers
+ * by ST Microelectronics.  This is a common peripheral available on multiple
+ * devices in the family.
  *
  * LGPL License Terms @ref lgpl_license
  */
@@ -44,7 +47,7 @@ void rng_enable(void)
 /** Randomizes a number (non-blocking).
  * Can fail if a clock error or seed error is detected. Consult the Reference
  * Manual, but "try again", potentially after resetting the peripheral
- * @param pointer to a uint32_t that will be randomized.
+ * @param rand_nr pointer to a uint32_t that will be randomized.
  * @returns true on success, pointer is only written to on success
  * @sa rng_get_random_blocking
  */
diff --git a/lib/stm32/common/rtc_common_l1f024.c b/lib/stm32/common/rtc_common_l1f024.c
index 7579dfdc..d7825a7c 100644
--- a/lib/stm32/common/rtc_common_l1f024.c
+++ b/lib/stm32/common/rtc_common_l1f024.c
@@ -1,4 +1,5 @@
-/** @addtogroup rtc_file
+/** @addtogroup rtc_file RTC peripheral API
+@ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
 
@@ -106,6 +107,7 @@ void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel)
 	 *    down-counting.
 	 */
 	RTC_WUTR = wkup_time;
+	RTC_CR &= ~(RTC_CR_WUCLKSEL_MASK << RTC_CR_WUCLKSEL_SHIFT);
 	RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT);
 	RTC_CR |= RTC_CR_WUTE;
 }
diff --git a/lib/stm32/common/st_usbfs_core.c b/lib/stm32/common/st_usbfs_core.c
index a4ab414a..0dba875b 100644
--- a/lib/stm32/common/st_usbfs_core.c
+++ b/lib/stm32/common/st_usbfs_core.c
@@ -40,6 +40,7 @@ void st_usbfs_set_address(usbd_device *dev, uint8_t addr)
 /**
  * Set the receive buffer size for a given USB endpoint.
  *
+ * @param dev the usb device handle returned from @ref usbd_init
  * @param ep Index of endpoint to configure.
  * @param size Size in bytes of the RX buffer. Legal sizes : {2,4,6...62}; {64,96,128...992}.
  * @returns (uint16) Actual size set
diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c
index 9c8b5cc6..64701836 100644
--- a/lib/stm32/common/timer_common_all.c
+++ b/lib/stm32/common/timer_common_all.c
@@ -1,4 +1,5 @@
-/** @addtogroup timer_file
+/** @addtogroup timer_file TIMER peripheral API
+@ingroup peripheral_apis
 
 @author @htmlonly &copy; @endhtmlonly 2010
 Edward Cheeseman <evbuilder@users.sourceforge.org>
diff --git a/lib/stm32/common/timer_common_f24.c b/lib/stm32/common/timer_common_f24.c
index ce1c1e38..8368c38a 100644
--- a/lib/stm32/common/timer_common_f24.c
+++ b/lib/stm32/common/timer_common_f24.c
@@ -33,8 +33,7 @@ Set timer options register on TIM2 or TIM5, used for trigger remapping on TIM2,
 and similarly for TIM5 for oscillator calibration purposes.
 
 @param[in] timer_peripheral Unsigned int32. Timer register address base
-@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5:
-@ref tim5_opt_trigger_remap.
+@param option flags TIM2 @ref tim2_opt_trigger_remap or TIM5 @ref tim5_opt_trigger_remap
 */
 
 void timer_set_option(uint32_t timer_peripheral, uint32_t option)
diff --git a/lib/stm32/f0/Makefile b/lib/stm32/f0/Makefile
index a5883643..6d832a57 100644
--- a/lib/stm32/f0/Makefile
+++ b/lib/stm32/f0/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_stm32f0
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -36,24 +34,28 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 
 ARFLAGS		= rcs
 
-OBJS		= can.o flash.o rcc.o dma.o rtc.o comparator.o \
-                  dac.o pwr.o gpio.o timer.o adc.o desig.o
-
-OBJS            += gpio_common_all.o gpio_common_f0234.o crc_common_all.o crc_v2.o \
-                   pwr_common_v1.o iwdg_common_all.o rtc_common_l1f024.o \
-                   dma_common_l1f013.o exti_common_all.o \
-                   dac_common_all.o \
-                   timer_common_all.o timer_common_f0234.o rcc_common_all.o
-
-OBJS		+= adc_common_v2.o
-OBJS		+= crs_common_all.o
-OBJS		+= flash_common_all.o flash_common_f.o flash_common_f01.o
-OBJS		+= usart_common_all.o usart_common_v2.o
-OBJS		+= i2c_common_v2.o
-OBJS		+= spi_common_all.o spi_common_v2.o
-
-OBJS		+= usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS		+= st_usbfs_core.o st_usbfs_v2.o
+OBJS += adc.o adc_common_v2.o
+OBJS += can.o
+OBJS += comparator.o
+OBJS += crc_common_all.o crc_v2.o
+OBJS += crs_common_all.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_l1f013.o dma_common_csel.o
+OBJS += exti_common_all.o
+OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += iwdg_common_all.o
+OBJS += i2c_common_v2.o
+OBJS += pwr_common_v1.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rtc_common_l1f024.o
+OBJS += spi_common_all.o spi_common_v2.o
+OBJS += timer_common_all.o timer_common_f0234.o
+OBJS += usart_common_all.o usart_common_v2.o
+
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += st_usbfs_core.o st_usbfs_v2.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/stm32/f0/adc.c b/lib/stm32/f0/adc.c
index 2302582a..663099dd 100644
--- a/lib/stm32/f0/adc.c
+++ b/lib/stm32/f0/adc.c
@@ -117,7 +117,7 @@ void adc_disable_discontinuous_mode(uint32_t adc)
  * @par
  *
  * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
- * @param[in] adc ::adc_opmode. ADC operation mode (@ref adc_opmode)
+ * @param[in] opmode ADC operation mode
  */
 
 void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode)
@@ -277,6 +277,16 @@ bool adc_get_eoc_sequence_flag(uint32_t adc)
 	return ADC_ISR(adc) & ADC_ISR_EOSEQ;
 }
 
+/*---------------------------------------------------------------------------*/
+/** @brief ADC Clear Regular End-Of-Conversion Sequence Flag
+ *
+ * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
+ */
+
+void adc_clear_eoc_sequence_flag(uint32_t adc)
+{
+	ADC_ISR(adc) = ADC_ISR_EOSEQ;
+}
 
 /**@}*/
 
@@ -291,12 +301,12 @@ bool adc_get_eoc_sequence_flag(uint32_t adc)
  *@{*/
 
 /*---------------------------------------------------------------------------*/
-/** @brief ADC Set Clock Prescale
+/** @brief ADC Set Clock Source
  *
  * The ADC clock taken from the many sources.
  *
  * @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
- * @param[in] prescale Unsigned int32. Prescale value (@ref adc_api_clksource)
+ * @param[in] source Unsigned int32. Source (@ref adc_api_clksource)
  */
 
 void adc_set_clk_source(uint32_t adc, uint32_t source)
diff --git a/lib/stm32/f0/dac.c b/lib/stm32/f0/dac.c
deleted file mode 100644
index 55cdd62c..00000000
--- a/lib/stm32/f0/dac.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dac_file DAC
- *
- * @ingroup STM32F0xx
- *
- * @brief <b>libopencm3 STM32F0xx DAC</b>
- *
- * @version 1.0.0
- *
- * @date 11 July 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dac.h>
diff --git a/lib/stm32/f0/dma.c b/lib/stm32/f0/dma.c
deleted file mode 100644
index 8f158a81..00000000
--- a/lib/stm32/f0/dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dma_file DMA
- *
- * @ingroup STM32F0xx
- *
- * @brief <b>libopencm3 STM32F0xx DMA</b>
- *
- * @version 1.0.0
- *
- * @date 10 July 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dma.h>
diff --git a/lib/stm32/f0/flash.c b/lib/stm32/f0/flash.c
index 433b7b53..d594a5e6 100644
--- a/lib/stm32/f0/flash.c
+++ b/lib/stm32/f0/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32F0xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F05x FLASH</b>
  *
diff --git a/lib/stm32/f0/gpio.c b/lib/stm32/f0/gpio.c
deleted file mode 100644
index f60b4289..00000000
--- a/lib/stm32/f0/gpio.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup gpio_file GPIO
- *
- * @ingroup STM32F0xx
- *
- * @brief <b>libopencm3 STM32F0xx General Purpose I/O</b>
- *
- * @version 1.0.0
- *
- * @date 18 August 2012
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/gpio.h>
diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c
index d4b79e5d..182bdd28 100644
--- a/lib/stm32/f0/rcc.c
+++ b/lib/stm32/f0/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32F0xx-rcc-file RCC
+/** @defgroup rcc_file RCC peripheral API
  *
- * @ingroup STM32F0xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F0xx Reset and Clock Control</b>
  *
@@ -51,7 +51,7 @@ uint32_t rcc_apb1_frequency = 8000000; /* 8MHz after reset */
  * Clear the interrupt flag that was set when a clock oscillator became ready
  * to use.
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param osc Oscillator ID
  */
 
 void rcc_osc_ready_int_clear(enum rcc_osc osc)
@@ -84,7 +84,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Enable the Oscillator Ready Interrupt
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param osc Oscillator ID
  */
 
 void rcc_osc_ready_int_enable(enum rcc_osc osc)
@@ -117,7 +117,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Disable the Oscillator Ready Interrupt
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param osc Oscillator ID
  */
 
 void rcc_osc_ready_int_disable(enum rcc_osc osc)
@@ -150,7 +150,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Read the Oscillator Ready Interrupt Flag
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param osc Oscillator ID
  * @returns int. Boolean value for flag set.
  */
 
@@ -238,7 +238,7 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc)
  * becomes ready (see @ref rcc_osc_ready_int_flag and @ref
  * rcc_wait_for_osc_ready).
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param osc Oscillator ID
  */
 
 void rcc_osc_on(enum rcc_osc osc)
@@ -276,7 +276,7 @@ void rcc_osc_on(enum rcc_osc osc)
  * @note An oscillator cannot be turned off if it is selected as the system
  * clock.
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param osc Oscillator ID
  */
 
 void rcc_osc_off(enum rcc_osc osc)
@@ -327,7 +327,7 @@ void rcc_css_disable(void)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set the Source for the System Clock.
  *
- * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, LSE and PLL have
+ * @param clk Oscillator ID. Only HSE, LSE and PLL have
  * effect.
  */
 
@@ -357,7 +357,7 @@ void rcc_set_sysclk_source(enum rcc_osc clk)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set the Source for the USB Clock.
  *
- * @param[in] osc enum ::osc_t. Oscillator ID. Only HSI48 or PLL have
+ * @param clk Oscillator ID. Only HSI48 or PLL have
  * effect.
  */
 void rcc_set_usbclk_source(enum rcc_osc clk)
@@ -402,7 +402,7 @@ void rcc_disable_rtc_clock(void)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set the Source for the RTC clock
 
-@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI.
+@param[in] clk RTC clock source. Only HSE/32, LSE and LSI.
 */
 
 void rcc_set_rtc_clock_source(enum rcc_osc clk)
@@ -467,7 +467,7 @@ void rcc_set_pllxtpre(uint32_t pllxtpre)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set the APB Prescale Factor.
  *
- * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
+ * @param[in] ppre Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
  */
 
 void rcc_set_ppre(uint32_t ppre)
@@ -501,7 +501,7 @@ void rcc_set_prediv(uint32_t prediv)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Get the System Clock Source.
  *
- * @returns ::osc_t System clock source:
+ * @returns current system clock source
  */
 
 enum rcc_osc rcc_system_clock_source(void)
@@ -543,7 +543,7 @@ uint32_t rcc_get_i2c_clocks(void)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Get the USB Clock Source.
  *
- * @returns ::osc_t USB clock source:
+ * @returns Currently selected USB clock source
  */
 
 enum rcc_osc rcc_usb_clock_source(void)
diff --git a/lib/stm32/f0/rtc.c b/lib/stm32/f0/rtc.c
deleted file mode 100644
index 6d55cc71..00000000
--- a/lib/stm32/f0/rtc.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup rtc_file RTC
- *
- * @ingroup STM32F0xx
- *
- * @brief <b>libopencm3 STM32F0xx RTC</b>
- *
- * @version 1.0.0
- *
- * @date 10 July 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/rtc.h>
diff --git a/lib/stm32/f0/timer.c b/lib/stm32/f0/timer.c
deleted file mode 100644
index 88006834..00000000
--- a/lib/stm32/f0/timer.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/** @defgroup timer_file Timers
- *
- * @ingroup STM32F0xx
- *
- * @brief <b>libopencm3 STM32F0xx Timers</b>
- *
- * @version 1.0.0
- *
- * @date 11 July 2013
- *
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/timer.h>
-
diff --git a/lib/stm32/f1/Makefile b/lib/stm32/f1/Makefile
index a2a8836e..f55fe391 100755
--- a/lib/stm32/f1/Makefile
+++ b/lib/stm32/f1/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_stm32f1
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -36,22 +34,30 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
 
-OBJS		= adc.o adc_common_v1.o can.o desig.o flash.o gpio.o \
-                  rcc.o rtc.o timer.o
-OBJS		+= mac.o mac_stm32fxx7.o phy.o phy_ksz80x1.o
-
-OBJS            += crc_common_all.o dac_common_all.o dma_common_l1f013.o \
-                   gpio_common_all.o i2c_common_v1.o iwdg_common_all.o \
-                   pwr_common_v1.o \
-                   timer_common_all.o usart_common_all.o usart_common_f124.o \
-                   rcc_common_all.o exti_common_all.o
+OBJS += adc.o adc_common_v1.o
+OBJS += can.o
+OBJS += crc_common_all.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_l1f013.o
+OBJS += exti_common_all.o
+OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f01.o
+OBJS += gpio.o gpio_common_all.o
+OBJS += i2c_common_v1.o
+OBJS += iwdg_common_all.o
+OBJS += pwr_common_v1.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rtc.o
+OBJS += spi_common_all.o spi_common_v1.o
+OBJS += timer.o timer_common_all.o
+OBJS += usart_common_all.o usart_common_f124.o
 
-OBJS		+= flash_common_all.o flash_common_f.o flash_common_f01.o
-OBJS		+= spi_common_all.o spi_common_v1.o
+OBJS += mac.o mac_stm32fxx7.o
+OBJS += phy.o phy_ksz80x1.o
 
-OBJS            += usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS		+= usb_dwc_common.o usb_f107.o
-OBJS		+= st_usbfs_core.o st_usbfs_v1.o
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += usb_dwc_common.o usb_f107.o
+OBJS += st_usbfs_core.o st_usbfs_v1.o
 
 OBJS		+= sdio_common_all.o 
 
diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c
index 24e79c51..3ff12bf7 100644
--- a/lib/stm32/f1/adc.c
+++ b/lib/stm32/f1/adc.c
@@ -59,11 +59,11 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent
 	adc_set_dual_mode(ADC_CR1_DUALMOD_IND);
 	adc_disable_scan_mode(ADC1);
 	adc_set_single_conversion_mode(ADC1);
-	adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC);
-	adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART);
+	adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR_SMP_1DOT5CYC);
+	adc_enable_external_trigger_regular(ADC1, ADC_CR2_EXTSEL_SWSTART);
 	adc_power_on(ADC1);
 	adc_reset_calibration(ADC1);
-	adc_calibration(ADC1);
+	adc_calibrate(ADC1);
 	adc_start_conversion_regular(ADC1);
 	while (! adc_eoc(ADC1));
 	reg16 = adc_read_regular(ADC1);
diff --git a/lib/stm32/f1/dac.c b/lib/stm32/f1/dac.c
deleted file mode 100644
index fa599bb7..00000000
--- a/lib/stm32/f1/dac.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dac_file DAC
-
-@ingroup STM32F1xx
-
-@brief <b>libopencm3 STM32F1xx DAC</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dac.h>
diff --git a/lib/stm32/f1/dma.c b/lib/stm32/f1/dma.c
deleted file mode 100644
index 70193659..00000000
--- a/lib/stm32/f1/dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dma_file DMA
-
-@ingroup STM32F1xx
-
-@brief <b>libopencm3 STM32F1xx DMA</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dma.h>
diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c
index 68606a9a..c990b1e6 100644
--- a/lib/stm32/f1/flash.c
+++ b/lib/stm32/f1/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32F1xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F1xx FLASH Memory</b>
  *
diff --git a/lib/stm32/f1/gpio.c b/lib/stm32/f1/gpio.c
index c8943fce..160c46b5 100644
--- a/lib/stm32/f1/gpio.c
+++ b/lib/stm32/f1/gpio.c
@@ -1,6 +1,4 @@
-/** @defgroup gpio_file GPIO
-
-@ingroup STM32F1xx
+/** @addtogroup gpio_file
 
 @brief <b>libopencm3 STM32F1xx General Purpose I/O</b>
 
diff --git a/lib/stm32/f1/pwr.c b/lib/stm32/f1/pwr.c
deleted file mode 100644
index 167f920d..00000000
--- a/lib/stm32/f1/pwr.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/** @defgroup pwr_file PWR
- *
- * @ingroup STM32F1xx
- *
- * @brief <b>libopencm3 STM32F1xx Power Control</b>
- *
- * @version 1.0.0
- *
- * @author @htmlonly &copy; @endhtmlonly 2012
- * Ken Sarkies <ksarkies@internode.on.net>
- *
- * @date 18 August 2012
- *
- * This library supports the power control system for the
- * STM32F1 series of ARM Cortex Microcontrollers by ST Microelectronics.
- *
- * LGPL License Terms @ref lgpl_license
- */
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/**@{*/
-
-#include <libopencm3/stm32/pwr.h>
-
-/**@}*/
-
diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c
index 69041d7c..6d1c252a 100644
--- a/lib/stm32/f1/rcc.c
+++ b/lib/stm32/f1/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32F1xx-rcc-file RCC
+/** @defgroup rcc_file RCC peripheral API
 
-@ingroup STM32F1xx
+@ingroup peripheral_apis
 
 @brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>
 
@@ -64,7 +64,7 @@ uint32_t rcc_ahb_frequency = 8000000;
 Clear the interrupt flag that was set when a clock oscillator became ready to
 use.
 
-@param[in] osc enum ::osc_t. Oscillator ID
+@param[in] osc Oscillator ID
 */
 
 void rcc_osc_ready_int_clear(enum rcc_osc osc)
@@ -97,7 +97,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Enable the Oscillator Ready Interrupt
 
-@param[in] osc enum ::osc_t. Oscillator ID
+@param osc Oscillator ID
 */
 
 void rcc_osc_ready_int_enable(enum rcc_osc osc)
@@ -130,7 +130,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Disable the Oscillator Ready Interrupt
 
-@param[in] osc enum ::osc_t. Oscillator ID
+@param[in] osc Oscillator ID
 */
 
 void rcc_osc_ready_int_disable(enum rcc_osc osc)
@@ -163,7 +163,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Read the Oscillator Ready Interrupt Flag
 
-@param[in] osc enum ::osc_t. Oscillator ID
+@param[in] osc Oscillator ID
 @returns int. Boolean value for flag set.
 */
 
@@ -255,7 +255,7 @@ status flag is available to indicate when the oscillator becomes ready (see
 backup domain write protection has been removed (see @ref
 pwr_disable_backup_domain_write_protect).
 
-@param[in] osc enum ::osc_t. Oscillator ID
+@param[in] osc Oscillator ID
 */
 
 void rcc_osc_on(enum rcc_osc osc)
@@ -296,7 +296,7 @@ backup domain write protection has been removed (see
 @ref pwr_disable_backup_domain_write_protect) or the backup domain has been
 (see reset @ref rcc_backupdomain_reset).
 
-@param[in] osc enum ::osc_t. Oscillator ID
+@param[in] osc Oscillator ID
 */
 
 void rcc_osc_off(enum rcc_osc osc)
@@ -452,7 +452,7 @@ void rcc_enable_rtc_clock(void)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set the Source for the RTC clock
 
-@param[in] clock_source ::rcc_osc. RTC clock source. Only HSE/128, LSE and LSI.
+@param[in] clock_source RTC clock source. Only HSE/128, LSE and LSI.
 */
 
 void rcc_set_rtc_clock_source(enum rcc_osc clock_source)
diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c
index 2743eed9..ec2711ad 100644
--- a/lib/stm32/f1/rtc.c
+++ b/lib/stm32/f1/rtc.c
@@ -1,6 +1,6 @@
-/** @defgroup rtc_file RTC
+/** @defgroup rtc_file RTC peripheral API
  *
- * @ingroup STM32F1xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F1xx RTC</b>
  *
@@ -241,7 +241,7 @@ uint32_t rtc_get_alarm_val(void)
 /*---------------------------------------------------------------------------*/
 /** @brief RTC set the Counter
 
-@param[in] uint32_t counter_val: 32 bit time setting for the counter.
+@param[in] counter_val 32 bit time setting for the counter.
 */
 
 void rtc_set_counter_val(uint32_t counter_val)
diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c
index fd46742c..6640d6f3 100644
--- a/lib/stm32/f1/timer.c
+++ b/lib/stm32/f1/timer.c
@@ -1,12 +1,5 @@
-/* This file is used for documentation purposes. It does not need
-to be compiled. All source code is in the common area.
-If there is any device specific code required it can be included here,
-in which case this file must be added to the compile list. */
-
-/** @defgroup timer_file Timers
-
-@ingroup STM32F1xx
-
+/** @defgroup timer_file TIMER peripheral API
+@ingroup peripheral_apis
 @brief <b>libopencm3 STM32F1xx Timers</b>
 
 @version 1.0.0
@@ -37,6 +30,8 @@ in which case this file must be added to the compile list. */
 
 #include <libopencm3/stm32/timer.h>
 
+/**@{*/
+
 /*---------------------------------------------------------------------------*/
 /** @brief Set Input Polarity
 
@@ -55,3 +50,4 @@ void timer_ic_set_polarity(uint32_t timer_peripheral, enum tim_ic_id ic,
 	}
 }
 
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/f2/Makefile b/lib/stm32/f2/Makefile
index 4b143e58..c832bc8c 100644
--- a/lib/stm32/f2/Makefile
+++ b/lib/stm32/f2/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_stm32f2
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -36,24 +34,29 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
 
-OBJS		= gpio.o rcc.o desig.o
-
-OBJS            += crc_common_all.o dac_common_all.o dma_common_f24.o \
-                   gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \
-                   iwdg_common_all.o rtc_common_l1f024.o \
-                   timer_common_all.o timer_common_f0234.o \
-		   timer_common_f24.o usart_common_all.o usart_common_f124.o \
-		   hash_common_f24.o \
-		   crypto_common_f24.o exti_common_all.o rcc_common_all.o
-OBJS		+= flash.o flash_common_all.o flash_common_f.o flash_common_f24.o
-OBJS		+= flash_common_idcache.o
-OBJS		+= rng_common_v1.o
-OBJS            += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
-
-OBJS            += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \
-                   usb_f107.o usb_f207.o usb_msc.o
+OBJS += crc_common_all.o
+OBJS += crypto_common_f24.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_f24.o
+OBJS += exti_common_all.o
+OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o flash_common_idcache.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += hash_common_f24.o
+OBJS += i2c_common_v1.o
+OBJS += iwdg_common_all.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rng_common_v1.o
+OBJS += rtc_common_l1f024.o
+OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
+OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o
+OBJS += usart_common_all.o usart_common_f124.o
+
+OBJS += usb.o usb_standard.o usb_control.o usb_msc.o
+OBJS += usb_dwc.o usb_dwc_common.o usb_f107.o usb_f207.o
+
+OBJS += sdio_common_all.o
 
-OBJS		+= sdio_common_all.o 
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/stm32/f2/dac.c b/lib/stm32/f2/dac.c
deleted file mode 100644
index 635e142b..00000000
--- a/lib/stm32/f2/dac.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dac_file DAC
-
-@ingroup STM32F2xx
-
-@brief <b>libopencm3 STM32F2xx DAC</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dac.h>
diff --git a/lib/stm32/f2/dma.c b/lib/stm32/f2/dma.c
deleted file mode 100644
index 285f1fe7..00000000
--- a/lib/stm32/f2/dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dma_file DMA
-
-@ingroup STM32F2xx
-
-@brief <b>libopencm3 STM32F2xx DMA</b>
-
-@version 1.0.0
-
-@date 30 November 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dma.h>
diff --git a/lib/stm32/f2/flash.c b/lib/stm32/f2/flash.c
index c2a0b3ba..958e62a9 100644
--- a/lib/stm32/f2/flash.c
+++ b/lib/stm32/f2/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32F2xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F2xx FLASH</b>
  *
diff --git a/lib/stm32/f2/gpio.c b/lib/stm32/f2/gpio.c
deleted file mode 100644
index 052e306f..00000000
--- a/lib/stm32/f2/gpio.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup gpio_file GPIO
-
-@ingroup STM32F2xx
-
-@brief <b>libopencm3 STM32F2xx General Purpose I/O</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/gpio.h>
diff --git a/lib/stm32/f2/hash.c b/lib/stm32/f2/hash.c
deleted file mode 100644
index ca48d8bb..00000000
--- a/lib/stm32/f2/hash.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup hash_file HASH
- *
- * @ingroup STM32F2xx
- *
- * @brief <b>libopencm3 STM32F2xx Hash Processor</b>
- *
- * @version 1.0.0
- *
- * @date 14 January 2014
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/hash.h>
diff --git a/lib/stm32/f2/pwr.c b/lib/stm32/f2/pwr.c
deleted file mode 100644
index 0e5641eb..00000000
--- a/lib/stm32/f2/pwr.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/** @defgroup pwr_file PWR
- *
- * @ingroup STM32F2xx
- *
- * @brief <b>libopencm3 STM32F2xx Power Control</b>
- *
- * @version 1.0.0
- *
- * @author @htmlonly &copy; @endhtmlonly 2014
- * Ken Sarkies <ksarkies@internode.on.net>
- *
- * @date 13 January 2014
- *
- * This library supports the power control system for the
- * STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics.
- *
- * LGPL License Terms @ref lgpl_license
- */
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/pwr.h>
-
diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c
index b662cebb..e530de47 100644
--- a/lib/stm32/f2/rcc.c
+++ b/lib/stm32/f2/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup rcc_file RCC
+/** @defgroup rcc_file RCC peripheral API
  *
- * @ingroup STM32F2xx
+ * @ingroup peripheral_apis
  *
  * @section rcc_f2_api_ex Reset and Clock Control API.
  *
@@ -355,6 +355,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
 	rcc_set_ppre1(clock->ppre1);
 	rcc_set_ppre2(clock->ppre2);
 
+	/* Disable PLL oscillator before changing its configuration. */
+	rcc_osc_off(RCC_PLL);
+
+	/* Configure the PLL oscillator. */
 	rcc_set_main_pll_hse(clock->pllm, clock->plln,
 			     clock->pllp, clock->pllq);
 
diff --git a/lib/stm32/f2/rtc.c b/lib/stm32/f2/rtc.c
deleted file mode 100644
index 06666ab1..00000000
--- a/lib/stm32/f2/rtc.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup rtc_file RTC
- *
- * @ingroup STM32F2xx
- *
- * @brief <b>libopencm3 STM32F2xx RTC</b>
- *
- * @version 1.0.0
- *
- * @date 4 March 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/rtc.h>
diff --git a/lib/stm32/f2/timer.c b/lib/stm32/f2/timer.c
deleted file mode 100644
index 6600705a..00000000
--- a/lib/stm32/f2/timer.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* This file is used for documentation purposes. It does not need
-to be compiled. All source code is in the common area.
-If there is any device specific code required it can be included here,
-in which case this file must be added to the compile list. */
-
-/** @defgroup timer_file Timers
-
-@ingroup STM32F2xx
-
-@brief <b>libopencm3 STM32F2xx Timers</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/timer.h>
diff --git a/lib/stm32/f3/Makefile b/lib/stm32/f3/Makefile
index e7a35b7f..c24cae90 100644
--- a/lib/stm32/f3/Makefile
+++ b/lib/stm32/f3/Makefile
@@ -21,10 +21,8 @@ LIBNAME		= libopencm3_stm32f3
 SRCLIBDIR	?= ../..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX	        ?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -37,23 +35,25 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 
 ARFLAGS		= rcs
 
-OBJS		= rcc.o adc.o can.o pwr.o dma.o flash.o desig.o
-
-OBJS            += gpio_common_all.o gpio_common_f0234.o \
-		   dac_common_all.o crc_common_all.o crc_v2.o \
-		   iwdg_common_all.o pwr_common_v1.o dma_common_l1f013.o\
-		   timer_common_all.o timer_common_f0234.o \
-		   exti_common_all.o rcc_common_all.o
-OBJS		+= adc_common_v2.o adc_common_v2_multi.o
-OBJS		+= flash_common_all.o flash_common_f.o
-OBJS		+= usart_common_v2.o usart_common_all.o
-OBJS		+= i2c_common_v2.o
-OBJS		+= spi_common_all.o spi_common_v2.o
-
-OBJS		+= usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS		+= st_usbfs_core.o st_usbfs_v1.o
-
-OBJS		+= sdio_common_all.o 
+OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o
+OBJS += can.o
+OBJS += crc_common_all.o crc_v2.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_l1f013.o
+OBJS += exti_common_all.o
+OBJS += flash.o flash_common_all.o flash_common_f.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += i2c_common_v2.o
+OBJS += iwdg_common_all.o
+OBJS += pwr_common_v1.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += spi_common_all.o spi_common_v2.o
+OBJS += timer_common_all.o timer_common_f0234.o
+OBJS += usart_common_v2.o usart_common_all.o
+
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += st_usbfs_core.o st_usbfs_v1.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/stm32/f3/adc.c b/lib/stm32/f3/adc.c
index 9eb73dc2..e9a36846 100644
--- a/lib/stm32/f3/adc.c
+++ b/lib/stm32/f3/adc.c
@@ -587,10 +587,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset)
  *
  * The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
  *
+ * @param adc peripheral of choice @ref adc_reg_base
  * @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
  * adc_ccr_adcpre
-*/
-
+ */
 void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
 {
 	uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | prescale);
@@ -605,10 +605,10 @@ void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
  *
  * The various modes possible are described in the reference manual.
  *
+ * @param adc peripheral of choice @ref adc_reg_base
  * @param[in] mode Unsigned int32. Multiple mode selection from @ref
  * adc_multi_mode
-*/
-
+ */
 void adc_set_multi_mode(uint32_t adc, uint32_t mode)
 {
 	ADC_CCR(adc) |= mode;
diff --git a/lib/stm32/f3/dac.c b/lib/stm32/f3/dac.c
deleted file mode 100644
index 2d8021e0..00000000
--- a/lib/stm32/f3/dac.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dac_file DAC
- *
- * @ingroup STM32F3xx
- *
- * @brief <b>libopencm3 STM32F3xx DAC</b>
- *
- * @version 1.0.0
- *
- * @date 18 August 2012
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dac.h>
diff --git a/lib/stm32/f3/dma.c b/lib/stm32/f3/dma.c
deleted file mode 100644
index c5d82b13..00000000
--- a/lib/stm32/f3/dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dma_file DMA
- *
- * @ingroup STM32F3xx
- *
- * @brief <b>libopencm3 STM32F3xx Direct Memory Access</b>
- *
- * @version 1.0.0
- *
- * @date 11 July 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dma.h>
diff --git a/lib/stm32/f3/flash.c b/lib/stm32/f3/flash.c
index da8dfb68..7d73ce62 100644
--- a/lib/stm32/f3/flash.c
+++ b/lib/stm32/f3/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32F3xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F3xx FLASH</b>
  *
diff --git a/lib/stm32/f3/pwr.c b/lib/stm32/f3/pwr.c
deleted file mode 100644
index 3c1a84bd..00000000
--- a/lib/stm32/f3/pwr.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/** @defgroup pwr_file PWR
- *
- * @ingroup STM32F3xx
- *
- * @brief <b>libopencm3 STM32F3xx Power Control</b>
- *
- * @author @htmlonly &copy; @endhtmlonly 2014
- * Ken Sarkies <ksarkies@internode.on.net>
- *
- * @date 13 January 2014
- *
- * @version 1.0.0
- *
- * @date 11 July 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/pwr.h>
-
-
diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c
index 0fdb9a48..3e1852bf 100644
--- a/lib/stm32/f3/rcc.c
+++ b/lib/stm32/f3/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup rcc_file RCC
+/** @defgroup rcc_file RCC peripheral API
  *
- * @ingroup STM32F3xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F3xx Reset and Clock Control</b>
  *
@@ -80,7 +80,7 @@ const struct rcc_clock_scale rcc_hse8mhz_configs[] = {
 		.ppre1 = RCC_CFGR_PPRE1_DIV_2,
 		.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
 		.ahb_frequency = 72e6,
-		.apb1_frequency = 32e6,
+		.apb1_frequency = 36e6,
 		.apb2_frequency = 72e6,
 	}
 };
diff --git a/lib/stm32/f3/rtc.c b/lib/stm32/f3/rtc.c
deleted file mode 100644
index f332765a..00000000
--- a/lib/stm32/f3/rtc.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/** @defgroup rtc_file RTC
- *
- * @ingroup STM32F3xx
- *
- * @brief <b>libopencm3 STM32F3xx Real Time Clock</b>
- *
- * @version 1.0.0
- *
- * @author @htmlonly &copy; @endhtmlonly 2014
- * Ken Sarkies <ksarkies@internode.on.net>
- *
- * @date 13 January 2014
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2014 Ken Sarkies <ksarkies@internode.on.net>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/rtc.h>
-
-
diff --git a/lib/stm32/f4/Makefile b/lib/stm32/f4/Makefile
index 91ccf4b9..ac2673ca 100644
--- a/lib/stm32/f4/Makefile
+++ b/lib/stm32/f4/Makefile
@@ -22,10 +22,8 @@ LIBNAME		= libopencm3_stm32f4
 SRCLIBDIR	?= ../..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX	        ?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -39,30 +37,39 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
 
-OBJS		= adc.o adc_common_v1.o can.o desig.o gpio.o pwr.o rcc.o \
-		  rtc.o crypto.o
-
-OBJS            += crc_common_all.o dac_common_all.o dma_common_f24.o \
-                   gpio_common_all.o gpio_common_f0234.o i2c_common_v1.o \
-                   iwdg_common_all.o pwr_common_v1.o rtc_common_l1f024.o \
-                   timer_common_all.o \
-                   timer_common_f0234.o timer_common_f24.o usart_common_all.o \
-		   usart_common_f124.o \
-		   hash_common_f24.o crypto_common_f24.o exti_common_all.o \
-		   rcc_common_all.o
-OBJS		+= flash.o flash_common_all.o flash_common_f.o flash_common_f24.o
-OBJS		+= flash_common_idcache.o
-OBJS		+= rng_common_v1.o
-OBJS		+= spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
-
-OBJS		+= sdio_common_all.o 
+OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o
+OBJS += can.o
+OBJS += crc_common_all.o
+OBJS += crypto_common_f24.o crypto.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_f24.o
+OBJS += dma2d_common_f47.o
+OBJS += dsi_common_f47.o
+OBJS += exti_common_all.o
+OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o
+OBJS += flash_common_idcache.o
+OBJS += fmc_common_f47.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += hash_common_f24.o
+OBJS += i2c_common_v1.o
+OBJS += iwdg_common_all.o
+OBJS += lptimer_common_all.o
+OBJS += ltdc_common_f47.o
+OBJS += pwr_common_v1.o pwr.o
+OBJS += rcc_common_all.o rcc.o
+OBJS += rng_common_v1.o
+OBJS += rtc_common_l1f024.o rtc.o
+OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
+OBJS += timer_common_all.o timer_common_f0234.o timer_common_f24.o
+OBJS += usart_common_all.o usart_common_f124.o
 
-OBJS            += usb.o usb_standard.o usb_control.o usb_dwc.o usb_dwc_common.o \
-		   usb_f107.o usb_f207.o usb_msc.o
+OBJS += usb.o usb_standard.o usb_control.o usb_msc.o
+OBJS += usb_dwc.o usb_dwc_common.o usb_f107.o usb_f207.o
 
-OBJS		+= mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o fmc.o
+OBJS += sdio_common_all.o 
 
-OBJS		+= ltdc.o 
+OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o
 
 VPATH += ../../usb:../:../../cm3:../common
 VPATH += ../../ethernet
diff --git a/lib/stm32/f4/dac.c b/lib/stm32/f4/dac.c
deleted file mode 100644
index c5397b62..00000000
--- a/lib/stm32/f4/dac.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dac_file DAC
-
-@ingroup STM32F4xx
-
-@brief <b>libopencm3 STM32F4xx DAC</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dac.h>
diff --git a/lib/stm32/f4/dma.c b/lib/stm32/f4/dma.c
deleted file mode 100644
index 6616621a..00000000
--- a/lib/stm32/f4/dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dma_file DMA
-
-@ingroup STM32F4xx
-
-@brief <b>libopencm3 STM32F4xx DMA</b>
-
-@version 1.0.0
-
-@date 30 November 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dma.h>
diff --git a/lib/stm32/f4/flash.c b/lib/stm32/f4/flash.c
index 8891be6e..93cef9f3 100644
--- a/lib/stm32/f4/flash.c
+++ b/lib/stm32/f4/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32F4xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F4xx FLASH</b>
  *
diff --git a/lib/stm32/f4/gpio.c b/lib/stm32/f4/gpio.c
deleted file mode 100644
index ea59ae79..00000000
--- a/lib/stm32/f4/gpio.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup gpio_file GPIO
-
-@ingroup STM32F4xx
-
-@brief <b>libopencm3 STM32F4xx General Purpose I/O</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/gpio.h>
diff --git a/lib/stm32/f4/hash.c b/lib/stm32/f4/hash.c
deleted file mode 100644
index cd791bff..00000000
--- a/lib/stm32/f4/hash.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup hash_file HASH
- *
- * @ingroup STM32F4xx
- *
- * @brief <b>libopencm3 STM32F4xx Hash Processor</b>
- *
- * @version 1.0.0
- *
- * @date 13 January 2014
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/hash.h>
diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c
index 58d9bd19..0d0c2d2d 100644
--- a/lib/stm32/f4/pwr.c
+++ b/lib/stm32/f4/pwr.c
@@ -1,6 +1,6 @@
-/** @defgroup pwr_file PWR
+/** @defgroup pwr_file PWR peripheral API
  *
- * @ingroup STM32F4xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F4xx Power Control</b>
  *
@@ -36,6 +36,8 @@
 
 #include <libopencm3/stm32/pwr.h>
 
+/**@{*/
+
 void pwr_set_vos_scale(enum pwr_vos_scale scale)
 {
 	uint32_t reg32;
@@ -43,3 +45,5 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale)
 	reg32 |= (scale & PWR_CR_VOS_MASK) << PWR_CR_VOS_SHIFT;
 	PWR_CR = reg32;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index 5dd775d5..66c3d4a1 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup rcc_file RCC
+/** @defgroup rcc_file RCC peripheral API
  *
- * @ingroup STM32F4xx
+ * @ingroup peripheral_apis
  *
  * @section rcc_f4_api_ex Reset and Clock Control API.
  *
@@ -49,29 +49,68 @@ uint32_t rcc_ahb_frequency = 16000000;
 uint32_t rcc_apb1_frequency = 16000000;
 uint32_t rcc_apb2_frequency = 16000000;
 
-const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 8,
-		.plln = 96,
+const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
+	{ /* 84MHz */
+		.pllm = 16,
+		.plln = 336,
+		.pllp = 4,
+		.pllq = 7,
+		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_2,
+		.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
+		.voltage_scale = PWR_SCALE1,
+		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+				FLASH_ACR_LATENCY_2WS,
+		.ahb_frequency  = 84000000,
+		.apb1_frequency = 42000000,
+		.apb2_frequency = 84000000,
+	},
+	{ /* 168MHz */
+		.pllm = 16,
+		.plln = 336,
+		.pllp = 2,
+		.pllq = 7,
+		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
+		.hpre = RCC_CFGR_HPRE_DIV_NONE,
+		.ppre1 = RCC_CFGR_PPRE_DIV_4,
+		.ppre2 = RCC_CFGR_PPRE_DIV_2,
+		.voltage_scale = PWR_SCALE1,
+		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 168000000,
+		.apb1_frequency = 42000000,
+		.apb2_frequency = 84000000,
+	},
+	{ /* 180MHz */
+		.pllm = 16,
+		.plln = 360,
 		.pllp = 2,
-		.pllq = 2,
+		.pllq = 8,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
 		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
 	},
+};
+
+const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
 	{ /* 84MHz */
 		.pllm = 8,
 		.plln = 336,
 		.pllp = 4,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_2,
 		.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
@@ -82,28 +121,13 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 8,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 8,
 		.plln = 336,
 		.pllp = 2,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
@@ -114,31 +138,33 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-};
-
-const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 12,
-		.plln = 96,
+	{ /* 180MHz */
+		.pllm = 8,
+		.plln = 360,
 		.pllp = 2,
-		.pllq = 2,
+		.pllq = 8,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
 		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
 	},
+};
+
+const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
 	{ /* 84MHz */
 		.pllm = 12,
 		.plln = 336,
 		.pllp = 4,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_2,
 		.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
@@ -149,28 +175,13 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 12,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 12,
 		.plln = 336,
 		.pllp = 2,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
@@ -181,31 +192,33 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-};
-
-const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 16,
-		.plln = 96,
+	{ /* 180MHz */
+		.pllm = 12,
+		.plln = 360,
 		.pllp = 2,
-		.pllq = 2,
+		.pllq = 8,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
 		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
 	},
+};
+
+const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
 	{ /* 84MHz */
 		.pllm = 16,
 		.plln = 336,
 		.pllp = 4,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_2,
 		.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
@@ -216,28 +229,13 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 16,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 16,
 		.plln = 336,
 		.pllp = 2,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
@@ -248,31 +246,33 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-};
-
-const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 25,
-		.plln = 96,
+	{ /* 180MHz */
+		.pllm = 16,
+		.plln = 360,
 		.pllp = 2,
-		.pllq = 2,
+		.pllq = 8,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
 		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
 	},
+};
+
+const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
 	{ /* 84MHz */
 		.pllm = 25,
 		.plln = 336,
 		.pllp = 4,
 		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_2,
 		.ppre2 = RCC_CFGR_PPRE_DIV_NONE,
@@ -283,37 +283,39 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
+	{ /* 168MHz */
 		.pllm = 25,
-		.plln = 240,
+		.plln = 336,
 		.pllp = 2,
-		.pllq = 5,
+		.pllq = 7,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
 		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
+				FLASH_ACR_LATENCY_5WS,
+		.ahb_frequency  = 168000000,
+		.apb1_frequency = 42000000,
+		.apb2_frequency = 84000000,
 	},
-	{ /* 168MHz */
+	{ /* 180MHz */
 		.pllm = 25,
-		.plln = 336,
+		.plln = 360,
 		.pllp = 2,
-		.pllq = 7,
+		.pllq = 8,
 		.pllr = 0,
+		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE_DIV_4,
 		.ppre2 = RCC_CFGR_PPRE_DIV_2,
 		.voltage_scale = PWR_SCALE1,
 		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
 				FLASH_ACR_LATENCY_5WS,
-		.ahb_frequency  = 168000000,
-		.apb1_frequency = 42000000,
-		.apb2_frequency = 84000000,
+		.ahb_frequency  = 180000000,
+		.apb1_frequency = 45000000,
+		.apb2_frequency = 90000000,
 	},
 };
 
@@ -684,7 +686,15 @@ uint32_t rcc_system_clock_source(void)
 	return (RCC_CFGR & 0x000c) >> 2;
 }
 
-void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
+/**
+ * Setup clocks to run from PLL.
+ *
+ * The arguments provide the pll source, multipliers, dividers, all that's
+ * needed to establish a system clock.
+ *
+ * @param clock clock information structure.
+ */
+void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
 {
 	/* Enable internal high-speed oscillator (HSI). */
 	rcc_osc_on(RCC_HSI);
@@ -694,8 +704,10 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
 	rcc_set_sysclk_source(RCC_CFGR_SW_HSI);
 
 	/* Enable external high-speed oscillator (HSE). */
-	rcc_osc_on(RCC_HSE);
-	rcc_wait_for_osc_ready(RCC_HSE);
+	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
+		rcc_osc_on(RCC_HSE);
+		rcc_wait_for_osc_ready(RCC_HSE);
+	}
 
 	/* Set the VOS scale mode */
 	rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_PWR);
@@ -709,8 +721,17 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
 	rcc_set_ppre1(clock->ppre1);
 	rcc_set_ppre2(clock->ppre2);
 
-	rcc_set_main_pll_hse(clock->pllm, clock->plln,
-			clock->pllp, clock->pllq, clock->pllr);
+	/* Disable PLL oscillator before changing its configuration. */
+	rcc_osc_off(RCC_PLL);
+
+	/* Configure the PLL oscillator. */
+	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
+		rcc_set_main_pll_hse(clock->pllm, clock->plln,
+				clock->pllp, clock->pllq, clock->pllr);
+	} else {
+		rcc_set_main_pll_hsi(clock->pllm, clock->plln,
+				clock->pllp, clock->pllq, clock->pllr);
+	}
 
 	/* Enable PLL oscillator and wait for it to stabilize. */
 	rcc_osc_on(RCC_PLL);
@@ -741,7 +762,21 @@ void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
 	rcc_apb2_frequency = clock->apb2_frequency;
 
 	/* Disable internal high-speed oscillator. */
-	rcc_osc_off(RCC_HSI);
+	if (clock->pll_source == RCC_CFGR_PLLSRC_HSE_CLK) {
+		rcc_osc_off(RCC_HSI);
+	}
+}
+
+/**
+ * Setup clocks with the HSE.
+ *
+ * @deprecated replaced by rcc_clock_setup_pll as a drop in replacement.
+ * @see rcc_clock_setup_pll which supports HSI as well as HSE, using the same
+ * clock structures.
+ */
+void rcc_clock_setup_hse_3v3(const struct rcc_clock_scale *clock)
+{
+	rcc_clock_setup_pll(clock);
 }
 
 /**@}*/
diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c
index f08ac2bc..847fb55b 100644
--- a/lib/stm32/f4/rtc.c
+++ b/lib/stm32/f4/rtc.c
@@ -1,6 +1,6 @@
-/** @defgroup rtc_file RTC
+/** @defgroup rtc_file RTC peripheral API
  *
- * @ingroup STM32F4xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F4xx RTC</b>
  *
@@ -32,6 +32,7 @@
 #include <libopencm3/cm3/nvic.h>
 #include <libopencm3/stm32/rtc.h>
 
+/**@{*/
 
 /*---------------------------------------------------------------------------*/
 /** @brief Enable the wakeup timer
@@ -95,3 +96,5 @@ void rtc_disable_wakeup_timer_interrupt(void)
 	/* 3. Disable RTC wakeup timer event. */
 	RTC_CR &= ~RTC_CR_WUTIE;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/f4/timer.c b/lib/stm32/f4/timer.c
deleted file mode 100644
index 72ecd8df..00000000
--- a/lib/stm32/f4/timer.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* This file is used for documentation purposes. It does not need
-to be compiled. All source code is in the common area.
-If there is any device specific code required it can be included here,
-in which case this file must be added to the compile list. */
-
-/** @defgroup timer_file Timers
-
-@ingroup STM32F4xx
-
-@brief <b>libopencm3 STM32F4xx Timers</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
- * Copyright (C) 2011 Stephen Caudle <scaudle@doceme.com>
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/timer.h>
diff --git a/lib/stm32/f7/Makefile b/lib/stm32/f7/Makefile
index 8b1bdef7..ff078655 100644
--- a/lib/stm32/f7/Makefile
+++ b/lib/stm32/f7/Makefile
@@ -21,10 +21,8 @@
 LIBNAME		= libopencm3_stm32f7
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 
 # STM32F7 only supports single precision FPU
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv5-sp-d16
@@ -42,16 +40,31 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 
 ARFLAGS		= rcs
 
-OBJS		= flash_common_all.o flash_common_f.o flash_common_f24.o flash.o
-OBJS		+= desig.o
-OBJS		+= gpio.o gpio_common_all.o gpio_common_f0234.o
-OBJS		+= pwr.o rcc.o
+OBJS += adc_common_v1.o adc_common_v1_multi.o adc_common_f47.o
+OBJS += can.o
+OBJS += crc_common_all.o crc_v2.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_f24.o
+OBJS += dma2d_common_f47.o
+OBJS += dsi_common_f47.o
+OBJS += exti_common_all.o
+OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o
+OBJS += fmc_common_f47.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += i2c_common_v2.o
+OBJS += iwdg_common_all.o
+OBJS += lptimer_common_all.o
+OBJS += ltdc_common_f47.o
+OBJS += pwr.o rcc.o
+OBJS += rcc_common_all.o
+OBJS += rng_common_v1.o
+OBJS += spi_common_all.o spi_common_v2.o
+OBJS += timer_common_all.o
+OBJS += usart_common_all.o usart_common_v2.o
 
-OBJS		+= rcc_common_all.o
-OBJS		+= rng_common_v1.o
-OBJS		+= spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
-OBJS		+= timer_common_all.o
-OBJS		+= usart_common_all.o usart_common_v2.o
+# Ethernet
+OBJS += mac.o phy.o mac_stm32fxx7.o phy_ksz80x1.o
 
 VPATH += ../../usb:../:../../cm3:../common
 VPATH += ../../ethernet
diff --git a/lib/stm32/f7/flash.c b/lib/stm32/f7/flash.c
index 9ec3e219..82dcf4f3 100644
--- a/lib/stm32/f7/flash.c
+++ b/lib/stm32/f7/flash.c
@@ -1,5 +1,6 @@
-/** @addtogroup flash_file
+/** @defgroup flash_file FLASH peripheral API
  *
+ * @ingroup peripheral_apis
  */
 
 /*
diff --git a/lib/stm32/f7/gpio.c b/lib/stm32/f7/gpio.c
deleted file mode 100644
index a5fb4afc..00000000
--- a/lib/stm32/f7/gpio.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup gpio_file GPIO
-
-@ingroup STM32F7xx
-
-@brief <b>libopencm3 STM32F7xx General Purpose I/O</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/gpio.h>
diff --git a/lib/stm32/f7/pwr.c b/lib/stm32/f7/pwr.c
index 93bb845d..cb19bb6a 100644
--- a/lib/stm32/f7/pwr.c
+++ b/lib/stm32/f7/pwr.c
@@ -1,6 +1,6 @@
-/** @defgroup pwr_file PWR
+/** @defgroup pwr_file PWR peripheral API
  *
- * @ingroup STM32F7xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32F7xx Power Control</b>
  *
@@ -38,6 +38,8 @@
 
 #include <libopencm3/stm32/pwr.h>
 
+/**@{*/
+
 void pwr_set_vos_scale(enum pwr_vos_scale scale)
 {
 	PWR_CR1 &= ~PWR_CR1_VOS_MASK;
@@ -64,3 +66,5 @@ void pwr_disable_overdrive(void)
 	PWR_CR1 &= ~(PWR_CR1_ODEN | PWR_CR1_ODSWEN);
 	while (!(PWR_CSR1 & PWR_CSR1_ODSWRDY));
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c
index ea6dcd50..7abdd770 100644
--- a/lib/stm32/f7/rcc.c
+++ b/lib/stm32/f7/rcc.c
@@ -1,8 +1,19 @@
+/** @defgroup rcc_file RCC peripheral API
+ *
+ * @ingroup peripheral_apis
+ * This library supports the Reset and Clock Control System in the STM32 series
+ * of ARM Cortex Microcontrollers by ST Microelectronics.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
 #include <libopencm3/cm3/assert.h>
 #include <libopencm3/stm32/rcc.h>
 #include <libopencm3/stm32/pwr.h>
 #include <libopencm3/stm32/flash.h>
 
+/**@{*/
+
 uint32_t rcc_ahb_frequency = 16000000;
 uint32_t rcc_apb1_frequency = 16000000;
 uint32_t rcc_apb2_frequency = 16000000;
@@ -392,6 +403,10 @@ void rcc_clock_setup_hse(const struct rcc_clock_scale *clock, uint32_t hse_mhz)
 	rcc_set_ppre1(clock->ppre1);
 	rcc_set_ppre2(clock->ppre2);
 
+	/* Disable PLL oscillator before changing its configuration. */
+	rcc_osc_off(RCC_PLL);
+
+	/* Configure the PLL oscillator. */
 	rcc_set_main_pll_hse(pllm, clock->plln,
 			     clock->pllp, clock->pllq);
 
@@ -468,3 +483,5 @@ void rcc_clock_setup_hsi(const struct rcc_clock_scale *clock)
 	rcc_apb1_frequency = clock->apb1_frequency;
 	rcc_apb2_frequency = clock->apb2_frequency;
 }
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/g0/Makefile b/lib/stm32/g0/Makefile
new file mode 100644
index 00000000..cb75e4fe
--- /dev/null
+++ b/lib/stm32/g0/Makefile
@@ -0,0 +1,53 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME		= libopencm3_stm32g0
+SRCLIBDIR	?= ../..
+
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
+TGT_CFLAGS	= -Os \
+		  -Wall -Wextra -Wimplicit-function-declaration \
+		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
+		  -Wundef -Wshadow \
+		  -I../../../include -fno-common \
+		  -mcpu=cortex-m0plus -mthumb $(FP_FLAGS) \
+		  -ffunction-sections -fdata-sections -MD -DSTM32G0
+TGT_CFLAGS	+= $(DEBUG_FLAGS)
+TGT_CFLAGS	+= $(STANDARD_FLAGS)
+
+ARFLAGS		= rcs
+
+OBJS += crc_common_all.o
+OBJS += exti.o exti_common_all.o
+OBJS += flash.o flash_common_all.o
+OBJS += gpio_common_all.o gpio_common_f0234.o 
+OBJS += i2c_common_v2.o
+OBJS += iwdg_common_all.o
+OBJS += lptimer_common_all.o
+OBJS += pwr.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rng_common_v1.o
+OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
+OBJS += timer_common_all.o
+OBJS += usart_common_all.o usart_common_v2.o
+
+VPATH +=../:../../cm3:../common
+
+include ../../Makefile.include
diff --git a/lib/stm32/g0/exti.c b/lib/stm32/g0/exti.c
new file mode 100644
index 00000000..fb5534ba
--- /dev/null
+++ b/lib/stm32/g0/exti.c
@@ -0,0 +1,72 @@
+/** @defgroup exti_file EXTI peripheral API
+ * @ingroup peripheral_apis
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * @date 10 January 2019
+ * 
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/exti.h>
+
+/* @brief Get the rising edge interrupt requestf flag of a given EXTI interrupt.
+ *
+ * @param[in] exti unsigned int32 Exti line.
+ *
+ * */
+uint32_t exti_get_rising_flag_status(uint32_t exti)
+{
+	return (EXTI_RPR1 & exti);
+}
+
+/* @brief Get the rising edge interrupt request flag of a given EXTI interrupt.
+ *
+ * @param[in] exti unsigned int32 Exti line.
+ *
+ * */
+uint32_t exti_get_falling_flag_status(uint32_t exti)
+{
+	return (EXTI_FPR1 & exti);
+}
+
+/* @brief Resets the rising edge interrupt request pending flag of a given EXTI interrupt.
+ *
+ * @param[in] exti unsigned int32 Exti line.
+ *
+ * */
+void exti_reset_rising_request(uint32_t extis)
+{
+	EXTI_RPR1 = extis;
+}
+
+/* @brief Resets the falling edge interrupt request pending flag of a given EXTI interrupt.
+ *
+ * @param[in] exti unsigned int32 Exti line.
+ *
+ * */
+void exti_reset_falling_request(uint32_t extis)
+{
+	EXTI_FPR1 = extis;
+}
+
+/**@}*/
diff --git a/lib/stm32/l0/flash.c b/lib/stm32/g0/flash.c
index b1ba6420..74ecf5d0 100644
--- a/lib/stm32/l0/flash.c
+++ b/lib/stm32/g0/flash.c
@@ -1,8 +1,10 @@
-/** @defgroup gpio_file GPIO
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32L0xx
+ * @ingroup peripheral_apis
  *
- * @brief <b>libopencm3 STM32L0xx General Purpose I/O</b>
+ * @brief <b>libopencm3 STM32G0xx FLASH</b>
+ *
+ * @version 1.0.0
  *
  * LGPL License Terms @ref lgpl_license
  */
@@ -24,4 +26,51 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
+/**@{*/
+
 #include <libopencm3/stm32/flash.h>
+
+void flash_icache_enable(void)
+{
+	FLASH_ACR |= FLASH_ACR_ICEN;
+}
+
+void flash_icache_disable(void)
+{
+	FLASH_ACR &= ~FLASH_ACR_ICEN;
+}
+
+void flash_icache_reset(void)
+{
+	FLASH_ACR |= FLASH_ACR_ICRST;
+}
+
+void flash_unlock_progmem(void)
+{
+	FLASH_KEYR = FLASH_KEYR_KEY1;
+	FLASH_KEYR = FLASH_KEYR_KEY2;
+}
+
+void flash_lock_progmem(void)
+{
+	FLASH_CR |= FLASH_CR_LOCK;
+}
+
+void flash_lock_option_bytes(void)
+{
+	FLASH_CR |= FLASH_CR_OPTLOCK;
+}
+
+void flash_unlock(void)
+{
+	flash_unlock_progmem();
+	flash_unlock_option_bytes();
+}
+
+void flash_lock(void)
+{
+	flash_lock_option_bytes();
+	flash_lock_progmem();
+}
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/stm32/g0/pwr.c b/lib/stm32/g0/pwr.c
new file mode 100644
index 00000000..32cd535a
--- /dev/null
+++ b/lib/stm32/g0/pwr.c
@@ -0,0 +1,100 @@
+/** @defgroup pwr_file PWR peripheral API
+ * @ingroup peripheral_apis
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * @ingroup peripheral_apis
+ *
+ * @brief <b>libopencm3 STM32G0xx Power Control</b>
+ *
+ * @version 1.0.0
+ *
+ * This library supports the power control system for the
+ * STM32G0 series of ARM Cortex Microcontrollers by ST Microelectronics.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/**@{*/
+#include <libopencm3/stm32/pwr.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief Setup voltage scaling range. 
+ */
+void pwr_set_vos_scale(enum pwr_vos_scale scale)
+{
+	uint32_t reg32;
+
+	reg32 = PWR_CR1 & ~(PWR_CR1_VOS_MASK << PWR_CR1_VOS_SHIFT);
+	reg32 |= (scale & PWR_CR1_VOS_MASK) << PWR_CR1_VOS_SHIFT;
+	PWR_CR1 = reg32;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable RTC domain write protect. 
+ */
+void pwr_disable_backup_domain_write_protect(void)
+{
+	PWR_CR1 |= PWR_CR1_DBP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable RTC domain write protect. 
+ */
+void pwr_enable_backup_domain_write_protect(void)
+{
+	PWR_CR1 &= ~PWR_CR1_DBP;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Select the low power mode used in deep sleep.
+ * @param lpms low power mode @ref pwr_cr1_lpms
+ */
+void pwr_set_low_power_mode_selection(uint32_t lpms)
+{
+	uint32_t reg32;
+
+	reg32 = PWR_CR1;
+	reg32 &= ~(PWR_CR1_LPMS_MASK << PWR_CR1_LPMS_SHIFT);
+	PWR_CR1 = (reg32 | (lpms << PWR_CR1_LPMS_SHIFT));
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable Power Voltage Detector.
+ * @param[in] pvdr_level Power Voltage Detector Rising Threshold voltage @ref pwr_cr2_pvdrt.
+ * @param[in] pvdf_level Power Voltage Detector Falling Threshold voltage @ref pwr_cr2_pvdft.
+*/
+void pwr_enable_power_voltage_detect(uint32_t pvdr_level, uint32_t pvdf_level)
+{
+	uint32_t reg32;
+
+	reg32 = PWR_CR2;
+	reg32 &= ~(PWR_CR2_PVDRT_MASK << PWR_CR2_PVDRT_SHIFT);
+	reg32 &= ~(PWR_CR2_PVDFT_MASK << PWR_CR2_PVDFT_SHIFT);
+	PWR_CR2 = (reg32 | (pvdf_level << PWR_CR2_PVDFT_SHIFT) | (pvdr_level << PWR_CR2_PVDRT_SHIFT) | PWR_CR2_PVDE);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Disable Power Voltage Detector.
+*/
+void pwr_disable_power_voltage_detect(void)
+{
+	PWR_CR2 &= ~PWR_CR2_PVDE;
+}
+
+/**@}*/
diff --git a/lib/stm32/g0/rcc.c b/lib/stm32/g0/rcc.c
new file mode 100644
index 00000000..c3f157ab
--- /dev/null
+++ b/lib/stm32/g0/rcc.c
@@ -0,0 +1,550 @@
+/** @defgroup rcc_file RCC peripheral API
+ *
+ * @ingroup peripheral_apis
+ *
+ * @brief <b>libopencm3 STM32G0xx Reset and Clock Control</b>
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2019 Guillaume Revaillot <g.revaillot@gmail.com>
+ *
+ * @date 10 January 2019
+ *
+ * This library supports the Reset and Clock Control System in the STM32 series
+ * of ARM Cortex Microcontrollers by ST Microelectronics.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/stm32/rcc.h>
+#include <libopencm3/stm32/pwr.h>
+#include <libopencm3/stm32/flash.h>
+#include <libopencm3/cm3/assert.h>
+
+/* Set the default clock frequencies after reset. */
+uint32_t rcc_ahb_frequency =  16000000;
+uint32_t rcc_apb1_frequency = 16000000;
+
+const struct rcc_clock_scale rcc_clock_config[RCC_CLOCK_CONFIG_END] = {
+	[RCC_CLOCK_CONFIG_LSI_32KHZ] = {
+		/* 32khz from lsi, scale2, 0ws */
+		.sysclock_source = RCC_LSI,
+		.hpre = RCC_CFGR_HPRE_NODIV,
+		.ppre = RCC_CFGR_PPRE_NODIV,
+		.flash_waitstates = FLASH_ACR_LATENCY_0WS,
+		.voltage_scale = PWR_SCALE2,
+		.ahb_frequency = 32000,
+		.apb_frequency = 32000,
+	},
+	[RCC_CLOCK_CONFIG_HSI_4MHZ] = {
+		/* 4mhz from hsi/4, scale2, 0ws */
+		.sysclock_source = RCC_HSI,
+		.hsisys_div = RCC_CR_HSIDIV_DIV4,
+		.hpre = RCC_CFGR_HPRE_NODIV,
+		.ppre = RCC_CFGR_PPRE_NODIV,
+		.flash_waitstates = FLASH_ACR_LATENCY_0WS,
+		.voltage_scale = PWR_SCALE2,
+		.ahb_frequency = 4000000,
+		.apb_frequency = 4000000,
+	},
+	[RCC_CLOCK_CONFIG_HSI_16MHZ] = {
+		/* 16mhz from hsi, scale2, 0ws */
+		.sysclock_source = RCC_HSI,
+		.hsisys_div = RCC_CR_HSIDIV_DIV1,
+		.hpre = RCC_CFGR_HPRE_NODIV,
+		.ppre = RCC_CFGR_PPRE_NODIV,
+		.flash_waitstates = FLASH_ACR_LATENCY_0WS,
+		.voltage_scale = PWR_SCALE2,
+		.ahb_frequency = 16000000,
+		.apb_frequency = 16000000,
+	},
+	[RCC_CLOCK_CONFIG_HSI_PLL_32MHZ] = {
+		/* 32mhz from hsi via pll @ 128mhz / 4, scale1, 1ws */
+		.sysclock_source = RCC_PLL,
+		.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
+		.pll_div = RCC_PLLCFGR_PLLM_DIV(1),
+		.pll_mul = RCC_PLLCFGR_PLLN_MUL(8),
+		.pllp_div = RCC_PLLCFGR_PLLP_DIV(4),
+		.pllq_div = RCC_PLLCFGR_PLLQ_DIV(4),
+		.pllr_div = RCC_PLLCFGR_PLLR_DIV(4),
+		.hpre = RCC_CFGR_HPRE_NODIV,
+		.ppre = RCC_CFGR_PPRE_NODIV,
+		.flash_waitstates = FLASH_ACR_LATENCY_1WS,
+		.voltage_scale = PWR_SCALE1,
+		.ahb_frequency = 32000000,
+		.apb_frequency = 32000000,
+	},
+	[RCC_CLOCK_CONFIG_HSI_PLL_64MHZ] = {
+		/* 64mhz from hsi via pll @ 128mhz / 2, scale1, 2ws */
+		.sysclock_source = RCC_PLL,
+		.pll_source = RCC_PLLCFGR_PLLSRC_HSI16,
+		.pll_div = RCC_PLLCFGR_PLLM_DIV(1),
+		.pll_mul = RCC_PLLCFGR_PLLN_MUL(8),
+		.pllp_div = RCC_PLLCFGR_PLLP_DIV(2),
+		.pllq_div = RCC_PLLCFGR_PLLQ_DIV(2),
+		.pllr_div = RCC_PLLCFGR_PLLR_DIV(2),
+		.hpre = RCC_CFGR_HPRE_NODIV,
+		.ppre = RCC_CFGR_PPRE_NODIV,
+		.flash_waitstates = FLASH_ACR_LATENCY_2WS,
+		.voltage_scale = PWR_SCALE1,
+		.ahb_frequency = 64000000,
+		.apb_frequency = 64000000,
+	},
+	[RCC_CLOCK_CONFIG_HSE_12MHZ_PLL_64MHZ] = {
+		/* 64mhz from hse@12mhz via pll @ 128mhz / 2, scale1, 2ws */
+		.sysclock_source = RCC_PLL,
+		.pll_source = RCC_PLLCFGR_PLLSRC_HSE,
+		.pll_div = RCC_PLLCFGR_PLLM_DIV(3),
+		.pll_mul = RCC_PLLCFGR_PLLN_MUL(32),
+		.pllp_div = RCC_PLLCFGR_PLLP_DIV(2),
+		.pllq_div = RCC_PLLCFGR_PLLQ_DIV(2),
+		.pllr_div = RCC_PLLCFGR_PLLR_DIV(2),
+		.hpre = RCC_CFGR_HPRE_NODIV,
+		.ppre = RCC_CFGR_PPRE_NODIV,
+		.flash_waitstates = FLASH_ACR_LATENCY_2WS,
+		.voltage_scale = PWR_SCALE1,
+		.ahb_frequency = 64000000,
+		.apb_frequency = 64000000,
+	},
+};
+
+void rcc_osc_on(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CR |= RCC_CR_PLLON;
+		break;
+	case RCC_HSE:
+		RCC_CR |= RCC_CR_HSEON;
+		break;
+	case RCC_HSI:
+		RCC_CR |= RCC_CR_HSION;
+		break;
+	case RCC_LSE:
+		RCC_BDCR |= RCC_BDCR_LSEON;
+		break;
+	case RCC_LSI:
+		RCC_CSR |= RCC_CSR_LSION;
+		break;
+	default:
+		cm3_assert_not_reached();
+		break;
+	}
+}
+
+void rcc_osc_off(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		RCC_CR &= ~RCC_CR_PLLON;
+		break;
+	case RCC_HSE:
+		RCC_CR &= ~RCC_CR_HSEON;
+		break;
+	case RCC_HSI:
+		RCC_CR &= ~RCC_CR_HSION;
+		break;
+	case RCC_LSE:
+		RCC_BDCR &= ~RCC_BDCR_LSEON;
+		break;
+	case RCC_LSI:
+		RCC_CSR &= ~RCC_CSR_LSION;
+		break;
+	default:
+		cm3_assert_not_reached();
+		break;
+	}
+}
+
+bool rcc_is_osc_ready(enum rcc_osc osc)
+{
+	switch (osc) {
+	case RCC_PLL:
+		return RCC_CR & RCC_CR_PLLRDY;
+	case RCC_HSE:
+		return RCC_CR & RCC_CR_HSERDY;
+	case RCC_HSI:
+		return RCC_CR & RCC_CR_HSIRDY;
+	case RCC_LSE:
+		return RCC_BDCR & RCC_BDCR_LSERDY;
+	case RCC_LSI:
+		return RCC_CSR & RCC_CSR_LSIRDY;
+	default:
+		cm3_assert_not_reached();
+		return 0;
+	}
+	return false;
+}
+
+void rcc_wait_for_osc_ready(enum rcc_osc osc)
+{
+	while (!rcc_is_osc_ready(osc));
+}
+
+void rcc_css_enable(void)
+{
+	RCC_CR |= RCC_CR_CSSON;
+}
+
+void rcc_css_disable(void)
+{
+	RCC_CR &= ~RCC_CR_CSSON;
+}
+
+void rcc_css_int_clear(void)
+{
+	RCC_CICR |= RCC_CICR_CSSC;
+}
+
+int rcc_css_int_flag(void)
+{
+	return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the Source for the System Clock.
+ * @param osc Oscillator to use.
+ */
+void rcc_set_sysclk_source(enum rcc_osc osc)
+{
+	uint32_t reg32;
+	uint32_t sw = 0;
+
+	switch (osc) {
+		case RCC_HSI:
+			sw = RCC_CFGR_SW_HSISYS;
+			break;
+		case RCC_HSE:
+			sw = RCC_CFGR_SW_HSE;
+			break;
+		case RCC_PLL:
+			sw = RCC_CFGR_SW_PLLRCLK;
+			break;
+		case RCC_LSE:
+			sw = RCC_CFGR_SW_LSE;
+			break;
+		case RCC_LSI:
+			sw = RCC_CFGR_SW_LSI;
+			break;
+		default:
+			cm3_assert_not_reached();
+			return;
+	}
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
+	RCC_CFGR = (reg32 | (sw << RCC_CFGR_SW_SHIFT));
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Return the clock source which is used as system clock.
+ * @return rcc_osc system clock source
+ */
+enum rcc_osc rcc_system_clock_source(void)
+{
+	switch ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) {
+		case RCC_CFGR_SW_HSISYS:
+			return RCC_HSI;
+		case RCC_CFGR_SW_HSE:
+			return RCC_HSE;
+		case RCC_CFGR_SWS_PLLRCLK:
+			return RCC_PLL;
+		case RCC_CFGR_SW_LSE:
+			return RCC_LSE;
+		case RCC_CFGR_SW_LSI:
+			return RCC_LSI;
+		default:
+			cm3_assert_not_reached();
+			return 0;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Wait until system clock switched to given oscillator.
+ * @param osc Oscillator.
+ */
+void rcc_wait_for_sysclk_status(enum rcc_osc osc)
+{
+	uint32_t sws = 0;
+
+	switch (osc) {
+		case RCC_PLL:
+			sws = RCC_CFGR_SWS_PLLRCLK;
+			break;
+		case RCC_HSE:
+			sws = RCC_CFGR_SWS_HSE;
+			break;
+		case RCC_HSI:
+			sws = RCC_CFGR_SWS_HSISYS;
+			break;
+		case RCC_LSI:
+			sws = RCC_CFGR_SWS_LSI;
+			break;
+		case RCC_LSE:
+			sws = RCC_CFGR_SWS_LSE;
+			break;
+		default:
+			cm3_assert_not_reached();
+			break;
+	}
+
+	while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK) != sws);
+}
+
+/**
+ * @brief Configure pll source.
+ * @param[in] pllsrc pll clock source @ref rcc_pllcfgr_pllsrc
+ */
+void rcc_set_pll_source(uint32_t pllsrc)
+{
+	uint32_t reg32;
+
+	reg32 = RCC_PLLCFGR;
+	reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
+	RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
+}
+
+/**
+ * @brief Configure pll source and output frequencies.
+ * @param[in] source pll clock source @ref rcc_pllcfgr_pllsrc
+ * @param[in] pllm pll vco division factor @ref rcc_pllcfgr_pllm
+ * @param[in] plln pll vco multiplation factor @ref rcc_pllcfgr_plln
+ * @param[in] pllp pll P clock output division factor @ref rcc_pllcfgr_pllp
+ * @param[in] pllq pll Q clock output division factor @ref rcc_pllcfgr_pllq
+ * @param[in] pllr pll R clock output (sysclock pll) division factor @ref rcc_pllcfgr_pllr
+ */
+void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp,
+	uint32_t pllq, uint32_t pllr)
+{
+	RCC_PLLCFGR = (source << RCC_PLLCFGR_PLLSRC_SHIFT) |
+		(pllm << RCC_PLLCFGR_PLLM_SHIFT) |
+		(plln << RCC_PLLCFGR_PLLN_SHIFT) |
+		(pllp << RCC_PLLCFGR_PLLP_SHIFT) |
+		(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
+		(pllr << RCC_PLLCFGR_PLLR_SHIFT);
+}
+
+/**
+ * @brief Enable PLL P clock output.
+ * @param[in] enable or disable P clock output
+ */
+void rcc_enable_pllp(bool enable)
+{
+	if (enable) {
+		RCC_PLLCFGR |= RCC_PLLCFGR_PLLPEN;
+	} else {
+		RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLPEN;
+	}
+}
+
+/**
+ * @brief Enable PLL Q clock output.
+ * @param[in] enable or disable Q clock output
+ */
+void rcc_enable_pllq(bool enable)
+{
+	if (enable) {
+		RCC_PLLCFGR |= RCC_PLLCFGR_PLLQEN;
+	} else {
+		RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLQEN;
+	}
+}
+
+/**
+ * @brief Enable PLL R clock output.
+ * @param[in] enable or disable R clock output
+ */
+void rcc_enable_pllr(bool enable)
+{
+	if (enable) {
+		RCC_PLLCFGR |= RCC_PLLCFGR_PLLREN;
+	} else {
+		RCC_PLLCFGR &= ~RCC_PLLCFGR_PLLREN;
+	}
+}
+
+/**
+ * @brief Configure APB peripheral clock prescaler
+ * @param[in] ppre APB clock prescaler value @ref rcc_cfgr_ppre
+ */
+void rcc_set_ppre(uint32_t ppre)
+{
+	uint32_t reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~(RCC_CFGR_PPRE_MASK << RCC_CFGR_PPRE_SHIFT);
+	RCC_CFGR = (reg32 | (ppre << RCC_CFGR_PPRE_SHIFT));
+}
+
+/**
+ * @brief Configure AHB peripheral clock prescaler
+ * @param[in] hpre AHB clock prescaler value @ref rcc_cfgr_hpre
+ */
+void rcc_set_hpre(uint32_t hpre)
+{
+	uint32_t reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
+	RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
+}
+
+/**
+ * @brief Configure HSI16 clock division factor to feed SYSCLK
+ * @param[in] hsidiv HSYSSIS clock division factor @ref rcc_cr_hsidiv
+ */
+void rcc_set_hsisys_div(uint32_t hsidiv)
+{
+	uint32_t reg32;
+
+	reg32 = RCC_CR;
+	reg32 &= ~(RCC_CR_HSIDIV_MASK << RCC_CR_HSIDIV_SHIFT);
+	RCC_CR = (reg32 | (hsidiv << RCC_CR_HSIDIV_SHIFT));
+}
+
+/**
+ * @brief Configure mco prescaler.
+ * @param[in] mcopre prescaler value @ref rcc_cfgr_mcopre
+ */
+void rcc_set_mcopre(uint32_t mcopre)
+{
+	uint32_t reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~(RCC_CFGR_MCOPRE_MASK << RCC_CFGR_MCOPRE_SHIFT);
+	RCC_CFGR = (reg32 | (mcopre << RCC_CFGR_MCOPRE_SHIFT));
+}
+
+/**
+ * @brief Setup sysclock with desired source (HSE/HSI/PLL/LSE/LSI). taking care of flash/pwr and src configuration
+ * @param clock rcc_clock_scale with desired parameters
+ */
+void rcc_clock_setup(const struct rcc_clock_scale *clock)
+{	
+	if (clock->sysclock_source == RCC_PLL) {
+		enum rcc_osc pll_source;
+
+		if (clock->pll_source == RCC_PLLCFGR_PLLSRC_HSE)
+			pll_source = RCC_HSE;
+		else
+			pll_source = RCC_HSI;
+
+		/* start pll src osc. */
+		rcc_osc_on(pll_source);
+		rcc_wait_for_osc_ready(pll_source);
+
+		/* stop pll to reconfigure it. */
+		rcc_osc_off(RCC_PLL);
+		while (rcc_is_osc_ready(RCC_PLL));
+
+		rcc_set_main_pll(clock->pll_source, clock->pll_div, clock->pll_mul, clock->pllp_div, clock->pllq_div, clock->pllr_div);
+
+		rcc_enable_pllr(true);
+	} else if (clock->sysclock_source == RCC_HSI) {
+		rcc_set_hsisys_div(clock->hsisys_div);
+	}
+
+	rcc_periph_clock_enable(RCC_PWR);
+	pwr_set_vos_scale(clock->voltage_scale);
+
+	flash_set_ws(clock->flash_waitstates);
+
+	/* enable flash prefetch if we have at least 1WS */
+	if (clock->flash_waitstates > FLASH_ACR_LATENCY_0WS)
+		flash_prefetch_enable();
+	else
+		flash_prefetch_disable();
+
+	rcc_set_hpre(clock->hpre);
+	rcc_set_ppre(clock->ppre);
+
+	rcc_osc_on(clock->sysclock_source);
+	rcc_wait_for_osc_ready(clock->sysclock_source);
+
+	rcc_set_sysclk_source(clock->sysclock_source);
+	rcc_wait_for_sysclk_status(clock->sysclock_source);
+
+	rcc_ahb_frequency = clock->ahb_frequency;
+	rcc_apb1_frequency = clock->apb_frequency;
+}
+
+/**
+ * @brief Setup RNG Peripheral Clock Divider
+ * @param rng_div clock divider @ref rcc_ccipr_rngdiv
+ */
+void rcc_set_rng_clk_div(uint32_t rng_div)
+{
+	uint32_t reg32 = RCC_CCIPR & ~(RCC_CCIPR_RNGDIV_MASK << RCC_CCIPR_RNGDIV_SHIFT);
+	RCC_CCIPR = reg32 | (rng_div << RCC_CCIPR_RNGDIV_SHIFT);
+}
+
+/**
+ * @brief Set the peripheral clock source
+ * @param periph peripheral of choice, eg XXX_BASE
+ * @param sel periphral clock source
+ */
+void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
+{
+	uint8_t shift;
+	uint32_t mask;
+
+	switch (periph) {
+		case ADC1_BASE:
+			shift = RCC_CCIPR_ADCSEL_SHIFT;
+			mask = RCC_CCIPR_ADCSEL_MASK;
+			break;
+		case RNG_BASE:
+			shift = RCC_CCIPR_RNGSEL_SHIFT;
+			mask = RCC_CCIPR_RNGSEL_MASK;
+			break;
+		case TIM1_BASE:
+			shift = RCC_CCIPR_TIM1SEL_SHIFT;
+			mask = RCC_CCIPR_TIM1SEL_MASK;
+			break;
+		case LPTIM1_BASE:
+			shift = RCC_CCIPR_LPTIM1SEL_SHIFT;
+			mask = RCC_CCIPR_LPTIM1SEL_MASK;
+			break;
+		case LPTIM2_BASE:
+			shift = RCC_CCIPR_LPTIM2SEL_SHIFT;
+			mask = RCC_CCIPR_LPTIM2SEL_MASK;
+			break;
+		case CEC_BASE:
+			shift = RCC_CCIPR_CECSEL_SHIFT;
+			mask = RCC_CCIPR_CECSEL_MASK;
+			break;
+		case USART2_BASE:
+			shift = RCC_CCIPR_USART2SEL_SHIFT;
+			mask = RCC_CCIPR_USART2SEL_MASK;
+			break;
+		case USART1_BASE:
+			shift = RCC_CCIPR_USART1SEL_SHIFT;
+			mask = RCC_CCIPR_USART1SEL_MASK;
+			break;
+		default:
+			cm3_assert_not_reached();
+			return;
+	}
+
+	uint32_t reg32 = RCC_CCIPR & ~(mask << shift);
+	RCC_CCIPR = reg32 | (sel << shift);
+}
+
+/**@}*/
diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile
index cd3e27c3..857d3d5c 100644
--- a/lib/stm32/l0/Makefile
+++ b/lib/stm32/l0/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_stm32l0
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-#PREFIX		?= arm-elf
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -36,25 +34,26 @@ TGT_CFLAGS	+= $(STANDARD_FLAGS)
 
 ARFLAGS		= rcs
 
-OBJS		= gpio.o rcc.o desig.o
-OBJS		+= pwr_common_v1.o pwr_common_v2.o
-OBJS		+= timer_common_all.o
-OBJS		+= spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
-
-OBJS            += gpio_common_all.o gpio_common_f0234.o rcc_common_all.o
-OBJS		+= adc_common_v2.o
-OBJS		+= crs_common_all.o
-OBJS		+= dma_common_l1f013.o
-OBJS		+= exti_common_all.o
-OBJS		+= flash.o flash_common_all.o flash_common_l01.o
-OBJS		+= i2c_common_v2.o
-OBJS		+= rng_common_v1.o
-OBJS		+= usart_common_all.o usart_common_v2.o
-OBJS		+= iwdg_common_all.o
-OBJS            += rtc_common_l1f024.o
-
-OBJS            += usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS            += st_usbfs_core.o st_usbfs_v2.o
+OBJS += adc_common_v2.o
+OBJS += crs_common_all.o
+OBJS += desig.o
+OBJS += dma_common_l1f013.o dma_common_csel.o
+OBJS += exti_common_all.o
+OBJS += flash_common_all.o flash_common_l01.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += i2c_common_v2.o
+OBJS += iwdg_common_all.o
+OBJS += lptimer_common_all.o
+OBJS += pwr_common_v1.o pwr_common_v2.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rng_common_v1.o
+OBJS += rtc_common_l1f024.o
+OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
+OBJS += timer_common_all.o
+OBJS += usart_common_all.o usart_common_v2.o
+
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += st_usbfs_core.o st_usbfs_v2.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/stm32/l0/gpio.c b/lib/stm32/l0/gpio.c
deleted file mode 100644
index 9382ece2..00000000
--- a/lib/stm32/l0/gpio.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup gpio_file GPIO
- *
- * @ingroup STM32L0xx
- *
- * @brief <b>libopencm3 STM32L0xx General Purpose I/O</b>
- *
- * @version 1.0.0
- *
- * @date 8 September 2014
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/gpio.h>
diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c
index a6e398e2..39bdaff7 100644
--- a/lib/stm32/l0/rcc.c
+++ b/lib/stm32/l0/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32L0xx-rcc-file RCC
+/** @defgroup rcc_file RCC peripheral API
  *
- * @ingroup STM32L0xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32L0xx Reset and Clock Control</b>
  *
@@ -105,7 +105,7 @@ void rcc_osc_off(enum rcc_osc osc)
  * Clear the interrupt flag that was set when a clock oscillator became ready
  * to use.
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param[in] osc Oscillator ID
  */
 void rcc_osc_ready_int_clear(enum rcc_osc osc)
 {
@@ -137,7 +137,7 @@ void rcc_osc_ready_int_clear(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Enable the Oscillator Ready Interrupt
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param[in] osc Oscillator ID
  */
 void rcc_osc_ready_int_enable(enum rcc_osc osc)
 {
@@ -169,7 +169,7 @@ void rcc_osc_ready_int_enable(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Disable the Oscillator Ready Interrupt
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param[in] osc Oscillator ID
  */
 void rcc_osc_ready_int_disable(enum rcc_osc osc)
 {
@@ -201,7 +201,7 @@ void rcc_osc_ready_int_disable(enum rcc_osc osc)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Read the Oscillator Ready Interrupt Flag
  *
- * @param[in] osc enum ::osc_t. Oscillator ID
+ * @param[in] osc Oscillator ID
  * @returns int. Boolean value for flag set.
  */
 int rcc_osc_ready_int_flag(enum rcc_osc osc)
@@ -279,8 +279,7 @@ void rcc_set_hsi48_source_pll(void)
 /*---------------------------------------------------------------------------*/
 /** @brief RCC Set the Source for the System Clock.
  *
- * @param[in] osc enum ::osc_t. Oscillator ID. Only HSE, HSI16, MSI and PLL have
- * effect.
+ * @param[in] osc Oscillator ID. Only HSE, HSI16, MSI and PLL have effect.
  */
 
 void rcc_set_sysclk_source(enum rcc_osc osc)
@@ -310,7 +309,7 @@ void rcc_set_sysclk_source(enum rcc_osc osc)
  *
  * @note This only has effect when the PLL is disabled.
  *
- * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pmf
+ * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pmf
  */
 
 void rcc_set_pll_multiplier(uint32_t factor)
@@ -326,7 +325,7 @@ void rcc_set_pll_multiplier(uint32_t factor)
  *
  * @note This only has effect when the PLL is disabled.
  *
- * @param[in] mul Unsigned int32. PLL multiplication factor @ref rcc_cfgr_pdf
+ * @param[in] factor PLL multiplication factor @ref rcc_cfgr_pdf
  */
 
 void rcc_set_pll_divider(uint32_t factor)
@@ -354,7 +353,7 @@ void rcc_set_pll_source(uint32_t pllsrc)
  *
  * @note The APB1 clock frequency must not exceed 32MHz.
  *
- * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb1pre
+ * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb1pre
  */
 
 void rcc_set_ppre1(uint32_t ppre)
@@ -369,7 +368,7 @@ void rcc_set_ppre1(uint32_t ppre)
  *
  * @note The APB2 clock frequency must not exceed 32MHz.
  *
- * @param[in] ppre1 Unsigned int32. APB prescale factor @ref rcc_cfgr_apb2pre
+ * @param[in] ppre APB prescale factor @ref rcc_cfgr_apb2pre
  */
 
 void rcc_set_ppre2(uint32_t ppre)
@@ -391,9 +390,115 @@ void rcc_set_hpre(uint32_t hpre)
 	RCC_CFGR = reg | (hpre << RCC_CFGR_HPRE_SHIFT);
 }
 
-/**
- * Set up sysclock with PLL from HSI16
- * @param clock full struct with desired parameters
+/*---------------------------------------------------------------------------*/
+/** @brief Set the range of the MSI oscillator
+*
+ * @param msi_range desired range @ref rcc_icscr_msirange
+ */
+void rcc_set_msi_range(uint32_t msi_range)
+{
+	uint32_t reg32 = RCC_ICSCR & ~(RCC_ICSCR_MSIRANGE_MASK << RCC_ICSCR_MSIRANGE_SHIFT);
+	RCC_ICSCR = reg32 | (msi_range << RCC_ICSCR_MSIRANGE_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the LPTIM1 clock source
+*
+ * @param lptim1_sel peripheral clock source @ref rcc_ccpipr_lptim1sel
+ */
+void rcc_set_lptim1_sel(uint32_t lptim1_sel)
+{
+	RCC_CCIPR &= ~(RCC_CCIPR_LPTIM1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT);
+	RCC_CCIPR |= (lptim1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT);
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the LPUART1 clock source
+*
+ * @param lpuart1_sel periphral clock source @ref rcc_ccpipr_lpuart1sel
+ */
+void rcc_set_lpuart1_sel(uint32_t lpuart1_sel)
+{
+	RCC_CCIPR &= ~(RCC_CCIPR_LPUART1SEL_MASK << RCC_CCIPR_LPTIM1SEL_SHIFT);
+	RCC_CCIPR |= (lpuart1_sel << RCC_CCIPR_LPTIM1SEL_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the USART1 clock source
+*
+ * @param usart1_sel periphral clock source @ref rcc_ccpipr_usart1sel
+ */
+void rcc_set_usart1_sel(uint32_t usart1_sel)
+{
+	RCC_CCIPR &= ~(RCC_CCIPR_USART1SEL_MASK << RCC_CCIPR_USART1SEL_SHIFT);
+	RCC_CCIPR |= (usart1_sel << RCC_CCIPR_USART1SEL_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the USART2 clock source
+*
+ * @param usart2_sel periphral clock source @ref rcc_ccpipr_usartxsel
+ */
+void rcc_set_usart2_sel(uint32_t usart2_sel)
+{
+	RCC_CCIPR &= ~(RCC_CCIPR_USART2SEL_MASK << RCC_CCIPR_USART2SEL_SHIFT);
+	RCC_CCIPR |= (usart2_sel << RCC_CCIPR_USART2SEL_SHIFT);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the peripheral clock source
+ * @param periph peripheral of desire, eg XXX_BASE
+ * @param sel peripheral clock source
+ */
+void rcc_set_peripheral_clk_sel(uint32_t periph, uint32_t sel)
+{
+	uint8_t shift;
+	uint32_t mask;
+
+	switch (periph) {
+		case LPTIM1_BASE:
+			shift = RCC_CCIPR_LPTIM1SEL_SHIFT;
+			mask = RCC_CCIPR_LPTIM1SEL_MASK;
+			break;
+
+		case I2C3_BASE:
+			shift = RCC_CCIPR_I2C3SEL_SHIFT;
+			mask = RCC_CCIPR_I2C3SEL_MASK;
+			break;
+
+		case I2C1_BASE:
+			shift = RCC_CCIPR_I2C1SEL_SHIFT;
+			mask = RCC_CCIPR_I2C1SEL_MASK;
+			break;
+
+		case LPUART1_BASE:
+			shift = RCC_CCIPR_LPUART1SEL_SHIFT;
+			mask = RCC_CCIPR_LPUART1SEL_MASK;
+			break;
+
+		case USART2_BASE:
+			shift = RCC_CCIPR_USART2SEL_SHIFT;
+			mask = RCC_CCIPR_USART2SEL_MASK;
+			break;
+
+		case USART1_BASE:
+			shift = RCC_CCIPR_USART1SEL_SHIFT;
+			mask = RCC_CCIPR_USART1SEL_MASK;
+			break;
+
+		default:
+			return;
+	}
+
+	uint32_t reg32 = RCC_CCIPR & ~(mask << shift);
+	RCC_CCIPR = reg32 | (sel << shift);
+}
+
+/** @brief RCC Setup PLL and use it as Sysclk source.
+ *
+ * @param[in] clock full struct with desired parameters
+ *
  */
 void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
 {
@@ -422,6 +527,7 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
 	/* Set up the PLL */
 	rcc_set_pll_multiplier(clock->pll_mul);
 	rcc_set_pll_divider(clock->pll_div);
+	rcc_set_pll_source(clock->pll_source);
 
 	rcc_osc_on(RCC_PLL);
 	rcc_wait_for_osc_ready(RCC_PLL);
diff --git a/lib/stm32/l1/Makefile b/lib/stm32/l1/Makefile
index ec1ea928..b5853051 100644
--- a/lib/stm32/l1/Makefile
+++ b/lib/stm32/l1/Makefile
@@ -20,10 +20,8 @@
 LIBNAME		= libopencm3_stm32l1
 SRCLIBDIR	?= ../..
 
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -35,22 +33,27 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 # ARFLAGS	= rcsv
 ARFLAGS		= rcs
-OBJS		= desig.o flash.o rcc.o dma.o lcd.o
-OBJS		+= crc_common_all.o dac_common_all.o
-OBJS		+= dma_common_l1f013.o
-OBJS		+= flash_common_all.o flash_common_l01.o
-OBJS		+= gpio_common_all.o gpio_common_f0234.o
-OBJS		+= i2c_common_v1.o iwdg_common_all.o
-OBJS		+= pwr_common_v1.o pwr_common_v2.o rtc_common_l1f024.o
-OBJS		+= spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
-OBJS		+= timer_common_all.o
-OBJS		+= usart_common_all.o usart_common_f124.o
-OBJS		+= exti_common_all.o
-OBJS		+= rcc_common_all.o
-OBJS		+= adc.o adc_common_v1.o
+OBJS += adc.o adc_common_v1.o adc_common_v1_multi.o
+OBJS += flash.o
+OBJS += crc_common_all.o
+OBJS += dac_common_all.o
+OBJS += desig.o
+OBJS += dma_common_l1f013.o
+OBJS += exti_common_all.o
+OBJS += flash_common_all.o flash_common_l01.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += i2c_common_v1.o
+OBJS += iwdg_common_all.o
+OBJS += lcd.o
+OBJS += pwr_common_v1.o pwr_common_v2.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rtc_common_l1f024.o
+OBJS += spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
+OBJS += timer.o timer_common_all.o
+OBJS += usart_common_all.o usart_common_f124.o
 
-OBJS		+= usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS		+= st_usbfs_core.o st_usbfs_v1.o
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += st_usbfs_core.o st_usbfs_v1.o
 
 VPATH += ../../usb:../:../../cm3:../common
 
diff --git a/lib/stm32/l1/adc.c b/lib/stm32/l1/adc.c
index 1768437d..e2d3e4b8 100644
--- a/lib/stm32/l1/adc.c
+++ b/lib/stm32/l1/adc.c
@@ -29,23 +29,6 @@ LGPL License Terms @ref lgpl_license
 
 /**@{*/
 
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Power On
-
-If the ADC is in power-down mode then it is powered up. The application needs
-to wait a time of about 3 microseconds for stabilization before using the ADC.
-If the ADC is already on this function call will have no effect.
- * NOTE Common with F4 and F2
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_power_on(uint32_t adc)
-{
-	ADC_CR2(adc) |= ADC_CR2_ADON;
-}
-
-
 /*----------------------------------------------------------------------------*/
 
 /** @brief ADC Set the Sample Time for a Single Channel
@@ -102,97 +85,6 @@ void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time)
 	ADC_SMPR3(adc) = reg32;
 }
 
-/*----------------------------------------------------------------------------*/
-/** @brief ADC Enable The Temperature Sensor
-
-This enables both the sensor and the reference voltage measurements on channels
-16 and 17.
-
-*/
-void adc_enable_temperature_sensor()
-{
-	ADC_CCR |= ADC_CCR_TSVREFE;
-}
-
-/*----------------------------------------------------------------------------*/
-/** @brief ADC Disable The Temperature Sensor
-
-Disabling this will reduce power consumption from the sensor and the reference
-voltage measurements.
-
-*/
-void adc_disable_temperature_sensor()
-{
-	ADC_CCR &= ~ADC_CCR_TSVREFE;
-}
-
-/*----------------------------------------------------------------------------*/
-/** @brief ADC Disable an External Trigger for Regular Channels
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-*/
-
-void adc_disable_external_trigger_regular(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK;
-}
-
-/*----------------------------------------------------------------------------*/
-/** @brief ADC Disable an External Trigger for Injected Channels
-
-@param[in] adc Unsigned int32. ADC block base address @ref adc_reg_base.
-*/
-
-void adc_disable_external_trigger_injected(uint32_t adc)
-{
-	ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable an External Trigger for Regular Channels
-
-This enables an external trigger for set of defined regular channels, and sets
-the polarity of the trigger event: rising or falling edge or both. Note that if
-the trigger polarity is zero, triggering is disabled.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular
-@param[in] polarity Unsigned int32. Trigger polarity @ref
-adc_trigger_polarity_regular
-*/
-
-void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
-					 uint32_t polarity)
-{
-	uint32_t reg32 = ADC_CR2(adc);
-
-	reg32 &= ~(ADC_CR2_EXTSEL_MASK | ADC_CR2_EXTEN_MASK);
-	reg32 |= (trigger | polarity);
-	ADC_CR2(adc) = reg32;
-}
-
-/*---------------------------------------------------------------------------*/
-/** @brief ADC Enable an External Trigger for Injected Channels
-
-This enables an external trigger for set of defined injected channels, and sets
-the polarity of the trigger event: rising or falling edge or both.
-
-@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
-@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected
-@param[in] polarity Unsigned int32. Trigger polarity @ref
-adc_trigger_polarity_injected
-*/
-
-void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
-					  uint32_t polarity)
-{
-	uint32_t reg32 = ADC_CR2(adc);
-
-	reg32 &= ~(ADC_CR2_JEXTSEL_MASK | ADC_CR2_JEXTEN_MASK);
-	reg32 |= (trigger | polarity);
-	ADC_CR2(adc) = reg32;
-}
-
 /**@}*/
 
 
diff --git a/lib/stm32/l1/dac.c b/lib/stm32/l1/dac.c
deleted file mode 100644
index ed118b4d..00000000
--- a/lib/stm32/l1/dac.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dac_file DAC
-
-@ingroup STM32L1xx
-
-@brief <b>libopencm3 STM32L1xx DAC</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dac.h>
diff --git a/lib/stm32/l1/dma.c b/lib/stm32/l1/dma.c
deleted file mode 100644
index 6f4622d2..00000000
--- a/lib/stm32/l1/dma.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup dma_file DMA
- *
- * @ingroup STM32L1xx
- *
- * @brief <b>libopencm3 STM32L1xx DMA</b>
- *
- * @version 1.0.0
- *
- * @date 10 July 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/dma.h>
diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c
index 5e176b05..dfd90d25 100644
--- a/lib/stm32/l1/flash.c
+++ b/lib/stm32/l1/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32L1xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32L1xx FLASH</b>
  *
diff --git a/lib/stm32/l1/gpio.c b/lib/stm32/l1/gpio.c
deleted file mode 100644
index 46ea658a..00000000
--- a/lib/stm32/l1/gpio.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup gpio_file GPIO
-
-@ingroup STM32L1xx
-
-@brief <b>libopencm3 STM32L1xx General Purpose I/O</b>
-
-@version 1.0.0
-
-@date 18 August 2012
-
-LGPL License Terms @ref lgpl_license
-*/
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/gpio.h>
diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c
index e9f7bd68..44eac07b 100644
--- a/lib/stm32/l1/rcc.c
+++ b/lib/stm32/l1/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup STM32L1xx-rcc-file RCC
+/** @defgroup rcc_file RCC peripheral API
 
-@ingroup STM32L1xx
+@ingroup peripheral_apis
 
 @brief <b>libopencm3 STM32L1xx Reset and Clock Control</b>
 
@@ -535,6 +535,10 @@ void rcc_clock_setup_pll(const struct rcc_clock_scale *clock)
 	flash_prefetch_enable();
 	flash_set_ws(clock->flash_waitstates);
 
+	/* Disable PLL oscillator before changing its configuration. */
+	rcc_osc_off(RCC_PLL);
+
+	/* Configure the PLL oscillator. */
 	rcc_set_pll_configuration(clock->pll_source, clock->pll_mul,
 				  clock->pll_div);
 
diff --git a/lib/stm32/l1/rtc.c b/lib/stm32/l1/rtc.c
deleted file mode 100644
index 5628aa7e..00000000
--- a/lib/stm32/l1/rtc.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/** @defgroup rtc_file RTC
- *
- * @ingroup STM32L1xx
- *
- * @brief <b>libopencm3 STM32L1xx RTC</b>
- *
- * @version 1.0.0
- *
- * @date 4 March 2013
- *
- * LGPL License Terms @ref lgpl_license
- */
-
-/*
- * This file is part of the libopencm3 project.
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <libopencm3/stm32/rtc.h>
diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c
index ab69c622..43f8d541 100644
--- a/lib/stm32/l1/timer.c
+++ b/lib/stm32/l1/timer.c
@@ -1,7 +1,5 @@
-/** @defgroup timer_file Timers
-
-@ingroup STM32L1xx
-
+/** @defgroup timer_file TIMER peripheral API
+@ingroup peripheral_apis
 @brief <b>libopencm3 STM32L1xx Timers</b>
 
 @version 1.0.0
@@ -30,18 +28,17 @@
  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-/**@{*/
-
 #include <libopencm3/stm32/timer.h>
 
+/**@{*/
+
 /*---------------------------------------------------------------------------*/
 /** @brief Set Timer Option
 
 Set timer options register on TIM2 or TIM3, used for trigger remapping.
 
 @param[in] timer_peripheral Unsigned int32. Timer register address base
-@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3:
-@ref tim3_opt_trigger_remap.
+@param[in] option Desired option @ref tim2_opt_trigger_remap and @ref tim3_opt_trigger_remap
 */
 
 void timer_set_option(uint32_t timer_peripheral, uint32_t option)
diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile
index a2748535..6a1594ff 100644
--- a/lib/stm32/l4/Makefile
+++ b/lib/stm32/l4/Makefile
@@ -21,10 +21,8 @@ LIBNAME		= libopencm3_stm32l4
 SRCLIBDIR	?= ../..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX	        ?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -37,28 +35,28 @@ TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 ARFLAGS		= rcs
 
-# Specific objs
-OBJS		= adc.o flash.o pwr.o rcc.o
-
-# common/shared objs
-OBJS            += rcc_common_all.o
-OBJS            += gpio_common_all.o gpio_common_f0234.o
-OBJS            += exti_common_all.o
-OBJS            += adc_common_v2.o adc_common_v2_multi.o
-OBJS            += crc_common_all.o crc_v2.o
-OBJS            += crs_common_all.o
-OBJS            += flash_common_all.o flash_common_f.o flash_common_idcache.o
-OBJS            += rng_common_v1.o
-OBJS            += timer_common_all.o
-OBJS            += i2c_common_v2.o
-OBJS            += usart_common_all.o usart_common_v2.o
-OBJS            += dma_common_l1f013.o
-OBJS            += iwdg_common_all.o
-OBJS            += rtc_common_l1f024.o
-OBJS            += spi_common_all.o spi_common_v2.o
+OBJS += adc.o adc_common_v2.o adc_common_v2_multi.o
+OBJS += can.o
+OBJS += crc_common_all.o crc_v2.o
+OBJS += crs_common_all.o
+OBJS += dac_common_all.o
+OBJS += dma_common_l1f013.o dma_common_csel.o
+OBJS += exti_common_all.o
+OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_idcache.o
+OBJS += gpio_common_all.o gpio_common_f0234.o
+OBJS += i2c_common_v2.o
+OBJS += iwdg_common_all.o
+OBJS += lptimer_common_all.o
+OBJS += pwr.o
+OBJS += rcc.o rcc_common_all.o
+OBJS += rng_common_v1.o
+OBJS += rtc_common_l1f024.o
+OBJS += spi_common_all.o spi_common_v2.o
+OBJS += timer_common_all.o
+OBJS += usart_common_all.o usart_common_v2.o
 
-OBJS            += usb.o usb_control.o usb_standard.o usb_msc.o
-OBJS            += st_usbfs_core.o st_usbfs_v2.o
+OBJS += usb.o usb_control.o usb_standard.o usb_msc.o
+OBJS += st_usbfs_core.o st_usbfs_v2.o
 
 VPATH += ../../usb:../:../../cm3:../common
 VPATH += ../../ethernet
diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c
index 58374b29..16007ee6 100644
--- a/lib/stm32/l4/flash.c
+++ b/lib/stm32/l4/flash.c
@@ -1,6 +1,6 @@
-/** @defgroup flash_file FLASH
+/** @defgroup flash_file FLASH peripheral API
  *
- * @ingroup STM32L4xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32L4xx FLASH</b>
  *
@@ -108,15 +108,16 @@ void flash_lock_option_bytes(void)
 	FLASH_CR |= FLASH_CR_OPTLOCK;
 }
 
-/** @brief Program a 32 bit Word to FLASH
- * This performs all operations necessary to program a 32 bit word to FLASH
- * memory. The program error flag should be checked separately for the event
- * that memory was not properly erased.
+/** @brief Program a 64 bit word to FLASH
+ *
+ * This performs all operations necessary to program a 64 bit word to FLASH memory.
+ * The program error flag should be checked separately for the event that memory
+ * was not properly erased.
  *
  * @param[in] address Starting address in Flash.
- * @param[in] data word to write
+ * @param[in] data Double word to write
  */
-void flash_program_word(uint32_t address, uint32_t data)
+void flash_program_double_word(uint32_t address, uint64_t data)
 {
 	/* Ensure that all flash operations are complete. */
 	flash_wait_for_last_operation();
@@ -124,8 +125,9 @@ void flash_program_word(uint32_t address, uint32_t data)
 	/* Enable writes to flash. */
 	FLASH_CR |= FLASH_CR_PG;
 
-	/* Program the word. */
-	MMIO32(address) = data;
+	/* Program the each word separately. */
+	MMIO32(address) = (uint32_t)data;
+	MMIO32(address+4) = (uint32_t)(data >> 32);
 
 	/* Wait for the write to complete. */
 	flash_wait_for_last_operation();
@@ -140,16 +142,12 @@ void flash_program_word(uint32_t address, uint32_t data)
  * memory was not properly erased.
  * @param[in] address Starting address in Flash.
  * @param[in] data Pointer to start of data block.
- * @param[in] len Length of data block.
+ * @param[in] len Length of data block in bytes (multiple of 8).
  */
 void flash_program(uint32_t address, uint8_t *data, uint32_t len)
 {
-	/* TODO: Use dword and word size program operations where possible for
-	 * turbo speed.
-	 */
-	uint32_t i;
-	for (i = 0; i < len; i++) {
-		flash_program_word(address+i, data[i]);
+	for (uint32_t i = 0; i < len; i += 8) {
+		flash_program_double_word(address+i, *(uint64_t*)(data + i));
 	}
 }
 
@@ -198,8 +196,8 @@ void flash_program_option_bytes(uint32_t data)
 		flash_unlock_option_bytes();
 	}
 
-	FLASH_OPTR = data & ~0x3;
-	FLASH_OPTR |= FLASH_CR_OPTSTRT;
+	FLASH_OPTR = data;
+	FLASH_CR |= FLASH_CR_OPTSTRT;
 	flash_wait_for_last_operation();
 }
 /**@}*/
diff --git a/lib/stm32/l4/pwr.c b/lib/stm32/l4/pwr.c
index 7bfc8361..e6bd877a 100644
--- a/lib/stm32/l4/pwr.c
+++ b/lib/stm32/l4/pwr.c
@@ -1,6 +1,6 @@
-/** @defgroup pwr_file PWR
+/** @defgroup pwr_file PWR peripheral API
  *
- * @ingroup STM32L4xx
+ * @ingroup peripheral_apis
  *
  * @brief <b>libopencm3 STM32L4xx Power Control</b>
  *
@@ -52,4 +52,24 @@ void pwr_set_vos_scale(enum pwr_vos_scale scale)
 	}
 	PWR_CR1 = reg32;
 }
+
+/** Disable Backup Domain Write Protection
+ *
+ * This allows backup domain registers to be changed. These registers are write
+ * protected after a reset.
+ */
+void pwr_disable_backup_domain_write_protect(void)
+{
+	PWR_CR1 |= PWR_CR1_DBP;
+}
+
+/** Re-enable Backup Domain Write Protection
+ *
+ * This protects backup domain registers from inadvertent change.
+ */
+void pwr_enable_backup_domain_write_protect(void)
+{
+	PWR_CR1 &= ~PWR_CR1_DBP;
+}
+
 /**@}*/
diff --git a/lib/stm32/l4/rcc.c b/lib/stm32/l4/rcc.c
index d1fb0c48..1d3e3472 100644
--- a/lib/stm32/l4/rcc.c
+++ b/lib/stm32/l4/rcc.c
@@ -1,6 +1,6 @@
-/** @defgroup rcc_file RCC
+/** @defgroup rcc_file RCC peripheral API
  *
- * @ingroup STM32L4xx
+ * @ingroup peripheral_apis
  *
  * @section rcc_l4_api_ex Reset and Clock Control API.
  *
@@ -369,4 +369,69 @@ void rcc_set_msi_range_standby(uint32_t msi_range)
 	RCC_CSR = reg;
 }
 
+/** Enable PLL Output
+ *
+ *	- P (RCC_PLLCFGR_PLLPEN)
+ *	- Q (RCC_PLLCFGR_PLLQEN)
+ *	- R (RCC_PLLCFGR_PLLREN)
+ *
+ * @param pllout One or more of the definitions above
+ */
+void rcc_pll_output_enable(uint32_t pllout)
+{
+	RCC_PLLCFGR |= pllout;
+}
+
+/** Set clock source for 48MHz clock
+ *
+ * The 48 MHz clock is derived from one of the four following sources:
+ *	- main PLL VCO (RCC_CCIPR_CLK48SEL_PLL)
+ *	- PLLSAI1 VCO (RCC_CCIPR_CLK48SEL_PLLSAI1Q)
+ *	- MSI clock (RCC_CCIPR_CLK48SEL_MSI)
+ *	- HSI48 internal oscillator (RCC_CCIPR_CLK48SEL_HSI48)
+ *
+ * @param clksel One of the definitions above
+ */
+void rcc_set_clock48_source(uint32_t clksel)
+{
+	RCC_CCIPR &= ~(RCC_CCIPR_CLK48SEL_MASK << RCC_CCIPR_CLK48SEL_SHIFT);
+	RCC_CCIPR |= (clksel << RCC_CCIPR_CLK48SEL_SHIFT);
+}
+
+
+/** Enable the RTC clock */
+void rcc_enable_rtc_clock(void)
+{
+	RCC_BDCR |= RCC_BDCR_RTCEN;
+}
+
+/** Disable the RTC clock */
+void rcc_disable_rtc_clock(void)
+{
+	RCC_BDCR &= ~RCC_BDCR_RTCEN;
+}
+
+/** Set the source for the RTC clock
+ * @param[in] clk ::rcc_osc. RTC clock source. Only HSE/32, LSE and LSI.
+ */
+void rcc_set_rtc_clock_source(enum rcc_osc clk)
+{
+	RCC_BDCR &= ~(RCC_BDCR_RTCSEL_MASK << RCC_BDCR_RTCSEL_SHIFT);
+
+	switch (clk) {
+	case RCC_HSE:
+		RCC_BDCR |= (RCC_BDCR_RTCSEL_HSEDIV32 << RCC_BDCR_RTCSEL_SHIFT);
+		break;
+	case RCC_LSE:
+		RCC_BDCR |= (RCC_BDCR_RTCSEL_LSE << RCC_BDCR_RTCSEL_SHIFT);
+		break;
+	case RCC_LSI:
+		RCC_BDCR |= (RCC_BDCR_RTCSEL_LSI << RCC_BDCR_RTCSEL_SHIFT);
+		break;
+	default:
+		/* none selected */
+		break;
+	}
+}
+
 /**@}*/
diff --git a/lib/swm050/Makefile b/lib/swm050/Makefile
new file mode 100644
index 00000000..977f5f74
--- /dev/null
+++ b/lib/swm050/Makefile
@@ -0,0 +1,40 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME		= libopencm3_swm050
+SRCLIBDIR	?= ..
+
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
+TGT_CFLAGS	= -Os \
+		  -Wall -Wextra -Wimplicit-function-declaration \
+		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
+		  -Wundef -Wshadow \
+		  -I../../include -fno-common \
+		  -mcpu=cortex-m0 $(FP_FLAGS) -mthumb -Wstrict-prototypes \
+		  -ffunction-sections -fdata-sections -MD -DSWM050
+TGT_CFLAGS      += $(DEBUG_FLAGS)
+TGT_CFLAGS	+= $(STANDARD_FLAGS)
+ARFLAGS		= rcs
+
+OBJS += gpio.o
+
+VPATH += ../cm3
+
+include ../Makefile.include
diff --git a/lib/swm050/gpio.c b/lib/swm050/gpio.c
new file mode 100644
index 00000000..fdf50996
--- /dev/null
+++ b/lib/swm050/gpio.c
@@ -0,0 +1,197 @@
+/** @addtogroup gpio_file GPIO peripheral API
+ * @ingroup peripheral_apis
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/swm050/gpio.h>
+
+/**@{*/
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set a Group of Pins
+
+Set one or more pins of GPIO to 1. Please note that this chip doesn't support
+atomic pin setting.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+*/
+void gpio_set(uint16_t gpios)
+{
+	GPIO_DATA |= gpios;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Clear a Group of Pins
+
+Set one or more pins of GPIO to 0. Please note that this chip doesn't support
+atomic pin setting.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+*/
+void gpio_clear(uint16_t gpios)
+{
+	GPIO_DATA &= ~gpios;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Read a Group of Pins.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	    If multiple pins are to be read, use bitwise OR '|' to separate
+	    them.
+@return The pin values as a bitfield. The bit position of the pin
+	value returned corresponds to the pin number.
+*/
+uint16_t gpio_get(uint16_t gpios)
+{
+	return GPIO_EXT & gpios;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Toggle a Group of Pins
+
+Toggle one or more pins of GPIO. The non-toggled pins are not affected.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+*/
+void gpio_toggle(uint16_t gpios)
+{
+	uint32_t curr_status = GPIO_DATA & gpios;
+	GPIO_DATA = (GPIO_DATA & (~gpios)) | (~curr_status);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the direction of a Group of Pins to Input
+
+Set the direction of one or more pins of GPIO to input.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+*/
+void gpio_input(uint16_t gpios)
+{
+	GPIO_DIR &= ~gpios;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Set the direction of a Group of Pins to Output
+
+Set the direction of one or more pins of GPIO to output.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+*/
+void gpio_output(uint16_t gpios)
+{
+	GPIO_DIR |= gpios;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Select the alternative function of a Group of Pins
+
+Select the alternative function of one or more pins of GPIO.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+@param[in] af_en Whether alternative function is selected
+*/
+void gpio_sel_af(uint16_t gpios, bool af_en)
+{
+	if (gpios & GPIO0) {
+		GPIO_SEL = (GPIO_SEL & (~0x3)) | (af_en ? 0x1 : 0x0);
+	}
+	if (gpios & GPIO1) {
+		GPIO_SEL = (GPIO_SEL & (~0xc)) | (af_en ? 0x4 : 0x0);
+	}
+	if (gpios & GPIO2) {
+		GPIO_SEL = (GPIO_SEL & (~0x30)) | (af_en ? 0x10 : 0x0);
+	}
+	if (gpios & GPIO7) {
+		GPIO_SEL = (GPIO_SEL & (~0xc000)) | (af_en ? 0x4000 : 0x0);
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable the internal pull-up of a Group of Pins
+
+Enable or disable the internal pull-up of one or more pins of GPIO.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+@param[in] en Bool. Whether pull-up is enabled
+*/
+void gpio_pullup(uint16_t gpios, bool en)
+{
+	if (en) {
+		GPIO_PULLUP |= gpios;
+	} else {
+		GPIO_PULLUP &= ~gpios;
+	}
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief Enable the input function of a Group of Pins
+
+Enable or disable the input function of one or more pins of GPIO. Disabling
+the input function of pins decreases the power usage of the MCU.
+
+@param[in] gpios Pin identifiers @ref gpio_pin_id
+	     If multiple pins are to be changed, use bitwise OR '|' to separate
+	     them.
+@param[in] en true to enable input function.
+*/
+void gpio_in_en(uint16_t gpios, bool en)
+{
+	if (en) {
+		GPIO_INEN &= ~gpios;
+	} else {
+		GPIO_INEN |= gpios;
+	}
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief Select the SWD function of GPIO 1/2
+
+Enable or disable the SWD debugging port at GPIO 1/2. When SWD debugging port
+is enabled, GPIO and AF of the SWD pins will be both unavailable.
+
+@param[in] en true to enable SWD.
+*/
+void gpio_sel_swd(bool en)
+{
+	if (en) {
+		SWD_SEL = 1;
+	} else {
+		SWD_SEL = 0;
+	}
+}
+
+/**@}*/
diff --git a/lib/usb/usb_efm32.c b/lib/usb/usb_efm32.c
index 5768947c..4f7fa254 100644
--- a/lib/usb/usb_efm32.c
+++ b/lib/usb/usb_efm32.c
@@ -1,3 +1,9 @@
+/** @addtogroup usb_file USB peripheral API
+ * @ingroup peripheral_apis
+ *
+ * @sa usb_defines
+ * @copyright See @ref lgpl_license
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -26,6 +32,8 @@
 #include <libopencm3/usb/usbd.h>
 #include "usb_private.h"
 
+/**@{*/
+
 /* Receive FIFO size in 32-bit words. */
 #define RX_FIFO_SIZE 256
 
@@ -424,3 +432,5 @@ const struct _usbd_driver efm32lg_usb_driver = {
 	.set_address_before_status = 1,
 	.rx_fifo_size = RX_FIFO_SIZE,
 };
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/usb/usb_efm32hg.c b/lib/usb/usb_efm32hg.c
index 96f22c1e..5459566e 100644
--- a/lib/usb/usb_efm32hg.c
+++ b/lib/usb/usb_efm32hg.c
@@ -1,3 +1,13 @@
+/** @addtogroup usb_file USB peripheral API
+ * @ingroup peripheral_apis
+ *
+ * @brief USB Peripheral for Happy Gecko
+ *
+ * The Happy Gecko uses the "standard" usb_dwc_otg core.
+ *
+ * @sa usb_defines
+ * @copyright See @ref lgpl_license
+ */
 /*
  * This file is part of the libopencm3 project.
  *
@@ -28,6 +38,8 @@
 #include "usb_private.h"
 #include "usb_dwc_common.h"
 
+/**@{*/
+
 /* Receive FIFO size in 32-bit words. */
 #define RX_FIFO_SIZE 256
 
@@ -124,3 +136,5 @@ const struct _usbd_driver efm32hg_usb_driver = {
 	.set_address_before_status = 1,
 	.rx_fifo_size = RX_FIFO_SIZE,
 };
+
+/**@}*/
\ No newline at end of file
diff --git a/lib/vf6xx/Makefile b/lib/vf6xx/Makefile
index d87247be..c8bfd2a3 100644
--- a/lib/vf6xx/Makefile
+++ b/lib/vf6xx/Makefile
@@ -22,10 +22,8 @@ LIBNAME		= libopencm3_vf6xx
 SRCLIBDIR	?= ..
 
 FP_FLAGS	?= -mfloat-abi=hard -mfpu=fpv4-sp-d16
-PREFIX		?= arm-none-eabi
-
-CC		= $(PREFIX)-gcc
-AR		= $(PREFIX)-ar
+CC		= $(PREFIX)gcc
+AR		= $(PREFIX)ar
 TGT_CFLAGS	= -Os \
 		  -Wall -Wextra -Wimplicit-function-declaration \
 		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
@@ -36,7 +34,11 @@ TGT_CFLAGS	= -Os \
 TGT_CFLAGS      += $(DEBUG_FLAGS)
 TGT_CFLAGS	+= $(STANDARD_FLAGS)
 ARFLAGS		= rcs
-OBJS		= ccm.o uart.o gpio.o iomuxc.o
+
+OBJS += ccm.o
+OBJS += gpio.o
+OBJS += iomuxc.o
+OBJS += uart.o
 
 VPATH += ../cm3