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path: root/include/libopencm3/stm32
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2019-09-21Merge remote-tracking branch 'upstream/master'D. Lisin
# Conflicts: # lib/stm32/f2/Makefile # lib/stm32/f4/Makefile
2019-08-28stm32g0: use proper register for gpio peripheral clock sleep enable.Guillaume Revaillot
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2019-08-28stm32g0: memorymap: get rid of apb1/apb2 reference, device only has one apb.Guillaume Revaillot
I apparently based memorymap.h on previously written header without noticing that g0 has only one apb despite a big hole in the memory space and addresses matching usual apb1/apb2 split..
2019-08-28stm32f4: doc: f4 are cortex m4f basedGuillaume Revaillot
2019-08-27stm32g0: fix bad typos in memorymap, impacting tim1 and tim15-17.Guillaume Revaillot
2019-07-06doc: stm32: adc: upgrade common_v2 documentationGuillaume Revaillot
add register grouping, fixup comment have them pickedup by doxygen, align style and masks.
2019-07-05stm32: lptim: add base supportGuillaume Revaillot
Add basically what's needed to have some minimal but usefull subset of function for a timer: irqs, compare, period, out polarity, enable/disable and start.
2019-07-05stm32g0: lptim: add additional cr bits and cfgr2 reg.Guillaume Revaillot
2019-07-05stm32: lptimer: enable lptimer.h usage on f4,f7,l4 and g0 chips.Guillaume Revaillot
2019-07-05stm32: extract l0 lptimer stuff from timer.h to common lptimer.hGuillaume Revaillot
lptimer peripheral is present on f4,f7,l0,l4,g0,g4 and prob others. Extract content from stm32l0 timer.h and make it usable by other chips.
2019-07-02stm32f4: lptim1 sits at 0x40002400 on stm32f410, update memorymapGuillaume Revaillot
2019-06-27doc: stm32f0: rcc: add missing groups for pll factors and sourcesKarl Palsson
2019-06-26doc: stm32f3: adc: register base addresses had landed outside a groupKarl Palsson
2019-06-26doc: stm32f7: rcc: add missing top level groupsKarl Palsson
2019-06-18doc: stm32l1: timer: fix params, missing groupingsKarl Palsson
2019-06-17stm32: dma: add dma_set_channel_request to ease dma cselr usage.Guillaume Revaillot
2019-06-17stm32l0: dma: include dma_cselr, present on l0x1-2-3.Guillaume Revaillot
2019-06-17stm32: dma: cselr: factorize register definition.Guillaume Revaillot
F09x and L4 share the same cselr register, as well as some L0s, factorize definitions in a new shared header and add helpers. fyi, that register allows to redefine dma channel peripheral mapping - see device datasheet for mapping tables.
2019-06-16doc: stm32: timer: remove redundant groupings and consistent namesKarl Palsson
2019-06-16doc: stm32l0: fix doxygen groupings.Karl Palsson
Makes some @ingroup directives redundant.
2019-06-16stm32: l0: timer/lptimer: doc+Guillaume Revaillot
better doc for l0 lptimer registers, add mask.
2019-06-13stm32g0: exti doc fixupGuillaume Revaillot
2019-06-13stm32g0: add timer.Guillaume Revaillot
Only tim2/3/7/14 have been really tested yet - but the others should work as well.
2019-06-13stm32g0: add crc.Guillaume Revaillot
Regular crc-v2 peripheral, except that CRC_IDR is now 32bit wide - but not used.
2019-06-13stm32g0: add rng.Guillaume Revaillot
Regular rng peripheral, with one additional bit : clock error detection apparently available on l4 chips). Curiously, Clock error detection is _disabled_ when bit is set, but bit is cleared by default, so peripheral / clock error detection behaves like all other chips.. NB: RNG need proper rcc_ccicr_rngsel bits set to work, no clock is set by default. Note also that on that chip fRNGCLK must be higher than fHCLK/32
2019-06-13stm32g0: add i2c.Guillaume Revaillot
Regular i2c peripheral. Partially tested as i had no i2c slave on hand, but i can see i2c on my scope..
2019-06-13stm32g0: add spi.Guillaume Revaillot
classic "common" spi + frf bit spi peripheral. As for i2c, i could only check signals on scope, no spi slave to check, but looks ok.
2019-06-13stm32g0: add usart.Guillaume Revaillot
2019-06-13stm32g0: add iwdg.Guillaume Revaillot
regular v2 iwdg.
2019-06-13stm32l4: add common DAC supportEric Van Albert
Replace the DAC1_BASE style, only used on l4 with the standard DAC_BASE used on all other targets. Reviewed-by: Karl Palsson <karlp@tweak.net.au>
2019-06-13doc: fix trivial missing trailers or typosKarl Palsson
2019-06-13doc: stm32l0: rcc: add groups requested by existing docsKarl Palsson
And cleanse the arguments to all match the docs.
2019-06-13doc: stm32l0: rcc: add groups and tags for bus prescalersKarl Palsson
2019-06-13doc: stm32f4: crypto trivial closing tag fixKarl Palsson
2019-06-13doc: stm32: exti-v1: fix conditionals, add registersKarl Palsson
Fixes some missing definitions. cond/endcond is hard to get right sometimes!
2019-06-13doc:stm32: usart: fix grouping and heirarchy of base addrsKarl Palsson
They were always landing on the top level, or not even present.
2019-06-13doc: stm32f0: rcc: add groups and tags for bus prescalersKarl Palsson
2019-06-13doc: stm32: crc-v2 fix up markup for doxygenKarl Palsson
Eliminates errors, fixes groupings, adds missing groupings.
2019-06-13doc: stm32g0: rcc: add groupings for periph resetsKarl Palsson
2019-06-13doc: stm32f7: rcc: add groupings for periph resetsKarl Palsson
2019-06-13doc: stm32f4: rcc: add groupings for periph resetsKarl Palsson
2019-06-13doc: stm32f3: rcc: add groupings for periph resetsKarl Palsson
2019-06-13doc: stm32l4: rcc: add groupings for periph resetsKarl Palsson
As we did with f2, use a parent grouping to contain the different sets of APB1 fields.
2019-06-13doc: stm32l0: rcc: add groupings for periph resetsKarl Palsson
2019-06-13doc: stm32f2: rcc: add groupings for periph resetsKarl Palsson
We use a parent grouping to make the generic "AHB" groups work, even though F2 and many later families have AHB1, AHB2 and AHB3
2019-06-13doc: stm32l1: rcc: add groupings for periph resetsKarl Palsson
2019-06-13doc: stm32f0: rcc: add groupings for periph resetsKarl Palsson
As done earlier for other families, makes the doxygen linking working properly.
2019-06-10doc: restore targets as pages.Karl Palsson
You can't have two mainpage items, and the second was just being ignored. This restores them, which makes the left side list longer, which we may or may not like, but it's at least how it was documented to be.
2019-06-04stm32l0: rcc: add rcc_set_peripheral_clk_sel(periph, sel)Guillaume Revaillot
2019-06-04stm32l0: rcc: add peripherals clock source selection helpers.Guillaume Revaillot
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