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author | Rhishikesh Agashe <Rhishikesh.Agashe@imgtec.com> | 2015-10-07 20:55:12 +0300 |
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committer | Jean-Marc Valin <jmvalin@jmvalin.ca> | 2015-10-07 20:55:12 +0300 |
commit | c9c2035355b8e028d1b62992b277b0c376634cf3 (patch) | |
tree | 36a7a9e3a0eb0285b47870f14643bf48d15db823 /celt/mips/celt_mipsr1.h | |
parent | 50d6701e2a0352954026caf40383d10dad3a2be4 (diff) |
Fixes compile problems for MIPS
Brings MIPS in sync with the ARM/SSE optimizations that added "arch" parameters.
Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>
Diffstat (limited to 'celt/mips/celt_mipsr1.h')
-rw-r--r-- | celt/mips/celt_mipsr1.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/celt/mips/celt_mipsr1.h b/celt/mips/celt_mipsr1.h index 7915d596..e85661a6 100644 --- a/celt/mips/celt_mipsr1.h +++ b/celt/mips/celt_mipsr1.h @@ -61,6 +61,8 @@ void comb_filter(opus_val32 *y, opus_val32 *x, int T0, int T1, int N, int i; opus_val32 x0, x1, x2, x3, x4; + (void)arch; + /* printf ("%d %d %f %f\n", T0, T1, g0, g1); */ opus_val16 g00, g01, g02, g10, g11, g12; static const opus_val16 gains[3][3] = { |