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| author | Timothy B. Terriberry <territim@amazon.com> | 2022-07-07 01:23:12 +0300 |
|---|---|---|
| committer | Timothy B. Terriberry <territim@amazon.com> | 2022-07-10 07:18:52 +0300 |
| commit | 08088411259056f63774befb2d00951fdd5c46ba (patch) | |
| tree | a501ceff6a61d14806d6edc6d38004e96fbeb87d /celt | |
| parent | 71fb707875b95672f0cd1cb153c890eff4219720 (diff) | |
Only build platform RTCD sources when enabled.
To avoid issues with empty compilation units.
Diffstat (limited to 'celt')
| -rw-r--r-- | celt/meson.build | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/celt/meson.build b/celt/meson.build index 370ea1fe..ad95d949 100644 --- a/celt/meson.build +++ b/celt/meson.build @@ -10,6 +10,10 @@ celt_neon_intr_sources = sources['CELT_SOURCES_ARM_NEON_INTR'] celt_static_libs = [] +if host_cpu_family in ['x86', 'x86_64'] and opus_conf.has('OPUS_HAVE_RTCD') + celt_sources += sources['CELT_SOURCES_X86_RTCD'] +endif + foreach intr_name : ['sse', 'sse2', 'sse4_1', 'neon_intr'] have_intr = get_variable('have_' + intr_name) if not have_intr @@ -30,7 +34,9 @@ if (intrinsics_support.length() + asm_optimization.length() + inline_optimizatio endif if host_cpu_family in ['arm', 'aarch64'] and have_arm_intrinsics_or_asm - celt_sources += sources['CELT_SOURCES_ARM'] + if opus_conf.has('OPUS_HAVE_RTCD') + celt_sources += sources['CELT_SOURCES_ARM_RTCD'] + endif if have_arm_ne10 celt_sources += sources['CELT_SOURCES_ARM_NE10'] endif |