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authorRadu Velea <radu.velea@intel.com>2015-10-27 13:21:36 +0300
committerTimothy B. Terriberry <tterribe@xiph.org>2015-11-05 12:23:05 +0300
commit1632152b83b8ab4e28393bca94450796b71b0201 (patch)
tree9d70a379010a47f5c203bad841dca40257619e14 /configure.ac
parentbb0e1e0d6f6b112160a10de84ba368689c41c1bb (diff)
Adding AVX config switches
Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
Diffstat (limited to 'configure.ac')
-rw-r--r--configure.ac38
1 files changed, 37 insertions, 1 deletions
diff --git a/configure.ac b/configure.ac
index bb838c0b..74aa2f48 100644
--- a/configure.ac
+++ b/configure.ac
@@ -351,10 +351,12 @@ AM_CONDITIONAL([OPUS_ARM_EXTERNAL_ASM],
AM_CONDITIONAL([HAVE_SSE], [false])
AM_CONDITIONAL([HAVE_SSE2], [false])
AM_CONDITIONAL([HAVE_SSE4_1], [false])
+AM_CONDITIONAL([HAVE_AVX], [false])
m4_define([DEFAULT_X86_SSE_CFLAGS], [-msse])
m4_define([DEFAULT_X86_SSE2_CFLAGS], [-msse2])
m4_define([DEFAULT_X86_SSE4_1_CFLAGS], [-msse4.1])
+m4_define([DEFAULT_X86_AVX_CFLAGS], [-mavx])
m4_define([DEFAULT_ARM_NEON_INTR_CFLAGS], [-mfpu=neon])
# With GCC on ARM32 softfp architectures (e.g. Android, or older Ubuntu) you need to specify
# -mfloat-abi=softfp for -mfpu=neon to work. However, on ARM32 hardfp architectures (e.g. newer Ubuntu),
@@ -371,11 +373,13 @@ AS_CASE([$host],
AC_ARG_VAR([X86_SSE_CFLAGS], [C compiler flags to compile SSE intrinsics @<:@default=]DEFAULT_X86_SSE_CFLAGS[@:>@])
AC_ARG_VAR([X86_SSE2_CFLAGS], [C compiler flags to compile SSE2 intrinsics @<:@default=]DEFAULT_X86_SSE2_CFLAGS[@:>@])
AC_ARG_VAR([X86_SSE4_1_CFLAGS], [C compiler flags to compile SSE4.1 intrinsics @<:@default=]DEFAULT_X86_SSE4_1_CFLAGS[@:>@])
+AC_ARG_VAR([X86_AVX_CFLAGS], [C compiler flags to compile AVX intrinsics @<:@default=]DEFAULT_X86_AVX_CFLAGS[@:>@])
AC_ARG_VAR([ARM_NEON_INTR_CFLAGS], [C compiler flags to compile ARM NEON intrinsics @<:@default=]DEFAULT_ARM_NEON_INTR_CFLAGS / DEFAULT_ARM_NEON_SOFTFP_INTR_CFLAGS[@:>@])
AS_VAR_SET_IF([X86_SSE_CFLAGS], [], [AS_VAR_SET([X86_SSE_CFLAGS], "DEFAULT_X86_SSE_CFLAGS")])
AS_VAR_SET_IF([X86_SSE2_CFLAGS], [], [AS_VAR_SET([X86_SSE2_CFLAGS], "DEFAULT_X86_SSE2_CFLAGS")])
AS_VAR_SET_IF([X86_SSE4_1_CFLAGS], [], [AS_VAR_SET([X86_SSE4_1_CFLAGS], "DEFAULT_X86_SSE4_1_CFLAGS")])
+AS_VAR_SET_IF([X86_AVX_CFLAGS], [], [AS_VAR_SET([X86_AVX_CFLAGS], "DEFAULT_X86_AVX_CFLAGS")])
AS_VAR_SET_IF([ARM_NEON_INTR_CFLAGS], [], [AS_VAR_SET([ARM_NEON_INTR_CFLAGS], ["$RESOLVED_DEFAULT_ARM_NEON_INTR_CFLAGS"])])
AC_DEFUN([OPUS_PATH_NE10],
@@ -566,7 +570,24 @@ AS_IF([test x"$enable_intrinsics" = x"yes"],[
AC_SUBST([OPUS_X86_SSE4_1_CFLAGS])
]
)
-
+ OPUS_CHECK_INTRINSICS(
+ [AVX],
+ [$X86_AVX_CFLAGS],
+ [OPUS_X86_MAY_HAVE_AVX],
+ [OPUS_X86_PRESUME_AVX],
+ [[#include <immintrin.h>
+ ]],
+ [[
+ static __m256 mtest;
+ mtest = _mm256_setzero_ps();
+ ]]
+ )
+ AS_IF([test x"$OPUS_X86_MAY_HAVE_AVX" = x"1" && test x"$OPUS_X86_PRESUME_AVX" != x"1"],
+ [
+ OPUS_X86_AVX_CFLAGS="$X86_AVX_CFLAGS"
+ AC_SUBST([OPUS_X86_AVX_CFLAGS])
+ ]
+ )
AS_IF([test x"$rtcd_support" = x"no"], [rtcd_support=""])
AS_IF([test x"$OPUS_X86_MAY_HAVE_SSE" = x"1"],
[
@@ -606,6 +627,19 @@ AS_IF([test x"$enable_intrinsics" = x"yes"],[
[
AC_MSG_WARN([Compiler does not support SSE4.1 intrinsics])
])
+ AS_IF([test x"$OPUS_X86_MAY_HAVE_AVX" = x"1"],
+ [
+ AC_DEFINE([OPUS_X86_MAY_HAVE_AVX], 1, [Compiler supports X86 AVX Intrinsics])
+ intrinsics_support="$intrinsics_support AVX"
+
+ AS_IF([test x"$OPUS_X86_PRESUME_AVX" = x"1"],
+ [AC_DEFINE([OPUS_X86_PRESUME_AVX], 1, [Define if binary requires AVX intrinsics support])],
+ [rtcd_support="$rtcd_support AVX"])
+ ],
+ [
+ AC_MSG_WARN([Compiler does not support AVX intrinsics])
+ ])
+
AS_IF([test x"$intrinsics_support" = x""],
[intrinsics_support=no],
[intrinsics_support="x86$intrinsics_support"]
@@ -672,6 +706,8 @@ AM_CONDITIONAL([HAVE_SSE2],
[test x"$OPUS_X86_MAY_HAVE_SSE2" = x"1"])
AM_CONDITIONAL([HAVE_SSE4_1],
[test x"$OPUS_X86_MAY_HAVE_SSE4_1" = x"1"])
+AM_CONDITIONAL([HAVE_AVX],
+ [test x"$OPUS_X86_MAY_HAVE_AVX" = x"1"])
AS_IF([test x"$enable_rtcd" = x"yes"],[
AS_IF([test x"$rtcd_support" != x"no"],[