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author | Timothy B. Terriberry <territim@amazon.com> | 2022-07-07 01:23:12 +0300 |
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committer | Timothy B. Terriberry <territim@amazon.com> | 2022-07-10 07:18:52 +0300 |
commit | 08088411259056f63774befb2d00951fdd5c46ba (patch) | |
tree | a501ceff6a61d14806d6edc6d38004e96fbeb87d /silk | |
parent | 71fb707875b95672f0cd1cb153c890eff4219720 (diff) |
Only build platform RTCD sources when enabled.
To avoid issues with empty compilation units.
Diffstat (limited to 'silk')
-rw-r--r-- | silk/meson.build | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/silk/meson.build b/silk/meson.build index 70692372..917048b2 100644 --- a/silk/meson.build +++ b/silk/meson.build @@ -21,6 +21,16 @@ endif silk_includes = [opus_includes, include_directories('float', 'fixed')] silk_static_libs = [] +if host_cpu_family in ['x86', 'x86_64'] and opus_conf.has('OPUS_HAVE_RTCD') + silk_sources += sources['SILK_SOURCES_X86_RTCD'] +endif + +if host_cpu_family in ['arm', 'aarch64'] and have_arm_intrinsics_or_asm + if opus_conf.has('OPUS_HAVE_RTCD') + silk_sources += sources['SILK_SOURCES_ARM_RTCD'] + endif +endif + foreach intr_name : ['sse4_1', 'neon_intr'] have_intr = get_variable('have_' + intr_name) if not have_intr |