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AgeCommit message (Collapse)Author
2019-04-09Fix build errors using Makefile.mipsMark Harris
Broken by earlier ARM optimizations.
2016-12-22Fix some compiler warningsMark Harris
2015-10-08Adds "arch" argument to MIPS MDCTRhishikesh Agashe
Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>
2015-10-07Fixes compile problems for MIPSRhishikesh Agashe
Brings MIPS in sync with the ARM/SSE optimizations that added "arch" parameters. Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>
2015-09-02Reorganize x86 SSE intrinsics code.Jonathan Lennox
Enable x86 intrinsics when building in floating-point mode. Support SSE as an arch value. Use RTCD to conditionally enable existing floating-point Celt SSE code. Call functions directly (without RTCD) when their architecture can be presumed. Use SSE4.1 intrinsics optimized code for Silk even in floating-point mode.
2014-12-02Fix celt_pitch_xcorr_c signature.Timothy B. Terriberry
This should not take an arch parameter, so it can properly be used as a fallback for accelerated versions which do not. This patch instead provides a separate version which can call accelerated helpers for platforms that have taken that approach.
2014-10-04There are no tabs in source code.Timothy B. Terriberry
There is also no trailing whitespace.
2014-10-04Cisco optimization for x86 & fixed pointxiangmingzhu
1. Only for fixed point on x86 platform (32bit and 64bit, uses SIMD intrinsics up to SSE4.2) 2. Use "configure --enable-fixed-point --enable-intrinsics" to enable optimization, default is disabled. 3. Official test cases are verified and passed. Signed-off-by: Timothy B. Terriberry <tterribe@xiph.org>
2014-06-20Whitespace fixesexp_mips_optJean-Marc Valin
2014-06-19MIPS optimizationsRhishikesh Agashe
Signed-off-by: Jean-Marc Valin <jmvalin@jmvalin.ca>
2011-04-29Moved all SILK source code to the silk/ directoryJean-Marc Valin
2011-04-25Loss rate adaptation for the CELT layerJean-Marc Valin
2011-03-31draft updateJean-Marc Valin
2011-03-23Build fixesJean-Marc Valin
2011-03-21Making mode switching use the same window as CELT (squared)Jean-Marc Valin
2011-03-18CELT updateJean-Marc Valin
With minor fixes
2011-03-18More project files updateJean-Marc Valin
2011-03-17Fixes a few PLC/DTX bugs due to the recent decode API changeJean-Marc Valin
2011-03-14Adding constrained VBR modeJean-Marc Valin
2011-03-14Draft update (allocationGregory Maxwell
2011-03-12Disable newly introduced CELT signallingJean-Marc Valin
2011-03-10Nothing to see hereJean-Marc Valin
2011-03-09CELT updateJean-Marc Valin
2011-03-08Support for glitchles mode switchingJean-Marc Valin
Uses a 5ms redundant CELT frame embedded into the SILK or hybrid packet to handle the switching. It's still possible to use the PLC-based method when no redundant packet is included.
2011-03-01SILK/CELT updateJean-Marc Valin
2011-02-15preparing the next versionJean-Marc Valin
2011-02-15missing filesJean-Marc Valin
2011-02-15SILK and CELT updatesJean-Marc Valin
2011-02-14Update for in-band FECKoen Vos
2011-02-04draft dateJean-Marc Valin
2011-02-04CELT updateJean-Marc Valin
2011-02-04Tuning the hybrid bit-rate splitKoen Vos
2011-02-04Oops, fixed the CELT versionJean-Marc Valin
2011-02-04Update Opus range coder due to CELT refactoring.Timothy B. Terriberry
The byte buffer is now part of the range coder struct itself, and rangeenc.c and rangedec.c have gone away.
2011-02-03CELT update, version numbersJean-Marc Valin
2011-02-03Build fixesJean-Marc Valin
2011-02-03Oops, had inverted some tuning linesJean-Marc Valin
2011-02-03Hybrid mode tuningKarsten Vandborg Sorensen
2011-02-03CELT updateJean-Marc Valin
2011-02-03Some work on the buildJean-Marc Valin
2011-02-03Enabling the CELT post-filter in OpusJean-Marc Valin
2011-02-02CELT updateJean-Marc Valin
2011-02-02Enabling real CELT VBRJean-Marc Valin
2011-02-01CELT updateJean-Marc Valin
2011-02-01CELT updateJean-Marc Valin
2011-01-31Fixes resampling in CELT-only modeJean-Marc Valin
2011-01-31Merge stereo switching CELT APIJean-Marc Valin
2011-01-31Updated to CELT's new APIJean-Marc Valin
2011-01-22CELT updateJean-Marc Valin
2011-01-18CELT updateJean-Marc Valin
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